JPH0261168B2 - - Google Patents

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Publication number
JPH0261168B2
JPH0261168B2 JP19456784A JP19456784A JPH0261168B2 JP H0261168 B2 JPH0261168 B2 JP H0261168B2 JP 19456784 A JP19456784 A JP 19456784A JP 19456784 A JP19456784 A JP 19456784A JP H0261168 B2 JPH0261168 B2 JP H0261168B2
Authority
JP
Japan
Prior art keywords
transistor
current
modulation
constant
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP19456784A
Other languages
Japanese (ja)
Other versions
JPS6173405A (en
Inventor
Takatoshi Noda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP19456784A priority Critical patent/JPS6173405A/en
Publication of JPS6173405A publication Critical patent/JPS6173405A/en
Publication of JPH0261168B2 publication Critical patent/JPH0261168B2/ja
Granted legal-status Critical Current

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  • Amplitude Modulation (AREA)
  • Control Of Amplification And Gain Control (AREA)
  • Amplifiers (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は変調度一定電流変調回路に係り、特に
集積回路において、電圧信号をバイアス電流に重
量した電流信号に変換する変調度一定電流変調回
路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a constant modulation degree current modulation circuit, and more particularly to a constant modulation degree current modulation circuit that converts a voltage signal into a current signal weighted with a bias current in an integrated circuit. It is something.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

従来電流変調度を一定に保ちながら電流値を3
段階に変化させる変調度一定電流変調回路として
は第5図に示す回路が知られている。
Conventionally, the current value was increased to 3 while keeping the current modulation degree constant.
A circuit shown in FIG. 5 is known as a constant current modulation circuit with a modulation degree that changes in stages.

即ち、差動動作する2個のトランジスタQ1
Q2のそれぞれのコレクタには負荷RL1,RL2が接
続され、ベースを入力電圧信号V3の入力端子と
し、エミツタ間には、接続をスイツチSw1,Sw2
で選択できる2つの抵抗R1,R2が並列に接続さ
れており、また各エミツタは同一電流値を出力
し、しかもこの電流値を選択できる制御端子2を
備えた制御回路1によつて同時に制御される定電
流源I1,I2に接続されるようになつている。
That is, two transistors Q 1 that operate differentially,
Loads RL 1 and RL 2 are connected to the respective collectors of Q 2 , the base is used as an input terminal for input voltage signal V 3 , and switches Sw 1 and Sw 2 are connected between the emitters.
Two resistors R 1 and R 2 that can be selected are connected in parallel, and each emitter outputs the same current value. It is designed to be connected to controlled constant current sources I 1 and I 2 .

次にこの回路の動作を説明すると、入力電圧信
号VsはトランジスタQ1,Q2のエミツタ間に伝え
られ、一方のトランジスタQ1の負荷RL1に流れる
電流iRL1は定電流源I1の電流i1に入力電圧信号Vs
をトランジスタQ1,Q2のエミツタ間の抵抗値で
割つたものに重量した値である。
Next, to explain the operation of this circuit, the input voltage signal Vs is transmitted between the emitters of transistors Q 1 and Q 2 , and the current i RL1 flowing through the load RL 1 of one transistor Q 1 is the current of the constant current source I 1 . Input voltage signal Vs to i 1
is divided by the resistance between the emitters of transistors Q 1 and Q 2 .

即ち、スイツチSw1を閉とした場合iRL1の変調
度は (Vsの振幅/R1)/i1 の式で表わされる。
That is, when the switch Sw1 is closed, the modulation degree of iRL1 is expressed by the formula (amplitude of Vs/ R1 )/ i1 .

この負荷RL1に流れるの電流iRL1のレベルを変
調度一定で増やすためにはスイツチSw2を閉と
し、制御端子2の接続を変更してトランジスタ
Q1の負荷RL1に流れる電流iRL1の変調度が式の値
と等しくなる様に定電流源I1の電流i1を変化させ
ることになる。
In order to increase the level of current i RL1 flowing through this load RL 1 with a constant modulation factor, close switch Sw 2 and change the connection of control terminal 2 to
The current i 1 of the constant current source I 1 is changed so that the modulation degree of the current i RL1 flowing through the load RL 1 of Q 1 becomes equal to the value of the formula.

もう一段レベルを変化させるには、スイツチ
Sw1を閉とし、制御端子2の接続を更に変更して
電流iRL1の変調度が式(1)と等しくなる様にi1を変
化させなければならない。
To change the level one more step, press the switch.
It is necessary to close Sw 1 and further change the connection of control terminal 2 to change i 1 so that the modulation degree of current i RL1 becomes equal to equation (1).

然るにこの回路を集積回路化した場合、第1及
び第2のトランジスタQ1,Q2のエミツタ間に抵
抗R1,R2及びスイツチSw1,Sw2が接続されてい
るため、対称性がくずれており、差動動作回路の
特徴である低歪増幅及び高速動作性が十分に発揮
できない問題点がある。
However, when this circuit is integrated, the symmetry is broken because resistors R 1 and R 2 and switches Sw 1 and Sw 2 are connected between the emitters of the first and second transistors Q 1 and Q 2 . Therefore, there is a problem in that the low distortion amplification and high-speed operation characteristics that are characteristic of differential operation circuits cannot be fully demonstrated.

更に、スイツチSw1,Sw2の部分は配線を伸ば
して集積回路の外部に端子を設けることになるた
め発振等の不安定動作の要因が増すと云う問題点
もある。
Furthermore, since the wiring for the switches Sw 1 and Sw 2 is extended and the terminals are provided outside the integrated circuit, there is a problem that the cause of unstable operation such as oscillation increases.

〔発明の目的〕[Purpose of the invention]

本発明は、上述した諸問題点に鑑みてなされた
ものであり、差動動作性を保持しながら変調度一
定で電流レベルを変えることが可能な変調度一定
電流変調回路を提供することを目的としている。
The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a constant modulation degree current modulation circuit that can change the current level with a constant modulation degree while maintaining differential operability. It is said that

〔発明の概要〕[Summary of the invention]

即ち、本発明は基本的には2個の差動電流変調
回路の並列接続回路であり、差動動作する2個の
トランジスタのベースを入力端子とし、エミツタ
間に抵抗を接続し、それぞれのコレクタに負荷抵
抗を接続し、それぞれのエミツタには同一電流値
を印加すると共に制御回路により動作・非動作が
同時に制御され得る定電流源がそれぞれ接続され
ている第1の差動電流変調回路と、この第1の差
動電流変調回路に2個のトランジスタと2個の定
電流源により第1の差動電流増幅回路と同様に構
成された第2の差動電増幅調回路が並列に接続さ
れた変調度一定電流増幅回路である。
That is, the present invention is basically a parallel connection circuit of two differential current modulation circuits, in which the bases of two transistors operating differentially are used as input terminals, a resistor is connected between the emitters, and the collectors of each transistor are connected in parallel. a first differential current modulation circuit, in which a load resistor is connected to the emitters, and a constant current source that applies the same current value to each emitter and can be simultaneously controlled to be activated or deactivated by a control circuit is connected to the first differential current modulation circuit; A second differential current amplification circuit configured similarly to the first differential current amplification circuit using two transistors and two constant current sources is connected in parallel to this first differential current modulation circuit. This is a constant modulation current amplification circuit.

〔発明の実施例〕[Embodiments of the invention]

次に本発明の一実施例を第1図により説明す
る。但し、従来例と同一符号は同一部を示す。
Next, one embodiment of the present invention will be described with reference to FIG. However, the same reference numerals as in the conventional example indicate the same parts.

即ち、ベースを入力端子とし、それぞれのコレ
クタに負荷抵抗RL1,RL2が接続され、エミツタ
間に第1の抵抗R1が接続され、またそれぞれの
エミツタに定電流源I1,I2が接続されている第1
及び第2のトランジスタQ1,Q2で構成された第
1の差動電流変調回路にベースとコレクタがそれ
ぞれ第1のトランジスタQ1のベースとコレクタ
にそれぞれ共通に接続された第3のトランジスタ
Q3のエミツタと、ベースとコレクタが第2のト
ランジスタQ2のベースとコレクタにそれぞれ共
通に接続された第4のトランジスタQ4のエミツ
タ間に第2の抵抗R2が接続され、それぞれのエ
ミツタには定電流源I3,I4が接続されている。
That is, the base is the input terminal, load resistors RL 1 and RL 2 are connected to the respective collectors, a first resistor R 1 is connected between the emitters, and constant current sources I 1 and I 2 are connected to the respective emitters. The first connected
and a third transistor whose base and collector are commonly connected to the base and collector of the first transistor Q 1 , respectively, to the first differential current modulation circuit composed of the second transistors Q 1 and Q 2 .
A second resistor R 2 is connected between the emitter of Q 3 and the emitter of a fourth transistor Q 4 whose base and collector are commonly connected to the base and collector of the second transistor Q 2 , respectively. Constant current sources I 3 and I 4 are connected to .

このうち、定電流源I1,I2、及びI3とI4は電流
値がそれぞれ等しく、制御端子12を備えた制御
回路11によつて、それぞれの電流源の組は同時
に動作・非動作が制御される。
Among these, the constant current sources I 1 , I 2 , and I 3 and I 4 have the same current value, and each set of current sources is activated and deactivated at the same time by a control circuit 11 equipped with a control terminal 12. is controlled.

また第1及び第2のトランジスタQ1,Q2と第
1の抵抗R1、定電流源I1,I2で構成される第1の
差動電流増幅回路の変調度と、第3及び第4のト
ランジスタQ3,Q4と第2の抵抗R2定電流源I3,I4
で独立に構成される第2の差動電流増幅回路の変
調度は、あらかじめ等しくされている。
Furthermore, the modulation degree of the first differential current amplifier circuit composed of the first and second transistors Q 1 and Q 2 , the first resistor R 1 , and the constant current sources I 1 and I 2 and the third and third transistors 4 transistors Q 3 , Q 4 and second resistor R 2 constant current sources I 3 , I 4
The modulation degrees of the second differential current amplification circuits configured independently are set equal in advance.

次に、本実施例の動作を説明する。 Next, the operation of this embodiment will be explained.

即ち制御回路11により、定電流源I1,I2のみ
の動作が選択されている場合、負荷RL1または
RL2に流れる電流についての変調度は上述した式
で表わされ、バイアス電流はi1である。
That is, when the control circuit 11 selects the operation of only the constant current sources I 1 and I 2 , the load RL 1 or
The degree of modulation for the current flowing through RL 2 is expressed by the above equation, and the bias current is i 1 .

また、定電流源I3,I4のみの動作が選択されて
いる場合、変調度は上述した式に等しく、バイア
ス電流はi3である。
Further, when the operation of only the constant current sources I 3 and I 4 is selected, the modulation degree is equal to the above formula and the bias current is i 3 .

更に定電流源I1,I2及びI3,I4両方の動作が選
択されている場合、その変調度は上述した式に等
しく、バイアス電流はi1+i3である。
Furthermore, when the operation of both constant current sources I 1 , I 2 and I 3 , I 4 is selected, the modulation degree is equal to the above formula and the bias current is i 1 +i 3 .

即ち、制御回路11が、いずれの電流源対の動
作を選択してもバイアス電流が変化するだけで変
調度は一定であり、差動性が保たれた変調度一定
電流変調回路を得ることが出来る。
That is, no matter which current source pair the control circuit 11 selects to operate, the modulation degree is constant only by changing the bias current, and it is possible to obtain a constant modulation degree current modulation circuit that maintains differential properties. I can do it.

次に本発明のそれぞれ異なる変形例を第2乃至
第4図により説明す。但し、実施例と同一符号は
同一部を示し、特に説明しない。
Next, different modifications of the present invention will be explained with reference to FIGS. 2 to 4. However, the same reference numerals as those in the embodiment indicate the same parts, and no particular explanation will be given.

先ず第2図の変形例は、定電流源I1,I2が第1
の抵抗R1の分割点P1とP2にそれぞれ接続され、
第1のトランジスタQ1のエミツタと分割点P1
の抵抗値及び第2のトランジスタQ2のエミツタ
と分割点P2間の抵抗値を等しくしてある。
First, in the modification shown in Fig. 2, the constant current sources I 1 and I 2 are
are connected to the dividing points P 1 and P 2 of the resistor R 1 , respectively,
The resistance value between the emitter of the first transistor Q 1 and the dividing point P 1 and the resistance value between the emitter of the second transistor Q 2 and the dividing point P 2 are made equal.

次の第3図の変形例は、定電流源I3,I4が第2
の抵抗R2の分割点P3,P4に接続され、第3のト
ランジスタQ3のエミツタと分割点P3間の抵抗値
及び第4のトランジスタQ4と分割点P4間の抵抗
値を等しくしてある。
In the following modification of Fig. 3, the constant current sources I 3 and I 4 are connected to the second
is connected to the dividing points P 3 and P 4 of the resistor R 2 , and the resistance value between the emitter of the third transistor Q 3 and the dividing point P 3 and the resistance value between the fourth transistor Q 4 and the dividing point P 4 are They are made equal.

次の第4図の変形例は実施例の回路のNPNト
ランジスタをPNPトランジスタに置き替えた例
である。
The following modification shown in FIG. 4 is an example in which the NPN transistor in the circuit of the embodiment is replaced with a PNP transistor.

〔発明の効果〕〔Effect of the invention〕

上述のように本発明によれば集積化された差動
回路の特徴である低歪動作及び高速動作性を満足
させながら一定変調度でバイアス電流が変えられ
る変調度一定電流変調回路を提供することが出来
る。
As described above, the present invention provides a constant modulation degree current modulation circuit that can change the bias current with a constant modulation degree while satisfying the characteristics of an integrated differential circuit, such as low distortion operation and high-speed operation. I can do it.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す回路図、第2
図、第3図及び第4図はそれぞれ異なる本発明の
変形例を示す回路図、第5図は従来例を示す回路
図である。 1,11……制御回路、2,12……制御端
子、I1,I2,I3,I4……定電流源、Q1,Q2,Q3
Q4……トランジスタ、R1……第1の抵抗、R2
…第2の抵抗、RL1,RL2……負荷。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
3 and 4 are circuit diagrams showing different modifications of the present invention, and FIG. 5 is a circuit diagram showing a conventional example. 1, 11... Control circuit, 2, 12... Control terminal, I 1 , I 2 , I 3 , I 4 ... Constant current source, Q 1 , Q 2 , Q 3 ,
Q 4 ...transistor, R 1 ...first resistor, R 2 ...
...Second resistance, RL 1 , RL 2 ...Load.

Claims (1)

【特許請求の範囲】 1 差動動作する2つのトランジスタQ1,Q2
それぞれのコレクタに負荷RL1,RL2が接続さ
れ、またそれぞれのベースを入力端子とし、更に
それぞれのエミツタは同一電流値を出力すると共
に同時に制御されるそれぞれの定電流源I1,I2
接続され、さらに両方のエミツタ間に第1の抵抗
R1を備えた第1の差動電流変調回路と、ベース
とコレクタが前記第1のトランジスタのベースと
コレクタにそれぞれ共通に接続された第3のトラ
ンジスタQ3のエミツタと、ベースとコレクタが
前記第2のトランジスタQ2のベースとコレクタ
にそれぞれ共通に接続された第4のトランジスタ
Q4のエミツタは、同一電流値をもち、しかも同
時に制御されるそれぞれの定電流源I3,I4に接続
され、更に両方のエミツタ間に前記第3のトラン
ジスタQ3及び第4のトランジスタQ4のコレクタ
電流の変調度が、前記第1の差動電流変調回路の
前記第1のトランジスタQ1と前記第2のトラン
ジスタQ2のコレクタ電流の変調度に等しくなる
値をもつ第2の抵抗R2を備えた第2の差動電流
変調回路と、複数個の制御端子を有し、これら制
御端子の開、閉の選択により前記定電流源I1,I2
の動作・非動作の制御及び前記定電流源I3,I4
動作・非動作の制御を行う制御回路とを具備する
ことを特徴とする変調度一定電流変調回路。 2 定電流源I1が第1の抵抗R1の分割点P1に接続
され、定電流源I2が前記第1の抵抗R1の分割点で
第2のトランジスタQ2のエミツタとの間の抵抗
値が第1のトランジスタQ1のエミツタと前記分
割点P1の間の抵抗値に等しくなる点に接続され
ていることを特徴とする特許請求の範囲第1項記
載の変調度一定電流変調回路。 3 定電流源I3が第2の抵抗R2の分割点P3に接続
され、定電流源I4が前記第2の抵抗R2の分割点で
第4のトランジスタQ4のエミツタとの間の抵抗
値が第3のトランジスタQ3のエミツタと前記分
割点P3の間の抵抗値に等しくなる点P4に接続さ
れていることを特徴とする特許請求の範囲第1項
記載の変調度一定電流変調回路。
[Claims] 1 Loads RL 1 and RL 2 are connected to the respective collectors of two differentially operated transistors Q 1 and Q 2 , each base is an input terminal, and each emitter is connected to the same current. It is connected to the respective constant current sources I 1 and I 2 that output the value and is controlled simultaneously, and a first resistor is connected between both emitters.
a first differential current modulation circuit comprising R 1 and an emitter of a third transistor Q 3 whose base and collector are commonly connected to the base and collector of said first transistor, respectively; A fourth transistor commonly connected to the base and collector of the second transistor Q2 , respectively.
The emitter of Q 4 is connected to respective constant current sources I 3 and I 4 that have the same current value and are controlled simultaneously, and the third transistor Q 3 and the fourth transistor Q are connected between both emitters. a second resistor having a value such that the degree of modulation of the collector current of No. 4 is equal to the degree of modulation of the collector currents of the first transistor Q1 and the second transistor Q2 of the first differential current modulation circuit; A second differential current modulation circuit having R 2 and a plurality of control terminals, the constant current sources I 1 and I 2 can be controlled by selecting whether to open or close these control terminals.
1. A constant modulation degree current modulation circuit comprising: a control circuit that controls operation/non-operation of the constant current sources I 3 and I 4 . 2. A constant current source I 1 is connected to the dividing point P 1 of the first resistor R 1 , and a constant current source I 2 is connected between the dividing point of the first resistor R 1 and the emitter of the second transistor Q 2 . The constant modulation current according to claim 1, wherein the constant modulation current is connected to a point where the resistance value of is equal to the resistance value between the emitter of the first transistor Q1 and the dividing point P1 . Modulation circuit. 3. A constant current source I3 is connected to the dividing point P3 of the second resistor R2 , and a constant current source I4 is connected between the dividing point of the second resistor R2 and the emitter of the fourth transistor Q4 . The modulation factor according to claim 1, characterized in that the modulation factor is connected to a point P4 whose resistance value is equal to the resistance value between the emitter of the third transistor Q3 and the dividing point P3 . Constant current modulation circuit.
JP19456784A 1984-09-19 1984-09-19 Current modulation circuit fixing modulation factor Granted JPS6173405A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19456784A JPS6173405A (en) 1984-09-19 1984-09-19 Current modulation circuit fixing modulation factor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19456784A JPS6173405A (en) 1984-09-19 1984-09-19 Current modulation circuit fixing modulation factor

Publications (2)

Publication Number Publication Date
JPS6173405A JPS6173405A (en) 1986-04-15
JPH0261168B2 true JPH0261168B2 (en) 1990-12-19

Family

ID=16326677

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19456784A Granted JPS6173405A (en) 1984-09-19 1984-09-19 Current modulation circuit fixing modulation factor

Country Status (1)

Country Link
JP (1) JPS6173405A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4282138B2 (en) 1998-10-12 2009-06-17 横浜ゴム株式会社 tire

Also Published As

Publication number Publication date
JPS6173405A (en) 1986-04-15

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