JPH0260381U - - Google Patents
Info
- Publication number
- JPH0260381U JPH0260381U JP13876988U JP13876988U JPH0260381U JP H0260381 U JPH0260381 U JP H0260381U JP 13876988 U JP13876988 U JP 13876988U JP 13876988 U JP13876988 U JP 13876988U JP H0260381 U JPH0260381 U JP H0260381U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- detection
- detection signal
- vertical synchronization
- zero bias
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Liquid Crystal Display Device Control (AREA)
- Transforming Electric Information Into Light Information (AREA)
Description
第１図及び第２図はこの考案の一実施例を示す
もので、第１図は回路構成を示すブロツク図、第
２図は動作の処理内容を示すタイミングチヤート
、第３図は従来の表示信号制御回路の構成を示す
ブロツク図、第４図は第３図の動作内容を示すタ
イミングチヤートである。
１１……１Ｖカウンタ、１２……Ｖ同期修正回
路、１３……Ｖ同期分離回路、１４，２２，２５
……Ｆ／Ｆ、２３……カウンタ。
Figures 1 and 2 show an embodiment of this invention. Figure 1 is a block diagram showing the circuit configuration, Figure 2 is a timing chart showing the processing contents of the operation, and Figure 3 is a conventional display. FIG. 4 is a block diagram showing the configuration of the signal control circuit, and FIG. 4 is a timing chart showing the operation contents of FIG. 11...1V counter, 12...V synchronization correction circuit, 13...V synchronization separation circuit, 14, 22, 25
...F/F, 23...Counter.
Claims (1)
てコモン電圧と同電位の電圧をかけるゼロバイア
ス手段と、 上記検出手段の検出信号に応じて垂直同期信号
の乱れがなくなつた際に上記ゼロバイアス手段の
動作を解除する解除手段と、 を具備したことを特徴とする表示信号制御回路。[Scope of Claim for Utility Model Registration] Detection means for detecting disturbances in the vertical synchronization signal; Zero bias means for applying a voltage of the same potential as the common voltage as a video signal in response to the detection signal of the detection signal; A display signal control circuit comprising: a release means for releasing the operation of the zero bias means when the vertical synchronization signal is no longer disturbed in accordance with a detection signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13876988U JPH0260381U (en) | 1988-10-25 | 1988-10-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13876988U JPH0260381U (en) | 1988-10-25 | 1988-10-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0260381U true JPH0260381U (en) | 1990-05-02 |
Family
ID=31401418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13876988U Pending JPH0260381U (en) | 1988-10-25 | 1988-10-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0260381U (en) |
-
1988
- 1988-10-25 JP JP13876988U patent/JPH0260381U/ja active Pending
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