JPH0260101A - Chip type electronic component - Google Patents
Chip type electronic componentInfo
- Publication number
- JPH0260101A JPH0260101A JP21068688A JP21068688A JPH0260101A JP H0260101 A JPH0260101 A JP H0260101A JP 21068688 A JP21068688 A JP 21068688A JP 21068688 A JP21068688 A JP 21068688A JP H0260101 A JPH0260101 A JP H0260101A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- plated layer
- layer
- resistor
- plating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 63
- 238000007747 plating Methods 0.000 claims abstract description 35
- 230000005496 eutectics Effects 0.000 claims abstract description 13
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 11
- 238000005476 soldering Methods 0.000 abstract description 9
- 239000000919 ceramic Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 239000012298 atmosphere Substances 0.000 abstract description 2
- 238000009736 wetting Methods 0.000 abstract description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 238000002844 melting Methods 0.000 description 8
- 230000008018 melting Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- RVZRBWKZFJCCIB-UHFFFAOYSA-N perfluorotributylamine Chemical compound FC(F)(F)C(F)(F)C(F)(F)C(F)(F)N(C(F)(F)C(F)(F)C(F)(F)C(F)(F)F)C(F)(F)C(F)(F)C(F)(F)C(F)(F)F RVZRBWKZFJCCIB-UHFFFAOYSA-N 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
Landscapes
- Details Of Resistors (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はチップ抵抗、チップコンデンサ等のチップ電子
部品に係り、特にその端子部の表面のはんだメッキ層に
関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to chip electronic components such as chip resistors and chip capacitors, and particularly to a solder plating layer on the surface of a terminal portion thereof.
チップ電子部品のうち、例えばチップ抵抗は、セラミッ
ク基板の表面に抵抗体を形成してなる本体と、この本体
の両端面に被着されて抵抗体に導通している電極部（端
子部）とから構成されており、各電極部の表面にはそれ
ぞれはんだメッキ層が形成されている。そして、かかる
チップ抵抗をプリント配線板に面実装する際には、予め
ペースト状のはんだを塗布しておいたプリント配線板上
のランドに上記電極部を合致させてチップ抵抗を搭載し
た後、リフロー炉等で加熱してはんだ付を行うが、この
とき、上記はんだメッキ層によりはんだ付性、つまりは
んだのぬれ性が確保されるようになっている。Among chip electronic components, for example, a chip resistor consists of a main body formed by forming a resistor on the surface of a ceramic substrate, and an electrode part (terminal part) attached to both end surfaces of the main body and connected to the resistor. A solder plating layer is formed on the surface of each electrode portion. When surface mounting such a chip resistor on a printed wiring board, after mounting the chip resistor by aligning the electrode portion with the land on the printed wiring board to which paste-like solder has been applied in advance, reflow Soldering is performed by heating in a furnace or the like, and at this time, the solder plating layer ensures solderability, that is, solder wettability.
ところで、チップ部品の電極部であるはんだメッキの成
分比は、通常、スズが約９０重量％、鉛が約１０重量％
に設定されているが、このようなはんだをメッキしてな
る従来のチップ電子部品のはんだメッキ層は、スズと鉛
が共晶状態になっていないことから、あまり高温でない
リフローはんだを行う際にはんだのぬれ性が悪がった。By the way, the composition ratio of solder plating, which is the electrode part of chip parts, is usually about 90% by weight of tin and about 10% by weight of lead.
However, in the solder plating layer of conventional chip electronic components made by plating such solder, tin and lead are not in a eutectic state, so it is difficult to perform reflow soldering at a low temperature. Solder wettability deteriorated.
すなわち、従来のチップ電子部品は、２３０℃以上のデ
イツブはんだを行う場合にははんだメッキ層が共晶はん
だとなりやすいことから、良好なはんだぬれ性を確保す
ることが可能であるが、ＩＣ等と一緒に実装するために
２２０℃前後のりフローはんだ、例えばヘーバーフエー
ズはんだを行う場合、はんだメッキ層が共晶はんだとな
らず、スズと鉛が個々にメッキされた状態になっている
ため、はんだのぬれ性が悪かった。その結果、実装時に
ツームストーン現象と称されるチップ立ちが発生したり
、はんだ付不良が起こるなどの不具合があった。In other words, when conventional chip electronic components are soldered at temperatures above 230°C, the solder plating layer tends to become eutectic solder, so it is possible to ensure good solderability. When using flow soldering at around 220°C, such as Heberphase soldering, for mounting together, the solder plating layer is not eutectic solder, but tin and lead are individually plated, so solder wetting may occur. It was bad sex. As a result, there were problems such as chip standing called tombstone phenomenon and soldering failure during mounting.
本発明はこのような事情に鑑みてなされたものであり、
その目的は、はんだメッキ層のはんだぬれ性が良好で、
ペーパーフェーズはんだ等のりフローはんだを行って確
実に面実装できるチップ電子部品を提供することにある
。The present invention was made in view of these circumstances, and
The purpose is to improve the solderability of the solder plating layer,
To provide a chip electronic component that can be reliably surface-mounted by glue flow soldering such as paper phase soldering.
上記目的を達成するために、本発明は、はんだメッキ層
中の鉛の成分比を２５〜４５重量％の範囲内に、つまり
スズの成分比を５５〜７５重量％の範囲内に設定すると
ともに、予め熱処理を施すことによってこのはんだメッ
キ層を共晶はんだにしておく構成とした。In order to achieve the above object, the present invention sets the component ratio of lead in the solder plating layer within the range of 25 to 45% by weight, that is, the component ratio of tin within the range of 55 to 75% by weight. The solder plating layer is made into eutectic solder by performing heat treatment in advance.
すなわち、はんだの融点はスズと鉛の成分比に応じて変
化するので、チップ電子部品のはんだメッキ層として比
較的融点の低いはんだを使用すれば、簡単な熱処理を施
すだけで共晶はんだのメッキ層が得られ、そのため、か
かるはんだメッキ層ははんだのぬれ性が極めて良好とな
り、ペーパーフェーズはんだにおいてもチップ立ち等の
実装不良が起こりにくくなる。In other words, the melting point of solder changes depending on the component ratio of tin and lead, so if a solder with a relatively low melting point is used as the solder plating layer for chip electronic components, eutectic solder plating can be achieved with a simple heat treatment. Therefore, such a solder plating layer has extremely good solder wettability, and mounting defects such as chip standing are less likely to occur even in paper phase solder.
以下、本発明の実施例を図に基づいて説明する。 Embodiments of the present invention will be described below based on the drawings.
第１図は本発明の一実施例に係るチップ抵抗の概略断面
図、第２図はこのチップ抵抗のはんだメッキ層に熱処理
を施している様子を示す説明図、第３図は鉛成分の重量
％とはんだの融点との相関関係を測定した特性図である
。Figure 1 is a schematic cross-sectional view of a chip resistor according to an embodiment of the present invention, Figure 2 is an explanatory diagram showing how the solder plating layer of this chip resistor is heat-treated, and Figure 3 is the weight of the lead component. It is a characteristic diagram which measured the correlation between % and melting point of solder.
第１図において、チップ抵抗ｌは、セラミック基板３の
表面にカーボン等の抵抗体４を形成した本体２と、この
本体２の両端面に被着されて抵抗体４に導通している電
極部５とから主に構成されており、各電極部５はそれぞ
れ、銀やパラジウム等の導電層６の表面に銀くわれを防
止するためのニッケルメッキＮ７を形成し、さらにニッ
ケルメッキ層７の表面にはんだぬれ性を確保するための
はんだメッキＮ８を形成して構成されている。なお、抵
抗体４の表面にはガラス等からなるオーバーコート９が
形成しである。In FIG. 1, a chip resistor l consists of a main body 2 in which a resistor 4 made of carbon or the like is formed on the surface of a ceramic substrate 3, and an electrode part that is adhered to both end surfaces of this main body 2 and is electrically connected to the resistor 4. 5, and each electrode part 5 is formed with nickel plating N7 on the surface of a conductive layer 6 made of silver, palladium, etc. to prevent silver corrosion, and further with a nickel plating N7 formed on the surface of the nickel plating layer 7. A solder plating N8 is formed to ensure solder wettability. Note that an overcoat 9 made of glass or the like is formed on the surface of the resistor 4.
上記はんだメッキ層８は、スズ成分と鉛成分の重量比が
約６：４のはんだをニッケルメッキ層７の表面にメッキ
した後、これを無酸素雰囲気中で２１０℃程度に加熱し
、さらに冷却することにより、共晶はんだとなっている
。すなわち、第３図に明らかなように、鉛成分を４０重
量％含有するはんだの融点は約１９０℃なので、このは
んだを２００℃以上に加熱してやればスズと鉛が共晶状
態となる。また、具体的な熱処理方法は、第２図に示す
ように、ステンレス製のマガジン１０に多数のチップ抵
抗１を装着したものを、フロリナートＦ２０の沸騰直前
の液体１１の中に約５分間浸せきした。The solder plating layer 8 is formed by plating the surface of the nickel plating layer 7 with solder having a weight ratio of tin to lead of about 6:4, then heating it to about 210°C in an oxygen-free atmosphere, and then cooling it. By doing so, it becomes a eutectic solder. That is, as is clear from FIG. 3, the melting point of solder containing 40% by weight of lead component is approximately 190°C, so if this solder is heated to 200°C or higher, tin and lead enter a eutectic state. In addition, as shown in Fig. 2, a specific heat treatment method is as follows: A stainless steel magazine 10 equipped with a large number of chip resistors 1 is immersed in Fluorinert F20 liquid 11 just before boiling for about 5 minutes. .
このように、上記実施例にあっては、チップ抵抗ｌの電
極部５の表面に形成されているはんだメッキ装置が共晶
はんだとなっているため、はんだのぬれ性が極めて良好
で、ヘーパーフエーズはんだにおいてもチップ立ち等の
実装不良が起こりにくくなっている。また、スズ成分と
鉛成分の重量比が約６：４で融点の低いはんだを使用し
ているので、これを共晶はんだにするための熱処理に窒
素雰囲気の炉等の高額な設備を特に必要とせず、単にフ
ロリナートＦ２０に浸せきするだけでよく、そのため安
価かつ容易に所望のはんだメッキ層８を得ることができ
る。In this way, in the above embodiment, since the solder plating device formed on the surface of the electrode portion 5 of the chip resistor l uses eutectic solder, the wettability of the solder is extremely good, and the heperphase solder Also, mounting defects such as chip stand-up are less likely to occur. Additionally, because the weight ratio of the tin component to the lead component is approximately 6:4 and the solder has a low melting point, expensive equipment such as a nitrogen atmosphere furnace is required for the heat treatment to convert it into eutectic solder. Instead, it is sufficient to simply immerse it in Fluorinert F20, and therefore the desired solder plating layer 8 can be obtained easily and inexpensively.
なお、第３図に明らかなように、鉛成分を２５〜４５重
量％（スズ成分を５５〜７５重量％）含有するはんだの
融点は２００℃以下なので、成分比がこの条件を満たす
はんだを使用すれば、上記実施例と同様の熱処理を行っ
て共晶はんだのメッキ層を形成することができる。As shown in Figure 3, the melting point of solder containing 25 to 45% by weight of lead component (55 to 75% by weight of tin component) is below 200°C, so use solder with a component ratio that satisfies this condition. Then, the same heat treatment as in the above embodiment can be performed to form a plating layer of eutectic solder.
また、本発明がチップ抵抗以外のチップ電子部品、例え
ばチップコンデンサ等にも適用できることはいうまでも
ない。It goes without saying that the present invention can also be applied to chip electronic components other than chip resistors, such as chip capacitors.
以上説明したように、本発明によれば、チップ電子部品
の端子部の表面のはんだメッキ層として、スズと鉛の成
分比を適宜選択してな名融点の低いはんだを使用し、こ
れに熱処理を施して共有はんだのメッキ層を得ているの
で、かかるはんだメッキ層ははんだぬれ性が極めて良好
で、ペーパーフェーズはんだにおいてもチップ立ち等の
実装不良が極力回避できる。As explained above, according to the present invention, a low melting point solder with an appropriately selected component ratio of tin and lead is used as the solder plating layer on the surface of the terminal portion of a chip electronic component, and the solder is heat-treated. Since the shared solder plating layer is obtained by applying the following steps, the solder plating layer has extremely good solder wettability, and mounting defects such as chip standing can be avoided as much as possible even in paper phase soldering.
第１図は本発明の一実施例に係るチップ抵抗の概略断面
図、第２図はこのチップ抵抗のはんだメッキ層に熱処理
を施している様子を示す説明図、第３図は鉛成分の重量
％とはんだの融点との相関関係を測定した特性図である
。
ｌ・・・・・・チップ抵抗、２・・・・・・本体、４・
・・・・・抵抗体、５・・・・・・電極部
（端子部）
８・・・・・・はんだメッキ層。
第２図
きよ襲←１（ｐ）Figure 1 is a schematic cross-sectional view of a chip resistor according to an embodiment of the present invention, Figure 2 is an explanatory diagram showing how the solder plating layer of this chip resistor is heat-treated, and Figure 3 is the weight of the lead component. It is a characteristic diagram which measured the correlation between % and melting point of solder. l...Chip resistor, 2...Main body, 4.
...Resistor, 5...Electrode part (terminal part) 8...Solder plating layer. Figure 2 Kiyo attack ← 1 (p)
Claims (1)
層を設けて上記電子素子に導通する端子部を備え、プリ
ント配線板に面実装されるチップ電子部品において、上
記はんだメッキ層中の鉛の成分比が２５〜４５重量％の
範囲内に設定してあるとともに、このはんだメッキ層が
熱処理を施すことによつて共晶はんだとなつていること
を特徴とするチップ電子部品。In a chip electronic component that is surface-mounted on a printed wiring board and has a solder plating layer on the surface of the main body on which an electronic element is provided and a terminal part that conducts to the electronic element, the lead content in the solder plating layer is A chip electronic component characterized in that the component ratio is set within the range of 25 to 45% by weight, and the solder plating layer is made into eutectic solder by heat treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21068688A JPH0260101A (en) | 1988-08-26 | 1988-08-26 | Chip type electronic component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21068688A JPH0260101A (en) | 1988-08-26 | 1988-08-26 | Chip type electronic component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0260101A true JPH0260101A (en) | 1990-02-28 |
Family
ID=16593425
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21068688A Pending JPH0260101A (en) | 1988-08-26 | 1988-08-26 | Chip type electronic component |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0260101A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55124965A (en) * | 1979-03-17 | 1980-09-26 | Pioneer Electronic Corp | Preliminary solder of lead wire with evaporated thin film |
| JPS6223436B2 (en) * | 1980-01-18 | 1987-05-22 | Gen Motors Corp |
-
1988
- 1988-08-26 JP JP21068688A patent/JPH0260101A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55124965A (en) * | 1979-03-17 | 1980-09-26 | Pioneer Electronic Corp | Preliminary solder of lead wire with evaporated thin film |
| JPS6223436B2 (en) * | 1980-01-18 | 1987-05-22 | Gen Motors Corp |
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