JPH026008B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a switch error detection device for setting conditions of an electronic fare scale.

(Prior Art) Conventionally, this type of electronic fare scale has a condition setting switch for setting various conditions, and by operating this condition setting switch, various conditions can be set. I'm going.

(Problems to be Solved by the Invention) In the above-mentioned conventional electronic fare scale, the setting by the condition setting switch may be caused by an erroneous operation when operating the condition setting switch, or due to a failure of the switch due to a disconnection, etc. Even if the conditions have changed from the original specifications intended by the user, the user will not be aware of this, and this may lead to the problem of unknowingly using an electronic price scale that has completely different performance or functions than the user intended. be.

The present invention has been made in view of the above-mentioned problems, and is an electronic rate scale that detects when a preset condition setting switch is used and the specifications are changed due to malfunction of the switch due to a disconnection or the like. An object of the present invention is to provide a switch error detection device for setting conditions.

[Structure of the invention]

(Means for Solving the Problems) The present invention is an electronic device that sets conditions by operating a condition setting switch, and that takes in weight data from a weighing section, performs arithmetic processing, displays the data, etc. based on the set conditions. In the type price scale, there is a condition setting memory that stores setting conditions corresponding to the condition setting switch, a parity memory, and a check data in which the sum of the contents of this parity memory and the condition setting memory is stored in the parity memory. a parity switch that stores a numerical value so that the condition setting memory and the parity memory are the same, and a control means that determines whether the total contents of the condition setting memory and the parity memory are the same as the check data and performs error processing if they do not match. It is equipped with the following.

(Function) In the present invention, the condition setting switch stores the setting conditions in the condition setting memory, and the parity switch stores the setting conditions in the parity memory so that the sum of the contents of the parity memory and the condition setting memory is the same as the check data. Set the numerical value as follows.

Then, the control means determines whether the total contents of the condition setting memory and the parity memory are the same as the check data, and if they do not match, error processing is performed.

(Example) Next, an example of the present invention will be described with reference to the drawings.

Fig. 1 is a perspective view showing the external appearance, in which 1 is a scale stand, 2 is a storage case on which the scale stand 1 is placed and various circuit elements are housed inside, and 3 is a case mounted on the front side of the storage case 2. The keyboard 4 is a display device that is attached to the back of the storage case 2 and has displays 5 and 6 on the front and back sides.

The keyboard 3 has 30 department keys 11 ranging from "01" to "30" and "0" to "30" as shown in FIG.
Ten number keys 12 of "9", a tare key 13, a unit price key 14, an erase key 15, a registration key 16, and a test key 10 are provided.

FIG. 3 is a block diagram showing the circuit configuration. Reference numeral 31 is a central processing unit (hereinafter referred to as CPU) as a control means, which includes an arithmetic circuit, an instruction decoder, a memory control circuit, an accumulator, etc. This CPU 31 is connected to an AD conversion circuit 40 via an address/data bus 32, a ROM 33, a RAM 34, a keyboard controller 35, a display controller 36, a status switch 24, and an I/O port 39. It is also connected to an interrupt controller 41. Then, the ROM is activated according to input signals from keyboard 3, etc.
Predetermined program data is read out from the AD conversion circuit 33 and weighed by a weighing section 43 consisting of a load cell in response to a signal from the interrupt controller 41.
The weight data converted at 0 is taken in, and the display controller 36 is controlled to cause the two displays 44 and 45 on the front and back sides to perform display operations.

The status switch 24 is provided with a status switch 24 for setting a plurality of conditions. This status switch 24 has
Digit processing switch 17 sets whether to round up or round up the last digit and the lowest digit of the price obtained by calculating "weight x unit price", and sets whether to suppress 0 in display etc. 0 suppress switch 1
8. Type-specific switch that allows you to set whether to use the A type with a receipt printer and price lookup (PLU), the B type without a receipt printer, or the C type without a PLU. 19. Specifications for 15 countries. 20 country-specific switches that can be set together, weighing weight 3Kg, 6Kg,
There is a weighing switch 21 for setting the weighing weight to one of three types of 15Kg, and a tare limit switching switch 22 for setting the tare limit to 100% or 5% of the weighing weight. Furthermore, a parity switch 23 for adjusting the parity of the status switch 24 is provided.

Further, each memory shown in FIG. 4 is configured in the RAM 34.

50 is a tare memory for storing the tare amount, 51 is a unit price memory for storing the unit price, 53 is a weight memory for storing the weight, 46 is a net weight memory for storing the net weight, 47 is a price memory for storing the price, 52
Reference numeral 56 represents a departmental memory that stores unit prices, weights, and prices for each department; 56 represents a status memory that stores each setting state corresponding to each status switch 24; A 1-bit digit processing memory 57 stores 0 if the value is rounded off and 1 if the value is rounded off, a 1-bit 0 suppression memory 58 stores 0 if the value is suppressed and 1 if it is not suppressed, and 00 if the type is A. , B
A 2-bit type memory 59 stores 01 for the type and 10 for the C type, a 4-bit country memory 60 stores values that differ depending on the country, for example 0101 for Japan, and a 4-bit country memory 60 for storing 0101 for the weight of 3 kg. 00, 6Kg
2-bit weighing-specific memory 61 that stores 01 for , 10 for 15Kg, 1-bit tare that stores 1 if the tare limit is 100% of the weight, 0.5% if possible, and 1 if possible. A limit specific memory 62 is provided. Also provided is a parity memory 63 that stores 0 or 1 when the parity switch 23 is operated.

Next, the AD conversion circuit 40 will be explained. this
The AD conversion circuit 40 is connected to the power supply 7 as shown in FIG.
2. It has a weighing section 43 consisting of a load cell, a sense amplifier 74, a fine adjuster 75, a zero point adjuster 76, a zero point amplifier 77, a test power supply 78, and a check contact b, and is operated by the test key 10 of the keyboard 3. switch 79, low pass filter 8
0, auto zero controller 81, AD converter 8
2. Consisting of an integrator 83, an auxiliary counter circuit 84, and an auxiliary polarity circuit 85, the I/O port 39
It is connected to the CPU 31 via the CPU 31 and also to the interrupt controller 41. Also,
The auxiliary counter circuit 84 has a first
and second flip-flop 86, 87, 1/4
Frequency divider 88, counter 89, two inverters 9
0, 91, an OR gate 92, and an AND gate 93. In addition, the auxiliary polarity circuit 85
is two flip-flops 9 as shown in FIG.
4,95, a hexadecimal counter 96, and two inverters 97,98.

As shown in FIG. 8, the AD converter 82 receives a weight signal which is converted into a voltage value by the weighing section 43 and inputted via a low-pass filter 80, an auto-zero amplifier 77, a power supply 72, a sense amplifier 74, and fine adjustment. and a reference signal inputted through the device 75.
The weight signal is converted into count data of -30000 to 30000 and output.

The count data is the value obtained by performing double integration using the input weight signal and reference signal to form the COMP signal shown in Fig. 9, and counting the clock signal of this COMP signal with a φ ₂ t period of 200 KHz using a counter. It is.

In addition to the count data, the AD converter 82 outputs a polarity signal indicating whether the count data is positive or negative, a strobe signal serving as an interrupt signal, and whether the count data is -30000 or less or
When the weight signal is 30,000 or more, an over signal is output, and a COMP signal as a comparison signal obtained by doubly integrating the weight signal and the reference signal, a Busy signal and a D5 signal that are output for the same period as the COMP signal are output. These signals are output at the timing shown in FIG. Five strobe signals are output at internal timing φ ₀ , and in synchronization with this strobe signal ^, the 10 ⁴ digit, 10 3 digit, 10 ² digit, and 10 ¹ digit of the count data are output as shown in Figure 10. , 10 ⁰ digits are output in sequence, and at the same time a polarity signal or an over signal is output. Next, the COMP signal and the Busy signal are output at internal timings _φ1 and _φ2 . Note that the COMP signal becomes a negative signal when the count number is positive, and becomes a positive signal when it is negative. In addition, 16 D5 signals are output during each φ _i (i=0 to 3) period.

Next, the auxiliary counter circuit 84 will be explained.
This auxiliary counter circuit inputs the strobe signal and Busy signal from the AD converter 82, and
Operates by inputting a 200KHz clock signal. First, the first flip-flop 86 is set by one strobe signal and the counter 89 is reset. However, the previous count data latched at this time remains without being reset.
Furthermore, the second flip-flop 87 is set while the strobe signal is being input, so it is 1/1/2.
Reset the 4-frequency divider 88. Therefore, no signal is input to the SiN input for carrying up the count data output by the counter 89. When the first strobe signal ends, the second flip-flop 87 is reset by the clock signal, so the 1/4 frequency divider 88 is also activated by the clock signal.
Four signals are input to the SiN input of the counter 89. This state is shown in FIG. Due to these four signals, the counter 89, which had been outputting the 10 ⁴ digit data of the count data that had been latched up to that point, now outputs the 10 ⁶ digit data. In this way, similarly to the AD converter 82, the count data's 10 ⁴ digits, 10 ³ digits, 10 ² digits,
Outputs data of 10 ^1s digits and 10 ^0s digits. This state is shown in FIG. Next, when the internal timing of the AD converter 82 reaches _φ1 , a Busy signal is input from the AD converter 82. Then the first flip-flop 8
6 is reset, the reset of the counter 89 is released, and counting operation starts from this point. When the falling signal of the Busy signal is input to the TRF input for latching count data, this count data is latched and transferred to the latch register in the counter 89. Then, when the internal timing signal of the AD converter 82 is φ ₀ and the strobe signal is input again, the data in the latch register is sequentially output digit by digit in the same manner as described above. Note that the count number _of this auxiliary counter circuit 84 is between φ ₁ + _{φ 2} t as shown in FIG.
Count data with a large number of counts will be output.

Next, the auxiliary polarity circuit 85 will be explained. This auxiliary polarity circuit 85 is the AD converter 8
It operates by inputting the Busy signal from 2 to 2, the D5 signal that is output 16 times during internal timing _φi , and the COMP signal for comparison, as well as inputting a 200KHz clock signal. The hexadecimal counter 96 operates while the Busy signal is input, and when 16 D5 signals are input, a signal is output from the hexadecimal counter, and at this point, the internal timing of the AD converter 82 is at the boundary between φ ₁ and φ ₂ It inputs and latches the COMP signal, and outputs a polarity signal according to this COMP signal.

Next, the display controller 36, as shown in FIG. It is composed of a data receiver 104.

This display controller operates the address selector 97 according to the count output of the 20-decimal counter 98.
control and display corresponding to the count number
Segment data is inputted to the segment driver 102 from the address of the RAM 105, and displayed according to the segment data on the front and back displays 5 and 6 via the segment check circuit 103. At this time, at the same time, the digit corresponding to the count on both the displays 5 and 6 is controlled by the digit decoder 100 and the digit driver 101 in accordance with the count output of the 20-decimal counter 107, and the segment data is stored in this digit position. Display will be made accordingly. Furthermore, at the same time as being displayed on the displays 5 and 6, the segment data and count outputs of both the displays 5 and 6 are outputted via data receivers 99 and 104.

Next, the operation of this scale will be explained based on the flowcharts shown in FIGS. 15 to 20.

FIG. 15 is a main flowchart. When the power is turned on at step 111, initial processing such as RAM clearing is performed. Next, at 112, the status switch 24 is initialized to a predetermined position, for example, the digit processing switch 17 is set to round up, the 0 suppress switch 18 is set to 0 suppressed, the type switch 19 is set to B type, the country switch 20 is set to Japan, and the weighing switch is set to When the switch 21 is set to 6 kg and the tare limit changeover switch 22 is set to 100% of the weighing weight, the status memory 56 of the RAM 34 stores each bit according to the combined position of the status switch 24 and parity switch 23. 0 or 1, for example, 0 in the digit processing memory 57, 0 in the 0 suppression memory 58, 01 in the type-specific memory 59, etc.
0101 is in the country memory 60, and 0101 is in the weighing memory 61.
01 is stored in the tare limit memory 62.
Note that at this time, the total of all bits in the status memory 24 and parity memory 23 is an even number.
Note that the reason why the sum of the contents of the status memory 56 and the parity memory 63 is an even number is to perform an even parity check, which will be described later.When performing an odd parity check, the contents of the status memory 56
and the total content of the parity memory 63 is set to be an odd number.

Next, if the unit price for each department is set in the department memory 52 by operating the department key 11 and number key 12, this is preset. Note that since the contents of the departmental memory 52 are held by an auxiliary power source (not shown), the setting operation need only be performed when the contents of the departmental memory 52 are to be changed.

Next, it is determined whether or not there is a key-in, and if there is a key-in, key processing is performed in step 113. If there is no key-in, the weight data is read from the weight memory 53 in step 114, the tare amount stored in the tare memory 50 of the RAM 34 is subtracted from this weight data to calculate the net weight, and this value is stored in the net weight memory 53. Transfer to. Next, 115 is the net weight and
The unit price stored in the unit price memory 51 of the RAM 34 is multiplied to calculate the price, and this value is transferred to the price memory. When this is completed, the CPU 31 is checked in step 116. This CPU check is 115
The weight is calculated by reversing the calculation performed in step 115, that is, dividing the price calculated in step 115 by the unit price. Next, compare this weight with the net weight above, and if they are the same, the CPU
31 is normal, and if they are not the same, the CPU 31 determines that it is abnormal. And if CPU31 is abnormal, 11
At step 7, 50 is assigned to AC0 of the accumulator shown in FIG. 14, and after AC1 to AC9 are cleared to F, at step 118, the subroutine shown in FIG. 17 display 2 is executed. This subroutine is executed in ROM3 as shown in Figure 14.
3 segment decoder to accumulator AC0
～Read the 8-bit segment data corresponding to the contents of AC9 and set it to DSP00 of the accumulator～
Assign to the corresponding location of DSP19. When this is completed 20 times, that is, 20 digit segment data is input to DSP00 to DSP19 of the accumulator, CPU 3
1 outputs a blanking signal. Then, this blanking signal causes the address selector 106 shown in FIG. 13 to operate, and the display RAM 10
Data in DSPi is transferred to address i (i=0 to 19) of 5. When the transfer is completed, the blanking signal is reset, the display controller 36 leaves the control of the CPU 31, and under the control of the 20-decimal counter, the front and back displays 5 and 6 are set to 50 by the segment data in the display RAM 105.
Display. And stop. If it is normal, go to 119 and change the price to match the currency unit. This means, for example, changing the price from $1.72 to $1.72.

Next, the ROM 33 is checked at 120. This is because the 2FFF address is adjusted in advance so that if you add all the contents from address 0 to 2FFF of ROM 33 of 12 Kbyte, the result will be 0, so 120 is adjusted from address 0 of ROM 33 to address 2FFF.
Add all contents up to address 2FFF. If the calculation result is 0, it is determined that it is normal, and if it is not 0, it is determined that it is abnormal. And if ROM33 is abnormal, 1
21 Substitute 70 for AC0 of the accumulator, and AC1~
After clearing AC9 to F, the routine of display 2 shown in FIG. 17 is executed at 122 to display 70 on both displays 5 and 6. And stop. If it is normal, the subroutine of display 1 shown in FIG. 18 is executed in step 123.

In this display 1, first, 123-1 sets the tare memory 5 to AC0 to AC1 of the accumulator shown in Fig. 14.
Save the tare weight within 0 to AC2 to AC4 in net weight memory 4
6, the unit prices in the unit price memory 51 are substituted into AC4 to AC6, and the values in the price memory 47 are substituted into AC7 to AC9. Next, in step 123-2, segment data corresponding to the ACi data is read from the two segment decoders in the ROM 33. Compare two segment data for equality. If they are not equal, assign 10 to AC0 of the accumulator, clear F of AC1 to AC9, and then perform the subroutine of display 2,
Display 70 on both displays 5 and 6. Then stop. If they are equal, the read segment data is substituted into the corresponding location of DSPi of the accumulator in step 123-4 as shown in FIG. 20 of this
Repeat for 20 digits. 12 if completed 20 times
A blanking signal is output at 3-5. When this blanking signal is output, the CPU
31, the segment data of the DSPi is transferred to address i of the display RAM 96. When this transfer is completed, the 123-7 blanking signal is reset. Then display controller 3
6 leaves the control of the CPU 31 and enters the 2decimal counter 107.
The output of the digit decoder 100 and the address selector 106 are controlled by the digit driver 101.
is driven to determine the digit, and for each digit, the address selector 106 operates to select the display RAM 1.
Segment data is sent to the segment driver 102 from the corresponding address of 05, and this segment driver 102 is driven to display the display devices 5 on both the front and back sides.
6.

At this time, the CPU 31 substitutes the digit return signal outputted from the 2decimal counter 107 via the data receiver 99 into the accumulator ACC1 at 123-8. Then, determine whether the content of ACC1 is 0 or not, and if it is not 0, return to 123-8 and 0
Repeat this until. If it is 0, then 123-
At step 9, the segment check circuit 103 transfers the two segment data displayed on the front display 5 and back display 6 to the data receiver 104 when the 20-decimal counter 107 is outputting 0.
Enter via. Then, it is determined whether these two segment data are the same. If they are not the same, use 123-10 to assign 15 to AC0 of the accumulator, clear F from AC1 to AC9, and then use 123-11.
The display 2 subroutine is executed and 15 is displayed on the displays 5 and 6 on both the front and back sides. And stop. If they are the same, then the segment data from the front display 5 at this time, that is, when ACC1=0, is compared with the segment data in DSP00 of the accumulator to determine whether they are the same. If they are not the same, use 123-12 to assign 16 to AC0 of the accumulator, and after clearing F for AC1 to AC9, use 123-13.
The display 2 subroutine is executed and 16 is displayed on both front and back displays 5 and 6. And stop. If they are the same, it is determined whether the digit return signal has changed. If it hasn't changed, wait until it does. Once changed, the contents of ACC1 of the accumulator are transferred to ACC2 in steps 123-14, and the changed new digit return signal is assigned to ACC1. Next, it is determined whether the contents of ACC1 have been added to the contents of ACC2 by 1 or whether they are 0. If 1 has not been added, 14 is assigned to AC0 of the accumulator at 123-15, and after F clearing AC1 to AC9, the display 2 subroutine is executed at 123-16, and 14 is displayed on both front and back displays 5 and 6. . And stop. It is determined whether the digit return signal of ACC1 is 0 or not by adding 1, and if it is not 0, the process returns to 123-9, and this process is repeated 20 times to check all 20 digits. Then, when the output of the 20-decimal counter 98 becomes 0 again and the digit return signal of ACC1 becomes 0, the program returns to the main routine and proceeds to the next step. Next, at 124, the status switch 24 is checked. This check of the status switch 24 is an even number parity check, in which the contents of the status memory 56 and the parity memory 63 are read and summed, and it is determined whether or not this total value is an even number, which is check data. If the number is not even, 40 is assigned to AC0 of the accumulator at 125, F is cleared for AC1 to AC9, and then the subroutine of display 2 is executed at 126, and the front and back side displays 5 and 6 are displayed.
Display 40. However, in this case, after displaying the error number in the display 2 subroutine, the process does not stop and returns to C. Here, it is sufficient to correct the status switch 24 that has been operated by mistake, or to repair a malfunction of the switch due to a disconnection or the like. If the number is even, return to B. Then repeat this.

Also, a case in which a key-in of the main routine occurs will be explained.

First, when the tare key 13 is pressed, the contents of the weight memory 53 at this time are transferred to the tare memory 50 and the process returns to B.

Further, when the department key 11 is pressed, the contents of the department memory 52 corresponding to the pressed department key 11 are transferred to the unit price memory 51 and the process returns to B.

Also, when the registration key 16 is pressed, the contents of the net weight memory 46 are added to the weight of the department memory 52 called up with the department key 11, the contents of the price memory 47 are added to the price, and at the same time, the contents of the total memory 46 The contents of the net weight memory 46 are added to the weight, and the contents of the price memory 47 are added to the price. Then return to B.

During execution of this main routine, when a strobe signal is input from the AD conversion circuit 40 to the CPU 31 via the interrupt controller 41,
The CPU 31 stops executing the main routine and executes the weight data interrupt routine shown in FIG. This transmits count data and polarity data from the AD converter 82, count data from the auxiliary counter circuit 84, and polarity data from the auxiliary polarity circuit 85 to the CPU 31.
Import into. Next, it is checked whether the polarity data from the AD converter 82 and the polarity data from the auxiliary polarity circuit 85 are the same. If they are not the same, assign 24 to AC0 of the accumulator,
After clearing AC1 to AC9, the subroutine for display 2 shown in Fig. 17 is executed, and both front and back displays 5 and 6 are displayed.
24 is displayed. And stop.

Also, if the polarity data is the same,
Make data so that the measured weight data and count data are proportional. First, if the polarity data is positive, 30,000 is added to the count data from the AD converter 82, and 19,999 is added to the counter data from the auxiliary counter circuit 84. If the polarity data is negative, the count data of the AD converter 82 is subtracted from 30000, and the count data of the auxiliary counter circuit 84 is subtracted from 40001. Next, the count data from the AD converter 82 after data making is compared with the count data from the auxiliary count circuit 84. If both count data are not the same, assign 24 to AC0 of the accumulator,
After clearing AC1 to AC9 F, the first
The display 2 subroutine shown in FIG. 7 is executed, and 24 is displayed on both front and back displays 5 and 6. And stop.

If they are the same, the count data is converted to weight data after performing known flicker prevention processing and auto-zero processing. This ends the weight data interrupt routine and returns to the point where the main routine left off.

The AD converter 40 can be checked by a manual check in addition to the polarity data and count data check routine shown in FIG. This is done by pressing test key 10 during key processing.
This is done by switching the switch 79 of the AD conversion circuit 40 from a to b. switch 79 a
When switching from to b, the same voltage as when 90% of the weighed weight is placed on the weighing section 43 is input to the AD converter 82 regardless of the weight placed on the weighing section. For this reason, press test key 10 and switch 7.
When 9 is switched from a to b, the AD converter 82, auxiliary counter circuit 84 and auxiliary polarity circuit 85
The count data and polarity data corresponding to 90% of the weighing amount are outputted, and the interrupt routine and main routine shown in FIG. , 6Kg total is 5.4Kg, 15Kg
If it were a total weight, it would display a weight of 13.5Kg. If the weight is displayed differently from the above weight, the sense amplifier 74, fine adjuster 75, low pass filter 80, auto zero amplifier 77, auto zero controller 81, AD converter 82, integrator 8
This indicates that one or more of 3 is not operating normally. Please note that this check only
Unlike other checks, this is a manual check that the user visually performs.

Next, RAM check will be explained.

In this RAM check method, when data is transferred to the RAM 34, the data is read again from the RAM 34 and the transferred data is compared with the data read from the RAM 34. If it is the same, RAM3
4 is normal, and if they are not the same, the RAM 34 is abnormal. And if it is abnormal, check the accumulator.
After assigning 60 to AC0 and clearing AC1 to AC9 to F, the display 2 subroutine shown in FIG. 17 is executed to display 60 on both front and back displays 5 and 6. And stop. If normal, proceed to the next program.
Although this check of the RAM 34 is not shown in each flowchart, it is always performed when data is transferred to the RAM 34 or when data from one address of the RAM 34 is transferred from another address.

Note that in the above embodiment, the status switch 24
Although the error check is an even parity check, it can also be an odd parity check.

〔Effect of the invention〕

According to the present invention, by determining whether the total contents of the condition setting memory and the parity memory are the same as the check data and performing error processing if they do not match, the preset condition setting switch is When using an electronic price scale, it is possible to detect cases where the specifications have changed due to incorrect operation of a condition setting switch that does not require operation or a switch failure due to a disconnection, etc., so that the performance and functions of the electronic price scale do not exceed the user's intended specifications. There is no difference from the specifications.

[Brief explanation of drawings]

Fig. 1 is a perspective view showing the external appearance of an electronic fare scale according to an embodiment of the present invention, Fig. 2 is a plan view showing the keyboard, Fig. 3 is a block diagram showing the circuit configuration, and Fig. 4 is the RAM memory. Configuration diagram, Figure 5 is a block diagram of the AD conversion circuit, Figure 6 is a circuit diagram of the auxiliary counter circuit, Figure 7 is a circuit diagram of the auxiliary polarity circuit, and Figure 8 is a circuit diagram of the auxiliary polarity circuit.
The figure is a characteristic diagram of the input voltage and count number of the AD converter, Figure 9 is a timing diagram of the AD converter's internal timing signal and each output signal, and Figure 10 is the output of the AD converter's strobe signal and count data signal. Timing diagram: Figure 11 is a timing diagram of the clock signal and SiN input signal in the auxiliary counter circuit; Figure 12 is a timing diagram of the strobe signal, SiN input signal, and counter data output signal;
Figure 13 is a block diagram showing the circuit configuration of the display controller, and Figure 14 shows the accumulator ACi.
DSPi correspondence diagram, Figures 15 and 16 are main flowcharts, Figure 17 is a flowchart showing error display processing,
18 and 19 are flowcharts showing display error check processing, and FIG. 20 is an interrupt flowchart showing error check processing of the AD conversion circuit. 23...Parity switch, 24...Status switch as a condition setting switch, 31...
...CPU, 43...Weighing unit, 56...Status memory as memory for setting conditions, 63...Parity memory.

Claims (1)

[Scope of Claims] 1. In an electronic price scale that sets conditions by operating a condition setting switch, and performs loading, arithmetic processing, and display of weight data from a weighing section based on the set conditions, the following conditions apply: A condition setting memory that stores setting conditions corresponding to the setting switch, a parity memory, and a parity memory so that the sum of the contents of the parity memory and the condition setting memory is the same as the check data. The present invention is characterized by comprising a parity switch for storing numerical values, and a control means for determining whether the total contents of the condition setting memory and the parity memory are the same as the check data, and performing error processing if they do not match. A switch error detection device for setting conditions for electronic fare scales.