JPH0260018B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] When multitasking is performed in a multiprocessor system, the execution order of each procedure (process) and the synchronization of data transfer to each processor are controlled using a dependency flow format. Data is used to efficiently execute data using a dedicated processor and storage means.

[Industrial application field]

The present invention relates to an information processing device,
In particular, it relates to multitasking technology in multiprocessor systems.

[Background of the invention]

In recent years, vector processing device 4 and later, VP
Multitasking processing using a system with a multiprocessor configuration (represented by ) is attracting attention. This means that in order to meet the demands of large-scale scientific calculations, a single processor system is required.
This is because no significant performance improvement can be expected.

For this reason, a multitasking method has been considered in which one task is divided into multiple processes and these processes are executed by multiple processors VP.

When performing multitasking, synchronization between processes becomes a particularly important issue. That is,
It is necessary to allocate execution of a plurality of processes to each processor in accordance with a predetermined temporal order (synchronization) and with little overhead.

Next, the concept of multitasking will be explained with reference to FIG.

In the figure, one task denoted by a is b
The process is divided into eight processes (procedures) from process 1 to process 8 shown in FIG. 1 to enable multitasking by a plurality of processors.

In this example, process 2 to process 5
cannot be executed in parallel with process 1 because it uses the execution result of process 1.

Similarly, process 6 and process 7 can wait for the completion of execution of process 2, process 3, process 4, and process 5, respectively, and then start execution, and process 8 can wait for the completion of execution of process 6 and process 7, respectively. You can wait and start execution.

Here each process has the same execution time and
Assuming there is no overhead for synchronizing processes, if the eight processes shown in Figure 6b are executed on four processors, the horizontally aligned processes can be processed concurrently. Therefore, the execution time can be halved compared to a single processor.

By the way, in multitasking where there are execution dependencies between a plurality of processes, control of the execution order, that is, synchronization control is generally required.

[Conventional technology]

A conventional example of a synchronization method in multitasking will be described next.

Multitasking is not common in general-purpose computers, and each processor in a multiprocessor executes an independent task. Of course, there are times when it is necessary to synchronize the processors, but in this case this is done by interlocking a part of the main memory.

Denel Core's HEP has a semaphore bit corresponding to each piece of data in main memory. If the semaphore bit is 0, writing is permitted but reading is not permitted, and if the semaphore bit is 1, the reverse is true. By controlling this semaphore bit, it is possible to
Performs READ/WRITE order control.

In Cray's CRAY-XMP, HEP
The system has something equivalent to a semaphore bit in a register. Processor data can also be transferred using registers. The idea is the same as the HEP method, but since it is performed using registers, faster operation is possible.

[Problem that the invention seeks to solve]

The present invention seeks to provide a procedure dispatch method in a high performance multiprocessor system that has a more efficient synchronization method than the conventional synchronization method between processors in multitasking.

[Means for solving problems]

The present invention uses a dependency flow (DEPENDENCY flow) to dispatch multiple procedures having a fixed execution order relationship to multiple processors.
FLOW).

Dependency flow is a control flow type program in which multiple control steps in a dependent relationship are chained according to the execution order.
Each control step of the flow is activated upon completion of all one or more preceding control steps to which it has predefined dependencies.

In the present invention, the execution steps of a plurality of procedures are expressed in a dependency flow format and stored in a storage means, and a processor for dispatch control is used to access the storage means and execute executable procedures. It sequentially detects them and issues an execution instruction to the processing processor, that is, a dispatch.

FIG. 1 shows the principle of the present invention using one embodiment. In the figure, 10-1 to 10-n are first processing devices that divide and execute a plurality of procedures constituting each task, and correspond to, for example, processor elements PE of a multiprocessor system.

11-1 to 11-n are main storage units of the first processing units 10-1 to 10-n, respectively (later abbreviated as MSU). Note that the main storage unit (MSU) may be shared by a plurality of first processing devices. Generally, a group of one or more first processing devices in each main storage unit is called a subsystem.

Reference numeral 12 denotes an execution procedure storage means (later abbreviated as DFM) that stores the execution procedures of a plurality of procedures constituting a task in the form of dependency flow data.

13 has a function of reading the execution procedure of the dependency flow data from the execution procedure storage means 12 and instructing the first processing device to execute the execution procedure that has become executable; This is a second processing device for multitasking control (later abbreviated as DFP) that has the function of instructing the storage control device to transfer data between the two.

14 is a mass storage unit of the multiprocessor system (later abbreviated as CSU).

15 transmits an execution instruction from the second processing device 13 to each first processing device, and main storage devices 11-1 to 11-n of any of the first processing devices 10-1 to 10-n to which execution instructions have been given. This is a storage control unit (later abbreviated as CMU) that controls the connection between the storage device 14 and the mass storage device 14.

[Effect]

In FIG. 1, the execution steps between multiple procedures constituting a task are converted into dependency flow data by a compiler, and
It is stored in the execution procedure storage means 12 in advance.

Each procedure in the dependency flow becomes executable upon completion of execution of each preceding procedure for which a dependency relationship is defined as an executable condition.

For this reason, the data in the execution procedure storage means 12 holds, for each procedure, information indicating the execution completion status of preceding procedures that have a dependent relationship. The information is updated by the second processing device based on the notification.

In response to the execution completion notification from the first processing device, the second processing device checks the feasibility of executing a procedure subordinate to the executed procedure, and if it is executable, it sends a predetermined first processing device to execute the procedure. instruct the
Furthermore, it is possible to instruct the storage control device 15 to transfer data.

The above control is performed according to the dependency flow data stored in the execution procedure storage means 12.

〔Example〕

FIG. 2 shows the configuration of one embodiment of the execution procedure storage means 12 and the second processing device 13 in the basic configuration of the present invention shown in FIG. In the figure, 120 is a dependency flow memory (hereinafter referred to as "execution procedure storage means 12" in FIG.
(abbreviated as DFM), in which the compiler writes the execution order of each process in which a task is divided into multiple processes in a dependency flow data format.

130 is a dependency flow processor (hereinafter referred to as DFP) corresponding to the second processing device in FIG.
).

131 is a data queue holding unit;
This is a buffer that temporarily holds data sent from the storage control unit 15CMU shown in the figure in order to write it to the DFM.

132 is a token and address queue holding unit, which is a buffer that temporarily holds an address for accessing the DFM. Process execution completion notification is performed using a token.

Reference numeral 133 denotes an firing detection unit, which checks whether the process read out as a result of accessing the DFM has fired (becomes executable).

134 is a DFP controller, and when a process read from DFM is fired,
Control operations are performed according to the contents of data read out about the process from the DFM.

135 is an interrupt controller, and DFP
According to instructions from the controller 134, the first processing devices 10-1 to 10-n shown in FIG.
Sends an interrupt signal to the corresponding one (represented by PE0 to PEN).

A selector 136 selects a token address and a token value (described later) output from each of the first processing devices 10-1 to 10-n (represented by PE0 to PEN).

FIG. 3 shows the data format of data constituting the dependency flow stored in the DFM.

In the figure, 30 is a token value for detecting satisfaction of firing conditions. Each time a token indicating completion of execution is input, the initial value is sequentially incremented by 1 and compared with the firing value. For example, a 4-bit value "1111" is used as the firing value.

31 is the initial value of the token value. For example, if you want to fire on the condition that three events occur,
The binary value "1100", which is the value 12 obtained by subtracting 3 from the token value 15, is set. This initial value is transferred to the token value, which is incremented by 1 each time the execution of the aforementioned predetermined preceding process is completed, and when it matches the firing value "1111", firing is determined.

32 is an OP code indicating control content.

33 is a flag indicating modification/information of the OP code 32.

34 is the number of the first processing device to be requested to execute the process (represented by PE NO). 35 is an interrupt code. When each first processing device receives an interrupt request from the DFP,
This interrupt code determines the type of interrupt.

36 and 37 are DFM addresses, which are used when it is necessary to access other data in the DFM again, for example, when dispatching multiple synchronized processes to multiple first processing units. Used as a chain.

38 is data transfer instruction information;
When data needs to be transferred between the first processing unit designated by PENO and the mass storage unit CSU of FIG. 1, the storage control unit CMU is notified.
This information includes the address of the mass storage device CSU where the details of the data transfer are stored.

Next, the general operation of the embodiment shown in FIG. 2 will be described with reference to FIGS. 1 and 3 as well.

Process execution completion notifications from each first processing unit PE to DFP, or other requests to DFP, are made using a token with a DFM address, and stored in the token and address queue holding unit 132 via the selector 136. (Details will be described later with reference to FIG. 4).

Token and address queue holding unit 132
If there is a notification or request within, then the DFM is accessed using that address.

The data read from the DFM (see Figure 3) is
The signal is sent to the ignition detection section 133.

The firing detection unit 133 increments the token value of the read data by 1 and checks whether it is equal to the firing value "1111".

If the result does not reach "1111", the value added by 1 to the token value is written as a new token value in DFM. In addition, if the above +1 value is equal to the ignition value "1111", it will be considered as ignition,
The remaining data excluding the token value and the initial value of the token value in the data in FIG. 3 is transferred to the DFP controller 134, and the initial value is written in the token value of the DFM data.

The DFP controller 134 includes the ignition detection unit 13
Based on the OP code and flag information in the data transferred from 3, the process to be executed is determined and the instructed process is started. Next, some processing examples are shown.

For example, when continuation of DFP processing is instructed, such as when dispatching multiple processes in synchronization, the DFM address in the data is sent to the token and address queue holding unit 132 via the access 136. , DFM again
, and repeat the above operation.

In addition, if data transfer is instructed,
As mentioned above, the data transfer instruction information (38 in FIG. 3) is sent to the storage control unit CMU in FIG.
Request processing.

As a result, the CMU uses the CSU address in the data transfer instruction information to retrieve information such as the CSU start address, operation code, MSU start address, and data transfer length required for data transfer from the CSU, and then issues an instruction. data transfer.

As another example, the CSU start address, operation code, MSU start address, and data transfer length are directly set in the data transfer instruction information 38 in FIG. 3, and when the CMU receives this information, , it is also possible to start the data transfer process immediately.

Furthermore, if an interrupt to the first processing device is instructed, the PE NO and interrupt code in the data are sent to the interrupt controller 135;
Request processing.

When the interrupt controller 135 receives the interrupt processing request, it sends an interrupt signal to the first processing device of the specified PE NO.

In this way, DFP can manage and synchronously control the execution order and data transfer order of multiple processes.

FIG. 4 shows an example of controlling the dependency flow data and dispatch within the DFM. The illustrated example shows four pieces of data at addresses A, B, C, and D.

The data at address A indicates that the first processing device PE2 is requested to execute process 2, and that it is chained to the data at addresses B and C.

The data at address B indicates that execution of process 3 is requested to the first processing device PE3 and that it is chained to the data at address D.

The data at address C indicates that execution of process 4 is requested to the processing device PE4.

The data at address D indicates that execution of process 5 is requested to first processing device PE5.

Note that the token value of each data at addresses A, B, C, and D is set to "14".

Here, when the execution of process 1 by PE1 is completed, PE1 notifies DFP of the DFM address A and the token. As a result, the data at address A is accessed, and its token value is incremented by 1 to become "15", which causes a fire to be sent to PE2 in process 2.
An execution instruction is given.

Subsequently, those data are also accessed by the chained addresses B and C, their respective token values are incremented by 1 and fired, and PE3 and PE4 are instructed to execute processes 3 and 4, respectively.

Further, the data at address D, which is chained from the data at address B, is accessed, which also fires, and the PE 5 is instructed to execute process 5.

In this way, processes 2 to 5 can be simultaneously dispatched to PE2 to PE5 in response to the execution completion notification from PE1.

In this way, you can control the execution order of multiple processes.
It can be managed with DFP, synchronized and dispatched. Although the explanation has been omitted for the sake of simplicity, it goes without saying that when each process is dispatched, necessary data transfer control is also executed in an orderly manner at the same time.

FIG. 5 shows one embodiment of a token and address generation mechanism for notifying the DFP of execution completion or making other requests in each first processing device PE.

In the figure, 110 is a first processing device PE.

111 is an instruction executed by the first processing device, which includes an OP code, an index register area X ₂ ,
It includes a base register area B ₂ and a displacement area D ₂ .

112 is an instruction decoder DEC.

113 is a DEP flag.

114 is a DFP flag copy.

115 is a token.

116 is a general purpose register GPR.

117 is an address adder.

118 is a memory address register MSAR.

119 is a DFM address.

During operation, when the optional first processing device 110 completes execution of the assigned process,
An instruction 111 is issued to notify the DFP of completion of execution.

When the instruction 111 is issued, its OP code is decoded by the instruction decoder 112, and when it is identified as an execution completion notification instruction for the DFP, the DFP flag 113 is set on.
The on state of the DFP flag 113 is transferred to the DFP flag copy 114 at the next timing and output as a token 115 to the DFP.

Also, X ₂ of the address modification data of instruction 111,
B ₂ and D ₂ are used to generate the DFM address. Of these, X ₂ and B ₂ are general-purpose registers GPR
The index value and base address value are read out, and the address adder 117 reads out the index value and base address value.
Added together with D ₂ . The address of the addition result is
MSAR118, then DFM address 1
It is output to the MFP as 19.

As previously explained in Figure 2, the token and DFM address entered into the DFP are accessed by access 1.
36 to the token and address queue holding unit 132, and DFM access, firing detection, etc. are performed.

〔Effect of the invention〕

According to the present invention, the dispatch of procedures (processes) to each processor in multitasking and the synchronized control of data transfer can be made more efficient, and the overhead can be reduced. When used in a multiprocessor configuration, system performance can be improved.

[Brief explanation of drawings]

Figure 1 is a diagram showing the basic configuration of the present invention, Figure 2 is a diagram showing the configuration of one embodiment of the invention, Figure 3 is an explanatory diagram of the data format of dependency flow, and Figure 4 is a diagram showing the data format of dependency flow. FIG. 5 is a diagram illustrating an example of dispatch control, FIG. 5 is a diagram showing a token and address generation mechanism in the first processing device, and FIG. 6 is a conceptual diagram of multitasking. In FIG. 1, 10-1 to 10-n...first processing device PE, 11-1 to 11-n...main storage device
MSU, 12... Execution procedure storage means DFM, 13...
...Second processing unit DFP, 14...Mass storage device
CSU, 15...Storage control unit CMU.

Claims (1)

[Scope of Claims] 1. One or more subsystems including one or more first processing devices and a main storage device, a mass storage device, and one or more subsystems including one or more first processing devices and a main storage device; In a multiprocessor system having a storage control device connected to a mass storage device, the execution procedure of multiple procedures constituting a task is
an execution procedure storage means that is stored and expressed as data in a dependency flow format; and a second process that reads an execution procedure from the execution procedure storage means and instructs a first processing device of the subsystem to execute the process. The data in the dependency flow format stored in the execution procedure storage means is created for each procedure, and each includes information indicating whether the procedure is executable or not, and data transfer. the second processing device has a function of determining whether or not the procedure is executable based on each piece of information in the data read from the execution procedure storage means; If it is possible to perform the data transfer and further data transfer is instructed, instruct the storage control device to execute the data transfer between the mass storage device and the main storage device of the designated subsystem. A multitasking method characterized by having the following functions.