JPH0258837A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor device with wiring of high reliability by a method wherein a substrate formed of a wiring is arranged in a vacuum chamber whereto a gas containing a specific element is introduced to produce a plasma for introducing an impurity containing the specific element to the surface and sides of the wiring. CONSTITUTION:An SiO2 film 12 and an Al film 11 are successively laminated on an Si substrate 13 formed of an element. The specified region of the Al film 11 is etched away to form an Al wiring 14 where As atoms 15 as an impurity are implanted by e.g., ECR plasma doping device. At this time, the As concentration on the surface is around 2X10<19>cm<-3> while As 15 in high concentration is added to the whole surface of the Al wiring 14. This prevents the diffusion of Al atoms in the crystal grains and grain boundaries from occurring so that any hillock making trouble to flattening process may be restricted to enhance the reliability upon wiring.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention involves adding impurities by plasma irradiation,
The present invention relates to a semiconductor device with improved wiring reliability and a manufacturing method thereof.

Conventional technology Aluminum (Al) is used for wiring of semiconductor devices.
It is generally used because of its low resistance, workability, and adhesion to Si02. However, with the recent miniaturization of wiring, problems such as electromigration deterioration, stress migration deterioration, and flatness deterioration due to hillock formation on the surface have become apparent.

To address these problems with AI interconnects, by changing the composition of the sputtering target, Cu,
A method of containing Ti, Mg, etc., a layered wiring in which a metal layer such as W, Ti, etc. is provided in the middle or upper layer of the AI wiring,
AI wiring is made of tungsten (W) using metal CVD method.
(For example, I, E, E, DM, Technical Digest (1987) Vol. 2)
Pages 05 to 208 I EDM (1987) P.
205-P, 208) Method of implanting Ar, As, etc. by ion implantation method in AI model, for example, AI, E.
DM, Technical Digest (1984) pp. 138-141 I E D M (1984)
P, 138-P, 141'), etc. are commonly used.

A method using ion implantation will be explained with reference to FIG. Fourth
FIG. U is a diagram showing that an AI/Si film is deposited on a Si substrate 43 and a SiO film 42 on which elements are formed.

Next, using an ion implanter, As” (SoKeV, 6
x10 cm) (Fig. 4b).

Next, a desired region is etched to form a wiring 45 (FIG. 4C).

In the wiring formed in this way, A
On the upper surface of the wiring containing s, the diffusion of A1 atoms is suppressed by As44 present in the crystal grains and at the grain boundaries, so that the atoms move ((), and the generation of surface hillocks is suppressed.

However, with respect to electromigration, which is a defect in which A1 atoms move due to the flow of current, voids 47. A hillock 48 has occurred. Similar voids and hillocks occur in response to stress migration in which AI atoms move due to film stress when a protective film is formed on the wiring surface.

Problems to be Solved by the Invention However, although the method of pre-containing impurities in wiring improves electromigration resistance and stress migration resistance, it may not be sufficient to prevent hillocks. Furthermore, layered wiring has problems with increased resistance and processability due to non-uniform reactions between layers. W
In the cover method, the actual wiring width becomes thicker. In the ion implantation method, although it is possible to prevent hillock formation, improvements in electromigration resistance and stress migration resistance are rarely seen.

In view of these problems, an object of the present invention is to solve these problems and provide a semiconductor device having wiring with excellent reliability and a method for manufacturing the same.

Means for Solving the Problems The present invention includes placing a substrate on which wiring is formed on a sample stage provided in a vacuum chamber, and generating plasma by introducing a gas containing a specific element into the vacuum chamber. This is a technique in which impurities containing a specific element are introduced into the top and side surfaces of the wiring.

Function In the present invention, since a doping method using plasma is used, a highly concentrated impurity can be added to the entire surface of the wiring, not only the top surface but also the side surface of the wiring, in a short time at low temperature. Impurities on the wiring surface prevent the diffusion of atoms in the wiring material, which improves the hillock type caused by the movement of atoms, electromigration deterioration, stress migration deterioration, wiring corrosion, etc., and improves the reliability of wiring. do.

EXAMPLE An example of the present invention will be explained step by step with reference to FIG. Figure 1a shows a 13.5in2 Si substrate on which the device is formed.
3 is a diagram showing that an AI film (A1/5i) 11 is deposited on a film 12. FIG. Next, a desired region of this A11lffll is etched to form an AI wiring 14 (FIG. 1b).

Next, the EC used in this experiment is applied to the surface of the AI wiring 14.
R plasma doping equipment (e.g. electronic materials, P,
103.1987.December issue), doped gas H
e/AsH, = 9515 (63CCM), pressure 5x
10 Torr, current density at ECR exit 2mAc
m, cathode drop voltage due to RF discharge (wafer potential -
vD. > as an impurity with -700V
Atoms 15 are implanted (FIG. 1C).

At this time, the As concentration at the top surface of the wiring is 2X1019cm3
It was about.

In this embodiment, a high concentration of As is applied to the entire surface of the AI wiring 14.
Since 15 is added, diffusion of A1 atoms within crystal grains and at grain boundaries is suppressed, and hillocks, which are a problem in planarization, do not occur.

In addition, against electromigration deterioration and stress migration deterioration, there is a layer on the entire wiring surface that suppresses the movement of AI atoms.
Since mechanical deformation due to the movement of atoms is suppressed, voids and hillocks do not occur.

FIG. 2 shows a structural diagram of the ECR plasma doping apparatus used in this example.

In Figure 2, 21 is a microwave waveguide (2,45G
Hz), 22 is the gas inlet (He-based A
s H3). 23 is a quartz vacuum chamber, 24 is a stainless steel vacuum chamber, 25 is a high-density ECR plasma, 26 is a coil, 27 is a substrate, 28 is a sample stage, 29 is a cooling water inlet, 30
3 is a cooling water outlet, 31 is a matching box, 32 is a high frequency power supply, 33 is a DC voltage system, and 34 is an exhaust port. There is no mention here of means for evacuating the vacuum chamber, such as turbomolecular pumps.

When doping with arsenic (As), a gas containing As, such as arsine (A s H8), is introduced into the vacuum chamber 23 through the gas inlet 22 . The inside of the vacuum 23, which is a plasma generation tank, is made of quartz, which serves to prevent contamination of the sample due to sputtering on the side walls of the vacuum tank and to minimize annihilation of plasma and radicals on the sides.

The degree of vacuum inside the vacuum chamber 24 was maintained at a pressure other than 5×10 −3 Torr by controlling the opening amount of the conductance valve to the exhaust system connected to the exhaust port 34 and the flow rate of As H3. Microwaves with a frequency of 2.45 GHz and several tens to hundreds of watts are introduced from the microwave inlet 21, and the magnetic field created by the coil 26 (up to about 90
0 Gauss) and the electrons in the plasma create a situation close to electron cyclotron resonance (ECR),
Generates relatively high-density plasma despite being in a high vacuum. The sample stage 28 is cooled by circulating cooling water cooled to about 0°C to 30°C. The sample stage 28 is cooled by using highly insulating ultrapure water, other highly insulating liquids, or by applying methods such as electronic cooling or cooling by spraying He on the back side of the substrate 27. , sample stage 28
By applying a DC or AC bias potential to the substrate, a discharge region can be formed between the substrate and the substrate. From this, the potential energy between the plasma and the sample stage can be set arbitrarily.

Plasma doping was performed using the above apparatus. A
I/Si wiring (line width 1, 2 tt m
, thickness 1.0 μm) is doped with As. As an impurity gas, A s H3 was diluted with He and introduced into the vacuum chamber at a flow rate of 6 SCCM at 5%, and the degree of vacuum was adjusted to 5 x l by adjusting the conductance valve.
Q Maintained at Torr. Plasma was generated under ECR conditions, RF discharge was performed between the plasma and the substrate 27, and the DC voltmeter 33 was maintained at 700V. When exposed to plasma for 300 seconds in this state, the surface concentration was 2 x 10 cm at the top surface of the wiring, and the depth was 50 nm.
It was confirmed by secondary ion mass spectrometry that A, s doping was performed.

In this example, since A1 wiring was used, the ECR plasma doping method was used to actively cool the substrate without exposing the wiring surface to high-density plasma, and the wiring surface temperature was kept at 150°C to suppress hillock formation during processing. Ta.

However, depending on the type of wiring, an inexpensive method of simply generating plasma using microwaves, high frequency waves, or direct current may also be applicable.

FIG. 3 is a diagram showing a comparison of the number of voids showing improvement in stress migration deterioration of aluminum wiring according to this example.

In this example, PSG (thickness: 800 nm, P concentration: 8
After forming an AI/Si film (thickness: 800 nm) by DC magnetron sputtering on the Si substrate on which the (wt%) film was deposited, 1) 5
Perform As implantation of 0KeV 6X10 cm,
Patterned sample (line width 1.2 μm), 2) After patterning (line width 1.2 μm), surface concentration 2×10 cm
A sample was prepared with ECR plasma doping so that
A SiN film was deposited to a thickness of 500 nm using the VD method and subjected to high temperature storage test 1.
The test was carried out at 50°C for 150 hours.

The number of voids on the test pattern is shown in FIG. 3 for each sample. When voids on the A1 wiring pattern were observed using a scanning electron microscope, it was found that in the sample without injection, the line width was 1
．． Fifteen voids were observed in a section with a thickness of 2 μm, a thickness of 800 nm, and a wiring length of 50 μm. Nine voids were observed in the sample subjected to As ion implantation, and two voids were observed in the sample subjected to ECR plasma doping.

As is clear from this figure, the manufacturing method of this example has the effect of extremely suppressing the generation of voids.

Here, we have talked about missing voids in the wiring, but the same tendency was observed for hillocks, which are prominent parts.

As described in detail, according to the present invention, it is possible to form wiring having high reliability with ease of processing, and in particular, it is possible to form wiring with low resistance, which has become difficult to use in submicron line widths. Cheap AI-based alloys can be used continuously, and the practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view showing the process order of an embodiment of the present invention, FIG. 2 is a schematic structural diagram of an ECR plasma doping apparatus used in the present invention, and FIG. FIG. 4 is a characteristic diagram illustrating the reduction, and a process sectional view showing a process sequence showing conventional prevention of hillock generation by ion implantation. 11... Aluminum film, 12... SiO2
Film, 13...Si substrate, 14...AI
Wiring, 15...As0 Name of agent: Patent attorney Shigetaka Awano and one other person Figure 1 Figure 2 (CL) Figure Injection Pyroion Implantation EC Scale Plasma Dorf Figure (α)

Claims (2)

[Claims] (1) A substrate with wiring formed thereon is placed on a sample stage provided in a vacuum chamber, and the wiring is exposed to the plasma to add a specific impurity to the top and side surfaces of the wiring. semiconductor device. (2) Place the substrate with wiring formed on a sample stage provided in a vacuum chamber, introduce a gas containing a specific element into the vacuum chamber to generate plasma, and connect the wiring to the plasma. A method for manufacturing a semiconductor device, characterized in that a specific impurity is added to the upper surface and side surface of the wiring by exposing the wiring.