JPH0258591B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) This invention relates to an abnormality detection device in a speed detection device.

(Prior art) Conventionally, for example, in an automated guided vehicle, in order to control the traveling speed more reliably, it has been required to be able to identify whether the vehicle is moving forward or backward, and to have a speed detection device that can provide a stable feedback signal even at low speeds. has been done.

Conventionally, there has been a speed detection device having a circuit configuration shown in FIG. This circuit uses first and second sensors 3 and 4 for detecting objects 2, which are provided at equal intervals on a rotating body 1 that rotates at a speed proportional to the running speed, at a timing of 90 degrees when detecting objects 2 to be detected. The detection signals SG1 and SG2, which are output from both sensors 3 and 4 and whose phases are shifted by 90 degrees from each other, are sent to the first sensor via the waveform shaping circuit 5. outputs the output signal SG3 of the NAND circuit 6 and the detection signal SG1 of the first sensor 3 to the second NAND circuit 7, and outputs the output signal SG3 of the first NAND circuit 6. and the detection signal of the second sensor is
The output signals SG4 and SG5 from the second and third NAND circuits 7 and 8 are outputted to the fourth NAND circuit 9 and the output signal SG is output to the fourth NAND circuit 9.
6 was taken out as a speed feedback signal.

Since this feedback signal SG6 outputs a pulse signal twice as large as the pulse signal proportional to the rotational speed extracted by one sensor, a stable feedback signal was obtained especially when running at low speed. Also, since this circuit extracts the detection signals SG1 and SG2 output from the two sensors 3 and 4 with a phase shift of 90 degrees from each other, it is possible to determine whether the transport vehicle is moving forward or backward. It can be identified from the states of signals SG1 and SG2.

Therefore, this detection device is adopted in many vehicles because it has the above-mentioned advantages.

(Problem to be solved by the invention) However, since this speed detection device uses two sensors, one sensor may be normal and the output of the other sensor may remain at a positive potential or remain at zero potential. , the output of both sensors remains at zero potential or remains at positive potential, or the output of one sensor remains at positive potential and the output of the other sensor remains at zero potential, There are many possible abnormalities such as when the pulse outputs of both sensors become synchronized. Therefore, there has been a desire for an abnormality detection device that can detect all abnormalities in this speed detection device.

Structure of the Invention (Means for Solving the Problems) In order to solve the above problems, the present invention provides two detecting objects arranged at equal intervals on a rotating body that rotates at a speed proportional to the traveling speed. sensors are shifted from each other so that the detection timing of the detected object is out of phase by 90 degrees, and the detection signals output from both sensors with a phase shift of 90 degrees from each other are output to the first NAND circuit. The output signal of the NAND circuit and the detection signal of the one sensor are output to a second NAND circuit, and the output signal of the first NAND circuit and the detection signal of the other sensor are output to a third NAND circuit. A speed detection device that outputs both output signals from the second and third NAND circuits to a fourth NAND circuit and uses the fourth output signal as a speed feedback signal, A timer circuit that counts the period of the output signal from the third NAND circuit, and a timer circuit that counts the period of the output signal from the second and third NAND circuits in advance when the two sensors are operating normally. The anomaly detection device consists of a comparison circuit that compares with a reference value set based on the cycle of This is a summary.

(Function) That is, the timer circuit counts the periods of the output signals of the second and third NAND circuits, respectively,
A comparator circuit compares the counted period with a reference value set based on the period of the output signals output from the second and third sensors when the two sensors are operating normally. and,
Next, the determination circuit determines whether or not there is an abnormality based on the results of both comparisons.

(Example) An example embodying the present invention will be described below with reference to the drawings. Incidentally, since this embodiment is embodied in the speed detection circuit shown in FIG. 4, the common parts are given the same reference numerals and their explanation will be omitted.

FIG. 1 shows a circuit diagram in which an abnormality detection circuit is added to the speed detection circuit, and the first timer circuit 11 consists of a transistor Tr1, a capacitor C1, and a resistor R1.
inputs the output signal SG4 from the second NAND circuit 7. As shown in FIG. 2, this timer circuit 11 outputs an integral wave output signal SG7 by turning on and off the transistor Tr1 and charging and discharging the capacitor C1 in response to the square wave output signal SG4. do. On the other hand, transistor Tr2,
A second timer circuit 12 consisting of a capacitor C2 and a resistor R2 receives the output signal from the third NAND circuit 8.
Enter SG5. Similarly, timer circuit 1
2 is the square wave output signal SG, as shown in Figure 2.
5, outputs an integral wave output signal SG8.

The first and second comparators 13 and 14 as comparison circuits have resistors R3 and R4 on the + terminal side, respectively.
The reference voltage Vs is input from the reference voltage setting circuit consisting of
and the output signals SG of the second timer circuits 11 and 12
7, SG8 is input. When output signals SG7 and SG8 of a level lower than the reference voltage Vs are input, the first and second comparators 13 and 14
outputs output signals SG9 and SG10 of positive potential (hereinafter referred to as H level), respectively, and conversely, when output signals SG7 and SG8 of high level are input, output signals of zero potential (hereinafter referred to as L level) are output.
It is designed to output SG9 and SG10.

Both signals SG9 and SG10 are output to a NAND circuit 15 as a discrimination circuit, and the NAND circuit 15 outputs an abnormality presence signal SG11 based on the levels of both signals SG9 and SG10.

The reference voltage Vs is a voltage with a preset value, and the speed detection device is operating normally at the lowest practical speed of the unmanned vehicle (the lowest speed in the speed range that the speed detection device must detect). At this time, the first timer circuit 11 (the second timer circuit 1
2) is set to be a value slightly larger than the maximum voltage value of the output signals SG7 and SG8.

Therefore, when the speed detection device is operating normally above the minimum practical speed, the output signal is always
Since the levels of SG7 and SG8 do not reach the reference voltage Vs, the first and second comparators 13 and 14
The output signals SG9 and SG10 are always at H level, and the NAND circuit 15 outputs an L level abnormality signal.
SG11 will be output.

Next, the operation of the abnormality detection device configured as described above will be explained.

Now, when the first and second sensors 3 and 4 are operating normally, as shown in FIG. , SG2 is output.

The first and second timer circuits 11 and 12
Output signals SG7 and SG8, which are less than the reference voltage Vs and whose phase is shifted by 180 degrees, are outputted from the output terminals 1 and 2, and are outputted to the first and second comparators 13 and 14 at the next stage, respectively. As a result, the output signals SG9 and SG10 outputted from both comparators 13 and 14 both become H level, and the abnormality detection signal SG11 becomes L level.

Next, a case where the first or second sensor 3, 4 is abnormal will be described.

When the first sensor 3 is normal and the second sensor 4 is abnormal and its detection signal SG2 remains at the L level, the third NAND circuit 8 is activated as shown in FIG. 3a. The output signal SG5 is always at H level, and the output signal SG8 of the second timer circuit 12 is equal to or higher than the reference voltage Vs. As a result, the output signal SG10 of the second comparator 14 changes from H level to L level.
level, and the abnormality presence/absence signal SG11 changes from L level to H level.

Furthermore, when the detection signal SG2 of the second sensor 4 remains at the H level, the output signal SG4 of the second NAND circuit 7 is always at the H level, as shown in FIG. Output signal SG of circuit 11
7 becomes equal to or higher than the reference voltage Vs. As a result, the output signal SG9 of the first comparator 13 changes from H level to L level, and the abnormality detection signal SG11 changes from L level to H level.

Also, contrary to the above, when the second sensor 4 is normal and the first sensor 3 is abnormal, the same operation as above is performed as shown in FIG.
SG11 becomes H level.

Next, as shown in FIG. 3e and f, if both sensors 3 and 4 are abnormal and their detection signals SG1 and SG2 both remain at H level or L level, the second and third NAND circuits 7 and 8 both become H level, and the output signals of the first and second timer circuits 11 and 12
Both SG7 and SG8 become equal to or higher than the reference voltage Vs. As a result, the first and second comparators 13, 14
The output signals SG9 and SG10 both become L level, and the abnormality detection signal SG11 becomes H level.

In addition, as shown in FIG. 3g and h, the detection signals SG1,
When SG2 outputs signals of opposite levels, the first or second timer 11,1
Either output signal SG7 or SG8 of 2 is the reference voltage.
Since the voltage is higher than Vs, the abnormality detection signal SG11 becomes H level.

Further, as shown in FIG. 3i, when the detection signals SG1 and SG2 of the first and second sensors 3 and 4 output signals in the same phase, the outputs of the first and second timer circuits 11 and 12 Since the signals SG7 and SG8 both exceed the reference voltage Vs, the abnormality detection signal SG11
becomes H level.

In this way, the abnormality detection signal SG11 is at L level only when both the first and second sensors 3 and 4 are operating normally, and it is not at H level during any other abnormality detection operation. Recognize.

As a result, by activating the alarm device based on this abnormality detection signal SG11, it is possible to reliably notify the presence or absence of an abnormality in the speed detection device. Also, for example, by installing this abnormality detection device in a speed detection device such as an unmanned vehicle, this abnormality detection signal can be detected.
If the drive of the unmanned vehicle is controlled to stop based on SG11, reliable operation of the unmanned vehicle can be achieved.

Effects of the Invention As detailed above, according to the present invention, the speed detection device has an excellent effect of being able to reliably detect the presence or absence of an abnormality.

[Brief explanation of drawings]

FIG. 1 is an electrical circuit diagram of an abnormality detection device embodying the present invention, FIG. 2 is a diagram of each output waveform of the abnormality detection device, and FIG. 3 is a diagram of each output waveform when the speed detection device is abnormal. FIG. 4 is an electric circuit diagram of the speed detection device, and FIG. 5 is a diagram of each output waveform of the speed detection device. In the figure, 1 is a rotating body, 2 is a detected object, 3 is a first sensor, 4 is a second sensor, 6 is a first NAND circuit, 7 is a second NAND circuit, and 8 is a third NAND circuit. 9 is a fourth NAND circuit, 11 is a first timer circuit, 12 is a second timer circuit, 13 is a first comparator, 14 is a second comparator, and 15 is a NAND circuit.

Claims (1)

[Scope of Claims] 1. Two sensors arranged at equal intervals on a rotating body rotating at a speed proportional to the traveling speed to detect objects to be detected are arranged such that the detection timing of the objects to be detected is out of phase by 90 degrees. The detection signals outputted from both sensors with a phase shift of 90 degrees from each other are outputted to the first NAND circuit, and the output signal of the NAND circuit and the detection signal of the one sensor are outputted to the second NAND circuit. At the same time, outputting the output signal of the first NAND circuit and the detection signal of the other sensor to a third NAND circuit, and outputting both output signals from the second and third NAND circuits. In a speed detection device that outputs a signal to a fourth NAND circuit and uses the fourth output signal as a speed feedback signal, a timer circuit that counts the period of the output signal from the second and third NAND circuits, respectively; a comparison circuit that compares the reference value with a reference value set in advance based on the period of the output signal output from the second and third NAND circuits when the two sensors are operating normally; and each comparison circuit. What is claimed is: 1. An abnormality detection device for a speed detection device, characterized in that it is provided with a discrimination circuit that inputs comparison results of the circuits and determines the presence or absence of an abnormality based on both comparison results.