JPH0258432A - Error position polynomial deriving circuit using bit serial type multiplier - Google Patents

Abstract

PURPOSE:To speed up the processing and to simultaneously, reduce the hardware quantity by unifying the expression form of the unknown to be inputted and outputted to a primary converted form with a Hankel matrix and providing a reverse converting circuit to execute the reverse conversion of the Hankel matrix in a multiplier with a bit serial type multiplier. CONSTITUTION:A bit serial type multiplier constituted based on a Wiener-Hopf equation to execute the multiplication with the unknown primarily converted with a Hankel matrix K and the unknown not to be converted is used. In the bit serial type multiplier, a reverse converting circuit 23 to execute the reverse conversion K<-1> of one side unknown is provided and all unknowns inputted and outputted to the bit serial type multiplier are unified to the expression form primarily converted by the Hankel matrix K respectively. Thus, the hardware quantity of a Galois field multiplier is reduced, the operation can be speeded up and simultaneously, the device can be miniaturized.

Description

[Detailed Description of the Invention] [Industrial Application Field] An error correction method that uses error correction codes such as Reed-Solomon codes and BCH codes to correct errors in multiple words within one block is used in optical disks, magnetic disks, and optical discs. It is widely used in fields such as magnetic disks and communications.

The present invention is directed to error correction codes (long distance codes: LD
The present invention relates to an error correction circuit using C), and more specifically, to an error locator deriving circuit that calculates an error locator polynomial using Euclidean algorithm when decoding a long distance code.

[Conventional technology]

In order to perform error correction of multiple words using a long discance code (hereinafter referred to as LDC) such as a Reed-Solomon code or a BCH code, it is necessary to generate a syndrome from received data and find the coefficients of an error locator polynomial. Generally, the LDC decoding procedure is as follows.

■ Find the syndrome S1(x) from the received data X.

■ Error locator polynomial σ from syndrome S r (x)
Find (X).

■ Find the error location from the error location polynomial σ(x).

■ Find error patterns.

■ Correct the received data X from the Jll position and error pattern.

In the above series of processing steps, the most complicated and time-consuming part is the part (2) in which the error locator polynomial σ(x) is determined. The Euclidean algorithm is known as one of the methods for determining the coefficients of the error locator polynomial. This Euclidean algorithm is an algorithm for finding the greatest common divisor (polynomial) of two given numbers (polynomials). Given two polynomials R-+ (x) and Ro(x), the following (
Repeat the operation of Ll ~ (J R'':, until Rt(x) = O, and when Rt (x) = 0, R; the two polynomials R given −1(x) −, (x
) and Ro(x).

Q+(x)=(R,-z(x)/Rt-+(x))
-11) R=(X)=Ri-z(x)-Q+(x)R
;-+(x)-121L;(x) = Lt-z(
x) Qi(x) L=-+(x) -131U1
(x)=U, -z(x)-Q;(x)U;-+(x)
-(41 However, () represents the quotient polynomial 2.

L-, (x) = O, LO(X) = 1U-1 (ni) = -1, U, (ni) = 0 In the calculation process of this Euclidean algorithm, the following properties hold true.

R1(x) = L;(x) Ro(x) −[1(
x) rl! −+(z)deg, R;(x) <de
g, R;-+(x) --[61deg, L
i(x)=deg, R-+(x)-deg, R;-+(
x)・−1−・−(7) L, (x)≠0 −
・－・・・・・・・・・(8) gr, d (U r , L
r ) = 1 --1 ---
--(91 Here, gcd() indicates the greatest common denominator polynomial.

The error locator polynomial σ(x) in question is L H( x).

That is, the syndrome S is expressed as follows. Here, α is a primitive element on the Galois field GF(2″), and X represents a received word.

Based on the syndrome S, the syndrome polynomial S (
x) is defined as follows.

5(X)=S, +S, X+S2X"+・+S?X'・・
−・ 0υ Also, the error locator polynomial σ(x) when one error occurs
is defined as follows.

f (x) = (X + VI) (X + Vz) −
(X + Vt) = X l+σ, -, 'X'-'+・
...10σ, X+σ.

・-(1no Here, ■, to ■1 indicate error positions.

The above syndrome polynomial S (x) and error locator polynomial σ
(x) has the following relationship.

A (x) X 2L+ ty (x) S (x)
= ti Cx) -----031deg, (
11(x) <deg, tt (x) ≦t
-------aIO However, A (x) Arbitrary polynomial ω(X): Error evaluation polynomial L 2 Number of correctable error words deg, ω(X): Degree deg of polynomial 〇(x), σ(
×): Degree of polynomial σ(x) This Q3), σ(x) and 0paX) that satisfy equation 041, are calculated in the calculation process of Euclid's mutual division method to find the greatest common polynomial of X2t and S (x). When the order of Ri(x) is less than t order (t is the number of words that can be corrected), L, (x) and R=
x).

Figure 5 shows Kun's method for determining the error locator polynomial σ(x) and error evaluation polynomial ω(x) using the Euclidean algorithm described above.
We present the systolic algorithm [by ng et al. In this systolic algorithm, the above-mentioned R r (x) is alternately represented by A (x) and B (ni), and L ; (x) is alternately represented by L (x) and M (x). There is.

Here, A (x) and B (x) are expressed as follows.

A(x)=a, x'+a, -, xt1+-°-a,
x+a. ---O5 B (x) = blIx'+ blI-, X'-'+・
+・b, x + b 0---〇6) At this time, the above (]) in Euclidean algorithm.

The calculation of equation (2) is as follows.

Q, (x)= (R, -z(x)/R;-+(x)1=
QbXk+qk-, xh-1...+q+X''q.

・−−−−−−−・−0η A (x) = A (x) −Q (X) B (X
) ----- θ (to) 0 Instead of the formula, the following formula is repeated +1 times.

A (x) = A (x) −q ux' B (
x) ・----1--・-(19) (u =
, ni -1,..., 0) If the coefficients of the highest order of A (x) and B (x) at each calculation of the a9,00 formula are denoted as β and α, respectively, then qu=β/α −− -One...-
・(2I, u = deg, A −deg, B
Using this fact, formula 091 can be rewritten as follows.

a A (x) = ex A (x)-βx (d
a'l -A -d I! 9°"' B(x)・
(21) Therefore, if αA(x) is replaced by A(x) again, the result of multiplying the error locator polynomial by a constant coefficient can be obtained by simply performing multiplication. That is, A (x) or B (
It represents an error locator polynomial in which either x) or M(x) is multiplied by a constant at the time when either x) becomes less than the tth degree. Further, it represents an error evaluation polynomial in which A (X) or B (x) at this time is multiplied by a constant.

Figure 6 shows 3 constructed using Euclidean mutual division method.
An example of a four-output error locator polynomial circuit capable of multiple error correction (t=3) is shown. The illustrated circuit shows only the calculation portion of A (x) and B (x) in the systolic algorithm of FIG. 5, and is for processing the calculations of A (x) and B (x) in parallel. Note that the calculation portions for L (x) and M (x) are omitted from illustration because they can be performed using a similar circuit configuration.

In the figure, reference numerals 1 and 2 are bit serial shift registers for storing coefficient data of A(x) and B(x), and have a parallel load function. 3,4
are buffers for holding coefficient data of A(x) and B(x) given from bit serial shift registers 1 and 2, respectively, and 5 and 6 select inputs of bit serial shift registers 1 and 20. It is a selector.

7.8 is A (x)B( given from buffers 3 and 4)
×) coefficient data and bit serial register 16.
Multiplication αA(X) with the highest order α and β given from 26
, βB (x).

9 is an adder, 10 to 12 are selectors, and selector 1
For 1.12, input "0" except when setting initial data. In addition, bit serial shift registers 16 and 26
represent the highest order coefficients of A(x) and B(x), ie, β and α, respectively.

Further, processing regarding the order is performed independently using flags, but this flag relationship is omitted from illustration.

The operation of the above circuit will be explained with reference to the flowchart of FIG.

First, initial data is set through selectors 11 and 12. In other words, since t=3, 2t=6, so
A(x
)=X' and set the syndrome polynomial S (x) as B (x) in the bit serial shift registers 2° to 26. In addition, other L not shown in the diagram
(x) and the workings of the arithmetic circuit of M (x)×),
Set M (x) to 1 (step [1 piece). At the same time, a flag for order calculation, which is not shown, is also set.

Next, the bit serial shift register 1° to 1.
The value of A (x) set to 3° to 3. and bit serial shift register 2° to 2. The value of B (x) - S (x) set to 4° to 4. (Step [2]). Further, in order to transfer the operation results of the Galois field multipliers 7 and 8 to the next stage bit serial shift register, each selector 5° to 5. and 6°~6. is switched to the selector 10o to 10s side (step 7 "3J").

Galois field multiplier 7°~7. are the highest order coefficient α of the bit serial shift register I and each buffer 3° to 3.
Multiplication with the value αA (x) is performed, and a Galois field multiplier 8° to 8. is the product β of the highest order coefficient β of the bit serial shift register 26 and the value of each buffer 4° to 45
B(x) is performed (step [4]), and the respective multiplication results are sent one bit at a time to each adder 9° to 9S for addition (step [5]).

The above addition results are sent to selectors 10° to 10.degree. under the control of an order flag (not shown). is transferred to the next stage bit serial shift registers 1 and 2 (step [6
]).

Set selectors 5° to 5S and 6° to 65 to bit/serial/
After switching to the shift register side (step [7]),
Bit serial shift registers 16, 2 . A (x) and B stored in
It is determined whether either the highest degree coefficient β or α of (x) is O (step [8]), and if either is 0, the bit serial shift register on the corresponding side is ]word shift 1 or 2 (step [9,])
. When the l side of the bit serial shift register is shifted, the order of A (x) decreases by one, and the bit serial shift register
When the shift register 2 side is shifted, the order of B (x) decreases by one.

If neither β nor α is O, step [10]
bit serial shift register l in an end check circuit (not shown).

A(X) stored in 2, de of 13(x)
g, A or deg, B is determined, and if t=3 or more, the process returns to step 7 [2] and the above process is repeated. On the other hand, if deg, A or deg, B is (=
If it is smaller than 3, the arithmetic processing using the Euclidean algorithm is terminated at that point (step [10]), and the data stored in the bit serial shift register is output (step [11]).

That is, at the end of the above, A (x) or B stored in the bit serial shift register side or 2
(×) is the error evaluation polynomial ω for the received data at that time
(x) and other L (x) and M (not shown)
The function stored in the arithmetic circuit of (x)
x) gives the error locator polynomial σ(x).

(Problem to be Solved by the Invention) The Galois field multiplier in the error position multi-term 2 derivation circuit has 4 for A (x) and B (x), and f, (x
) and M (x), 2L pieces are required, making a total of 6 pieces. Conventionally used Galois field multipliers, for example, are bit parallel type multipliers with a capacity of 300
In the case of 3 in the above example, approximately 5400 gates are required in total. Therefore, t=
In the case of an LDC such as the well-known optical disk No. 8, approximately 20,000 gates are required in total, which increases the amount of circuit hardware and becomes an obstacle to miniaturization of the device.

In addition, Iwamura et al. have proposed a processing unit (PE) for encoding and decoding Reed-Solomon codes through VLSI and speeding up by vibline processing based on the systolic algorithm. IEICE Transactions '88/3 Vol, J71-A
No, 3 pp751-759), but this I
Even a processing unit that becomes H requires about 1000 gates per unit, and (7t+4) gates are required for the entire circuit.

Therefore, in the case of t=8, which is used in optical disks, a total of about 60,000 gates are required, resulting in an expensive system.

In view of the above circumstances, the present invention reduces the amount of hardware for the Galois field multiplier compared to the conventional one by considering the circuit configuration of the Galois field multiplier, which occupies most of the hardware in this type of error locator polynomial derivation circuit. The present invention provides an error locator polynomial deriving circuit that achieves high-speed calculation and miniaturization of the device.

[Means to solve the problem]

In order to achieve the above object, the present invention uses a Galois field multiplier that multiplies two elements in an error locator polynomial derivation circuit that calculates an error locator polynomial from a syndrome using Euclidean algorithm when decoding a long distance code. , Ihener-, which performs multiplication by an element that has been linearly transformed using a Hankel matrix and an element that has not been transformed.
In addition to using a Pinto serial type multiplier configured based on the Hopf equation, the bit serial type multiplier 2
An inverse conversion circuit that inversely transforms one element K −1 is attached in g, and all elements input and output to the bit-serial multiplier are unified into an expression format in which each element is linearly transformed by Hankel matrix K. It is.

[For production]

All input and output elements of the bit-serial multiplier configured based on the Wiener-Hopf equation are unified into an expression format that is linearly transformed using a Hankel matrix, and one of the two elements to be multiplied is inversely transformed. Since the configuration is such that multiplication is performed, the calculation speed is increased and the circuit configuration is simplified.

〔Example〕

Examples of the present invention will be described below.

The present invention is directed to the Galois field multipliers 7° to 7. in the error locator polynomial deriving circuit shown in FIG. and 80-8. This uses a bit serial type multiplier configured based on the Wiener-Hopi equation as detailed below.

Bit-serial type multipliers include those constructed using a method based on a normal basis and those constructed using Berlkamp's method. , the base conversion becomes complicated. Therefore, the present invention provides a bit-serial multiplier constructed based on the Wiener-Hopf equation proposed by Morii et al. (IEICE Transactions '88/3 Vol. J71-A No.

3 pp. 845-853) was adopted as a Galois field multiplier. First, a bit serial multiplier constructed based on the Wiener-Hopf equation will be described.

Now, from the two elements U and S on the Galois field GF (2”) expressed as a vector,
Consider finding S that satisfies (22). This is v (z) = u (z) −s (
z) mod f(z) --(23) However, f (
z) is equivalent to finding v (z) that satisfies the primitive polynomial. At this time,
The following formula holds true.

ing. When U and V are converted into bases using this Hankel matrix K, the following results are obtained.

・---(24) Here, α is a primitive element of the Galois field GF (2ffi), and β is an arbitrary element, where xeGF(::') is used. Here, put .

In general, by using U and V, which are referred to as Hankel matrices above, a general bit serial type multiplier shown in FIG. 4 can be constructed based on equation (24). That is, as the initial value of shift 1 register R9-R7-1, RH-IJt, (i = 0. I
, −m −1) −−−−−−(29) By giving m shift operations, Vi(i =0.1.
...m-1) can be output and generated.

Here, the primitive polynomial "(2) is f(z)=z"+fffi-, z+...t f, z--
------- (30).

However, the bit serial type multiplier shown in Figure 1 is not versatile because the representation format of the elements to be multiplied is different, and for this reason, it has been used only when generating codes or syndromes where one multiplier is a constant. Couldn't use it.

In the operation in the Euclidean algorithm mentioned above, A(x
), the representation format of the Galois field must be the same since the coefficients of B(x) are multiplied by the highest degree of each polynomial. Therefore, the present invention is based on the Wiene shown in FIG.
In order to generalize the bit serial type multiplier based on the r-Hopf equation so that it can be used as an error locator polynomial derivation circuit using the Euclidean algorithm, we expand the circuit configuration as shown in Figure 2 and perform multiplication. It is now possible to display two elements in the same representation format.

That is, in FIG. 4, U and V are linearly transformed using the Hankel matrix K, and S remains a polynomial basis, but in the present invention, the remaining S can also be expressed as shown in FIG. , it is generalized to use S linearly transformed into a Hankel matrix, and all elements are linearly transformed into a Hankel matrix to form a unified representation format. Then, in order to return the linearly transformed τ to the Hankel matrix to the original base representation form, the inverse transformation l! is performed in the multiplier. An inverse conversion circuit for performing AK-' is attached.

As a result, the representation formats of all the originals are unified, and therefore arithmetic processing can be performed without changing the representation format of the registers. Here, β in equation (24) can be arbitrarily selected, so −1 is 21 in the inverse matrix according to the Hankel matrix.
There are 1-1 matrices, and by selecting the most advantageous matrix, the circuit required for inverse transformation can be minimized.

Based on the above conclusion, − As an example, if the primitive polynomial is
FIG. 3 shows a specific example of the configuration of a bit serial multiplier based on the Wiener-Hopf equation on the c-o7 body GF(2') where X'+X'+X''+1. Here, if β-α250, then (2
The inverse matrix K −1 given by equation 6) is as follows.

In this case, this inverse transformation is performed using two XO
It can be configured with only R gates 31 and 32. Therefore, the circuit elements required for one Galois field multiplier are AND
There are 8 gates, 11 XOR gates, and 1 word buffer for storing the multiplicand. This reduces the amount of hardware to about 1/3 compared to a conventional bit-parallel multiplier.

FIG. 1 is an example of an error locator polynomial deriving circuit according to the present invention constructed using a bit-serial multiplier based on the generalized Wiener-Hopf equation described above. The illustrated circuit includes buffers 3° to 31 and Galois field multipliers 7° to 7.0 for calculating αA (x) in FIG. This is the circuit corresponding to the part.

In FIG. 1, α, which gives the highest order coefficient of B (x), is linearly transformed by the Hankel matrix K and is stored in the shift register 2.
1, and the coefficient data of A (x) is linearly transformed by Hankel matrix K and sent to buffers 221 to 2.
2 □ is memorized.

The execution of the multiplication αA (x) is carried out in the buffer 22. ~22zt
After each coefficient data of -+ is inversely transformed in the inverse transformer 23, it is sent one pint at a time to the A'N D plane 24 and multiplied by α from the shift register 21, and the multiplication result is converted into one pin by the XOR plane 25. The focus is output one by one. Therefore, (21
) To calculate the equation, arrange two circuits in Figure 1 and calculate αA.
(x) and βB (x) and XOR the respective outputs. In the case of the above configuration, the Galois field multiplier can be made much smaller than a conventional multiplier, and can be made into a chip using an LSI.

In addition, since calculations can be performed on all coefficients by simply shifting α and β m times, even if the number of words that can be error corrected increases, the processing time only increases by one order of magnitude.

〔Effect of the invention〕

According to the present invention, the representation format of the input/output source is unified to a format obtained by linear transformation using a Hankel matrix, and a bit serial multiplier based on the Wiener-11oρf equation, which is generalized as a Galois field multiplier, is used. Since the multiplier is provided with an inverse transform circuit for inversely transforming the Hankel matrix, it is possible to speed up the processing and at the same time reduce the amount of hardware and downsize the device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main part configuration of one embodiment of the error locator polynomial deriving circuit according to the present invention, and FIG. 2 is a bit serial type constructed based on the generalized Wiener-Hopf equation used in the present invention. Figure 3 is a diagram showing the principle of construction of a multiplier. Figure 3 is a diagram showing a concrete example of a bit-serial multiplier constructed based on the generalized 11ener-Hopf equation 2. Figure 4 is a diagram showing the construction principle of the Wiener-Hopf equation. Figure 5 is a flowchart of a systolic algorithm for determining an error locator polynomial using the Euclidean algorithm; FIG. 6 is a diagram showing the configuration of the error locator polynomial deriving circuit, and FIG. 7 is a flowchart of the operation of the error locator polynomial deriving circuit. 21...Shift register, 22...Buffer, 23
...Inverse transformation circuit, 5...XOR brane, K...Pankel matrix, K-1...inverse matrix.

Claims (1)

[Scope of Claims] In an error locator polynomial deriving circuit that calculates an error locator polynomial from syndromes using the Euclidean algorithm when decoding a long distance code, as a Galois field multiplier that multiplies two elements, a first-order polynomial in a Hankel matrix is used. A bit-serial multiplier configured based on the Wiener-Hopi equation that multiplies a transformed element and an untransformed element is used, and one element is placed inside the bit-serial multiplier. It is characterized in that it is equipped with an inverse conversion circuit that performs inverse conversion K^-^1, and that all elements input and output to the bit-serial type field multiplier are unified into a representation format in which each element is linearly transformed by Hankel matrix K. Error locator polynomial derivation circuit using bit-serial multiplier.