JPH0258429A - Da converter - Google Patents

Abstract

PURPOSE:To satisfy the accuracy and the monotone by using the DA converting circuit of an (n) bit for an (n) bit data input, making an effective bit inputted to the DA converting circuit from the upper-order effective bit into an (m) bit only with a mask circuit. CONSTITUTION:A mask circuit 12 of digital data is provided for a DA converting circuit DAC 10, and a control circuit 16 of the mask circuit 12 and an upper-order effective bit detecting circuit 14 of a digital input are provided. When the DA converting circuit 10 is an (n) bit and consequently, a digital input is also the (n) bit, the mask circuit 12 keeps an (m) bit (m<n) continuous from the first 1 at the high order side in the (n) bit as it is. For a remaining n-m bit, 0 of the l number up to the first 1 is kept as it is, a remaining bit n-m-l number at the lower order side from the (m) bit is all made into 0 and given to the DA converting circuit 10. The (m) is the number of bits necessary to guarantee the accuracy of the DAC 10. Thus, the comparatively inexpensive DAC 10 can practically satisfy the accuracy and the monotone.

Description

[Detailed Description of the Invention] [Summary of the Invention] It is an object of the present invention to provide a DA converter, particularly its input circuit, which can satisfy both accuracy and monotonicity in practice at a relatively low cost or with AC. A bit DA conversion circuit receives the digital input of the plurality of bits, and converts the predetermined plurality of bits from the most significant effective bit, which is the bit where l is set and is the most significant bit, to the predetermined plurality of bits on the lower side. The above DA
a mask circuit for digital data to be applied to a conversion circuit; a most significant bit detection circuit for detecting the most significant bit of the digital input; and receiving an output from the detection circuit, causing the mask circuit to process the digital input. and a mask control circuit that generates a signal.

[Industrial application field]

The present invention relates to a DA (digital-to-analog converter), particularly to its input circuit.

[Conventional technology]

A typical DA converter (DAC) uses an R-2R ladder circuit, and its outline is shown in FIG. R,2
R is a resistance with a resistance value of R, 2R, Sl+S 2+...
... is a changeover switch, OP is an operational amplifier, v and I are reference voltages, and Vo is an output voltage. Switch SI is the LSB side of the input digital value, switch S. is on the MsB side, and these switches SI+S2+...S, are switched to the ground side if the bit is 0, and to the output line side if it is 1, so that the amplifier OP corresponds to the input digital value. Generates analog output Vo.

Accuracy of AC like this is, except for non-linear ones like C0DEC, the error is how many LSBs from the full scale.
The rules are set in such a way as to ensure that the conditions are met. For example, with a 12-bit DAC, when the reference voltage is 5μ, I
LSB will be 1.25 mV, but this DAC will be +
It is defined as ILSB, that is, an accuracy of ±1.25 mV. It does not specify an error for the output signal. When shown in a graph of the output analog value against the input digital value, the error compensation range has a constant width as shown in FIG. 6(a).

However, in this case, when the digital value is small, the error appears relatively large. Since the precision of an analog signal is considered as a ratio to the signal itself (what percentage of the signal value is an error), a similar graph is shown in FIG. 6(b). That is, the error is small where the digital value is small, and the error is large where the digital value is large. If the accuracy regulation as shown in (a) is a small error that can be satisfied at a small digital value, then an unnecessarily high precision is required at a large digital value.

Furthermore, the input/output characteristics of a DAC are often required to be monotonic, but if the number of bits is large, it will not increase monotonically, as shown in Figure 5 (b).
As shown by the arrows, it decreases in some areas. Figure 5 (a
) indicates the DA conversion characteristic, and ideally it is a 45° straight line, but when the actual one is enlarged, it is shown in Figure 5 (b) (C)
becomes. Although the formation of a staircase wave is unavoidable in principle, it is inconvenient that a recessed portion as shown in (b) is formed. Note that Fig. 5(b) and (C) are the same as Fig. 5(a).

Corresponds to 0 copies.

The reason why a recessed portion occurs is as follows. The DAC consists of resistors R, 2R and switches S l + S as shown in Figure 7.
2 +..., but the resistance has variations in resistance value, and the switch has parasitic resistance. Then, when the human-powered digital value increases by one digit, for example, 0111...
...1 to 1000...When the MSB is set to 0, the switch S, switches from the ground side to the output line side, and the switch S□l+5n-4+...,
S, simultaneously switches from the output line side to the ground side. This is a large change in terms of the above-mentioned resistance value variation and switch parasitic resistance, and a phenomenon occurs in which the input voltage to the amplifier OP decreases after switching than before switching, and as a result, the analog output voltage Vo decreases.

Sometimes it's an increase, not a decrease, but generally it's a decrease. That is, assuming that the current in the branch on the LSB side is I, as shown in Fig. 7, and that there is a resistance Rs in switch 7, and that there is no variation in resistance, then the branch point B1
The potential of is (2R+RS)to, and the potential of branch point B2 is 21
o R+ (2R+ Rs)1, so Ir(
2R+Rs) = 4 L R + I. It becomes Rs. This can be transformed into I+=2[.

-Rs Io/(2R+Rs). 1 if Rs=O
1=21. However, if there is Rs, ■, becomes RsIo/
(2R-t-Rs).

[Problem to be solved by the invention] As described above, conventional DACs do not consciously change the accuracy relative to full scale in response to digital data, so depending on the speed and resolution of the DAC, the accuracy required near full scale may vary depending on the speed and resolution of the DAC. The accuracy will be higher than that.

As a characteristic of a DAC having a wide dynamic range, accuracy equivalent to resolution is not required near full scale, but monotonicity may be required. In such a case, if a DAC with precision specified for full scale is used as in the past, an expensive AC with higher precision than necessary will be used.

The object of the present invention is to improve these points and to make it possible to achieve practical accuracy and monotonicity with a relatively inexpensive AC.

[Means for Solving the Problems] As shown in FIG. 1, in the present invention, a digital data masking circuit 12 is provided for the DA conversion circuit 10, and a control circuit 16 of the masking circuit and a top-level digital input A valid bit detection circuit 14 is provided.

If the DA conversion circuit 10 has n bits, and therefore the digital input is also n bits, then the mask circuit 12 converts m consecutive bits from the first 1 on the upper side of the n bits (it upper significant bit) (m<n) remains as is, the remaining n-m bits are the same as the two 0s up to the first 1\and the m
Remaining vias on the lower side of the bit) n-m-1 are all 0
(all may be set to 1) and fed to the DA conversion circuit 10.

The above m is the number of bits necessary to guarantee the accuracy of the DAC.

[Effect]

The n-bit digital input to the DA conversion circuit 10 is expressed as follows, and the first 1 (most significant bit) on the upper side is a.
n-j! Suppose that it is -1.

a r+an-1+ ”””+ a n-11+an-
Love-ll “””+ a n-north-n+a ll-1
-s-1+ ”'”' a + mask circuit 1
The output of 2 is as follows.

0+O+ ”'”' +0. a n-IL-1+”
'''' + a, I-j!-s+o+ ”・”'
+0 The first 0,0 . of this output. ......, 0 is"
Ill arl-11...a a-ffi,
All of them are O's, but they have been passed through as is. next a
n-ff1-1+"""+an-jLM is an-1-
Since 1 was the first 1 on the upper side, this 1 and the following m-
One bit passed through as is, and the last 0,...
..., 0 is a ++-ffi-m-1+...
・With +al, regardless of the value, it is passed by setting it to all 0s (it may also be set to 0. This annotation will be omitted below).

To perform this processing, it is necessary to detect the first 1 on the high-order side, that is, the most significant valid bit, and the detection circuit 14 performs this. Furthermore, when the most significant valid bit is detected, the continuous m bits including the most significant bit are passed through as is, and all other bits are passed as 0. This control is controlled by the control circuit.
6 will do it.

In this way, even if there is an n-bit digital input, only the continuous m bits including the most significant bit are DA converted, and the bits lower than the m bits are truncated (when set to 0) or all Although it is rounded up to 1, the accuracy can be guaranteed with m bits, so the rounding up can be ignored.

Then, when the lower n-m-1 bits are rounded down/rounded up, the corresponding switch of the DAC S R-11-1+...
・+S I is fixed to the state of 0 or 1, and the above 1
Since they do not switch all at once even when carrying up, no recesses occur and monotony can be guaranteed.

In the present invention, the number of bits to be truncated/rounded up (n-m-1) increases as the MSB (most significant bit) of m bits is in the lower middle of n bits. This is reversed as the distance increases, so the error range is as shown in Figure 6 (
b).

〔Example〕

An embodiment of the DAC of the present invention is shown with a resolution of 15 bits and an accuracy of 8 bits ILSB. The bit is set (1) in 15-bit input data.
8 consecutive bits starting from the most MSB bit (most significant bit)
The bit is used as is, and the lower data bits are all set to the same value of 1 or 0, regardless of the data value of 1.0. This processing is performed by the mask circuit 12, and the processing results are shown in the following table. The upper row of each pair shows the human data before processing, and the lower row shows the data after processing. In this example, data lower than 8 bits is set to 0.

Table 1 In Figure 2, 21.22 is the priority encoder (8
-Line to 3-Line 0ctal Pr
1ority encoder), 0 to 7 are its 8-bit inputs, A and BC are outputs, I is an enable input, and EO is an output horn. Circuit configuration of encoders 21 and 22 (2).

22 also has the same configuration) is shown in FIG. Output AO, A1, A
2 corresponds to A, B, and C above. GS is a group signal output. Table 2 shows the function table.

/ / (In addition, between a IS+ 314+...etc. and each numerical value.

is entered, but this will be omitted) This process requires detecting where the most significant bit is among the 15 input bits (in example 1, a15 is the most significant bit, and in example 2, a14 is the most significant bit) valid bit,
. . . In example (2), all is the most significant effective bit), and a specific example of the most significant effective bit detection circuit 14 that performs this is shown in FIG.

Note Table X is an arbitrary level. As shown in this table 2, encoders 21 and 22 are
Output A2. which indicates the position of 1 from the high-order side of the bits (21 is 7 bits) (or L because it is inverted) in binary. Generates AI and AO. This encoder is L(
low) is active and therefore the upper encoder 2
The L level is input to El of 1. When the upper encoder 21 cannot detect the most significant bit, the lower encoder 22 becomes active upon receiving E◯=L at El. Since the encoder 21 searches for the most significant effective bit from the upper 8 bits, H is entered in the input cuff and this is always set to 01. The position of the highest effective bin 1- detected in this embodiment is 1514.13.・・・・・・8
There are 8 types of 1111.1110, which DCBA
．． 1101. ...It is expressed by being 1000.

A specific example of the mask circuit 12 and its control circuit 16 is shown in FIG. 31.32 is a decoder (3-Lineto 8-
1, 2, 3, . . . . According to 15, one of the output terminals 0 to 7 is set to L. Outputs 1 to 7 of the lower decoder remain as they are (corresponding to the above outputs 1 to 7, O is not used), and the output O...7 of the upper decoder 32 is 8...・Corresponds to 15. Therefore the input DCBA
If is 1111, the decoder 32 output is 11, all other outputs are 11, and if the input DCBA is 1110, the decoder 3
Output 6 of 2 becomes H, and all other outputs become H, and the following applies accordingly.

In addition, 41 to 55 are Nant gates (only 55 is imparked because it is operated by one person), and the input thereof is common to each of the 8 gates from the MSB side, and is sequentially shifted one by one to the decoder 32.
connected to the output of In other words, the inputs from 55 to 48 go to the cuff at 32, the human power from 54 to 47 goes to the output 6 at 32, etc.
・Connected, 47 to 410 to the cuff of the decoder 31
The inputs 46 to 41 are connected to the output 6 of the decoder 31.

These Nant gates 41-55 and decoders 31.32
constitutes the mask control circuit 16. The digital data mask circuit 12 is composed of AND gates 61 to 75. A 15-bit digital input is input one bit at a time to these 15 AND gates, and 15 NAND gates 41 to 5 are input to the other inputs of these AND gates.
5 outputs are manually powered one by one.

Therefore, the total most significant bit detection output DCBA is 1111
When the output voltage of the decoder 32 becomes L, the outputs of the Nant gates 48 to 55 become H, and the AND gate 68
.about.75 is opened and outputs the most significant 8 bits of the 15-bit digital input. If DCBA is 1110, the output 6 of the decoder 32 becomes L, and the Nant gates 47 to 54
produces an H level output, AND gates 67-74 open and output the 8 bits from the next most significant bit of the 15-bit digital input. The following shall apply accordingly.

〔Effect of the invention〕

As explained above, in the present invention, an n-bit DA conversion circuit is used for n-bit data input, but only m bits from the most significant effective bit are input to the DA conversion circuit using a mask circuit. Therefore, there is no loss of single-81st character due to changes in the lower bits, and the accuracy can be kept at a constant ratio (ILSB of i9m bits) according to the input data.

The present invention is effective when a wide dynamic range is required, accuracy can be guaranteed not as a ratio to full scale but as a ratio to analog output, and monotonicity of DA conversion characteristics is essential, especially for control signals with a wide dynamic range. is effective in the feedback control system used.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the principle of the present invention, Figure 2 is a block diagram of the most significant bit detection circuit, Figure 3 is a circuit diagram of a mask circuit and its control circuit, and Figure 4 is a detailed diagram of the encoder shown in Figure 2. FIG. 5 is an explanatory diagram of DA conversion characteristics, FIG. 6 is an explanatory diagram of DA conversion error, and FIG. 7 is a circuit diagram of an R-2R type DA converter. In Figure 1, IO is a DA conversion circuit, 12 is a digital data mask circuit, 14 is a most significant bit detection circuit, and IO
is the mask control circuit.

Claims (1)

[Claims] 1. A plurality of (n) bits of DA conversion circuit (10) receives the plurality of (n) bits of digital input, and starts from the most significant effective bit which is the bit set to 1 and is the most significant bit. A predetermined plurality of (m) bits on the lower side and all bits that are 0 on the upper side than the predetermined plurality of bits are left as they are,
and a digital data masking circuit (12) that sets all bits lower than the predetermined plurality of bits (m<n) to a constant value of 1 or 0 and supplies the digital data to the DA conversion circuit, and the most significant effective bit of the digital input. a most significant valid bit detection circuit (14) for detecting; and receiving the output of the detection circuit;
A DA converter comprising a mask control circuit (16) that generates a signal that causes the mask circuit (12) to process the digital input.