JPH0257016A - Automatic gain control circuit - Google Patents

Abstract

PURPOSE:To widely enlarge the dynamic range of an analog input signal by using a DELTASIGMAAD converter. CONSTITUTION:An analog input signal A and a signal, which causes the analog input signal A to pass through a rectifying and averaging circuit 21, a mixing circuit 20 and a switch 23 and defines it as a reference voltage, are supplied through a feedback loop to an adder 13 of an AD converter 10. Then, an adding output is supplied to the negative side input terminal of an operational amplifier 11. The output of the operational amplifier 11 and the reference voltage through the feedback loop formerly are supplied to the negative side input terminal of the operational amplifier 12. Thus, after only the difference of analog quantity to correspond to preceding digital data is obtained to the analog input signal which is newly incoming, integration is executed. The analog input signal A is sampled at a high speed by a clock pulse f, converted to a digital output B of 1 bit and taken out.

Description

[Detailed description of the invention] [Industrial use 1! i'] The present invention allows the signal to be taken out as an output to remain at a constant level even when the analog human input signal level changes.
:Automatic gain control that automatically adjusts interests (8GC)
) It is something that adds IJJI to the circuit.

[Conventional technology] A conventional automatic gain control (iC) circuit uses an operational amplifier, a rectifying and averaging circuit, and a voltage controlled variable resistor (VCR) as shown in Figure 3, for example. Are known. To explain the operating principle of the GC circuit, VCR
As the control voltage increases, the resistance value decreases, and conversely, as the control voltage increases, the resistance value increases. In the circuit shown in Fig. 3, when the input terminal is small, the output of the rectifying and averaging circuit is small (lx), so the control voltage becomes low and the resistance value of the VCR becomes large. Since the input to the amplifier is a divided voltage value of the fixed resistor R and VCH, the human input value becomes large and the gain is increased. On the other hand, when the input terminal is low, the VCR f7) resistor (iii becomes small, the input value to the amplifier becomes small, and the gain is reduced) becomes f.

In order to keep the output level constant in this circuit, it is necessary for VCIt to be very small and the resistance value to vary greatly depending on the control voltage.

In general, VCRs use transistors or field-effect I-transistors (FITs), and in such cases, the conventional 71 G The output level changes depending on the human power level because the VCR or oven status changes depending on the human power level, and the output level also changes depending on the human power level because the on resistance of the VCR remains constant at high and high power levels. As a result, the dynamic range of the conventional 8GC gain control is limited. Moreover, the resistance value of the one-heran transistor or FLiT used for vCH changes depending on the voltage between its collector and emitter, so there is a drawback that distortion occurs when an alternating current signal is applied.

[Problem to be solved by the invention] Therefore, the purpose of the present invention is to increase the dynamic range of an analog input signal, and to solve the problem of whether it is necessary to have a highly accurate circuit configuration. It is an object of the present invention to provide a GC circuit which is less susceptible to damage and which is suitable for MOS-LSI implementation and which automatically performs profit control.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides an analog signal with a frequency fs that is 10 times or more than the frequency of the analog signal (No. A ΔΣΔD converter means for forming a digital signal of , a signal mixing means that supplies the feedback loop of the △ΣAD converter means as a reference voltage, and a signal mixing means that performs DA conversion on the outputs of the ΔΣAD converter means and then removes high frequency components to maintain a constant level despite fluctuations in the analog signal level. The fact that the filter means is provided with a filter means for taking out No. 43 whose gain has been adjusted as shown in FIG.

Here, -J double frequency f8 is set to 10 or more, preferably several tens of f4 or more, preferably several hundred times or more of the frequency of the analog human input signal.

[Function] According to the present invention, by using a ΔΣAD converter, the dynamic range of an analog human input signal can be broadly expanded, and it is less susceptible to the influence of noise.
Furthermore, there is no need to make the circuit configuration highly accurate, and the entire circuit can be made into a MOS-LSI. Furthermore, since the ΔΣ-type converter has an output completely synchronized with the clock, A[iC
Fill to get the output.

It is also suitable for the filter means to be composed of a switched capacitor filter.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

An embodiment of the present invention is shown in FIG. 1, and examples of signal waveforms at various parts thereof are shown in FIGS. 2(A) to 2(D).

In FIG. 1, .lO is a ΔΣ type 8 to converter. The AD converter 10 itself has a known configuration, and here an example of a second-order ΔΣ type AD converter is shown.

Here, 11 and 12 are operational amplifiers, 13 and 14
is an adder, and 15 and 16 are operational amplifiers 11 and 1.
2 feedback capacitor, 17 comparator, 18 D
It is a type flip-flop.

Here, the analog input signal (8) is input to the input point a in Figure 1.
When input manually, it is supplied to the adder 13 of the AD converter 10, and is also supplied to the mixing circuit 20 via the rectifying and averaging circuit 21. In the mixing circuit 20, via the inverter 22 and directly, That is, the signals are supplied to the inner input terminal of the switch 23 with mutually opposite phases.

The switch 23 is activated depending on the data content of the digital signal (B) which is the output of the converter lO shown in FIG. A switch that is switched, and depending on its operation, for example, an analog human input signal (A) or a second
In the case of a signal having an amplitude of the peak value In the case of a signal having a value Y, a pulse signal having an amplitude of the reference voltage β is supplied to the adder 13 and the adder 14 via the switch 23.0 point and the feedback loop of the AD converter 10.

As described above, the adder 13 of the AD converter IO receives the analog human input signal (A) and the analog human input signal (Δ).
A reference voltage is supplied through a rectifying and averaging circuit 21, a mixing circuit 20, and a switch 23 through a feedback loop, and the summed output thereof is supplied to a negative input terminal of an operational amplifier 11. The output of the operational amplifier 11 and the reference voltage via the feedback loop are supplied to the adder 14, and the added output is supplied to the negative input terminal of the operational amplifier 12. The positive input terminals of operational amplifiers 11 and 12 are connected to analog ground potential, and comparator 17 compares the output from operational amplifier 12 with the analog ground voltage. If the output is greater than ground voltage, '! ”, otherwise “0°°” is output. flip flop 18
The pig input terminal of is the binary output from comparator 17°
"0°° or 1°' is supplied, and a clock pulse f having a frequency more than 10 times the frequency of the analog human input signal (8) is also supplied to the tarock input terminal, and in synchronization with that clock pulse. A data value of 0"' or 1°" from the comparator 17 is taken in. The output of the flip-flop 18 is passed through a 1-pill DA converter 30 and a low-pass filter 31 to the output (D
) and controls the operation of the switch 23. That is, here, the analog human input signal (A) is rectified and averaged by a circuit 21, a mixing circuit 20, and a switch 23.
Based on the voltage obtained through! 18 voltage, when the output of flip-flop 1B is '1', it is - (reference voltage), and when it is '0', it is + (reference voltage).
are added to adder 13.14 via a feedback loop, and fed back as a difference to operational amplifier 11.12, respectively. Thus, for a newly incoming analog input signal, an analog quantity or difference corresponding to the immediately preceding digital data is taken, and then integration is performed.

In this way, the analog human input signal (8) is sampled at high speed using the clock pulse fs, as shown in Fig. 2 (B).
Shown in J: Digital output of sea urchin, 1 pit 1~ (B)
is converted to and extracted.

This digital signal (B) is an analog human signal (8)
When is X, the pulse train has a duty ratio proportional to x/α, and when it is Y, the pulse train has a duty ratio proportional to Y/β. However, since the flip-flop 18 operates with the clock pulse fg, the pulse width of the digital output is l/fS (seconds).
It only takes values that are integral multiples of , and is a digitally discrete quantity. The duty ratio is ΔΣ type 8D.
It changes depending on the amplitude and polarity of the analog signal supplied to the converter 101ζ, and when the amplitude is zero or no im signal, it is 50%, and as the amplitude becomes positive and the amplitude increases, the number of sections of °' Bi increases; As the amplitude increases, it becomes 0°'
The number of sections increases.

Based on the above explanation, the operation of the uninvented AGC circuit will be described. z/l, that is, an analog force signal having a peak value
Assuming that, the signal arriving at the output point of the AD converter 1o is tic as shown in Figure 2 (B).
It is 1.1' with the digital number of 1~. This digital signal is a pulse transmission having a duty ratio proportional to
By passing through the low-pass filter 31 and removing high-frequency components, the peak value X as shown in FIG.
An output signal with . The amplitude X of this signal is proportional to the duty ratio of the 1-bit digital signal.

Next, there is a high (
Assuming that the reference voltage of the corresponding feedback loop is β, one digital signal arriving at the output point of the AD converter 10 is Y/β. By passing through the DA converter 3o and the low-pass filter 31, output No. 5 having a proportional duty ratio and having a peak value y as shown in FIG. 2(D) is obtained.

By the way, the signal (C) at the 0 point of the loop 1-2 from the switch 23 to the feedback loop is the rectified and averaged human-powered alley log signal inputted to the human-powered point a, so the signal (C)
) is proportional to the amplitude of the analog signal manually applied to the width of the human force a. From this, it becomes X/α-Y/β, and when the human-powered analog signal X is added to the human-powered point a, the duty of the digital signal (B) is・The ratio is the same as t2. These are DA converter 3o
Since the amplitude of the signal obtained after passing through the low-pass filter 31 is proportional to the duty ratio of the digital signal ([1), the amplitudes X and y of output signal No. 8 are equal.

However, because of the circuit configuration of the present invention, even if the human power level of the analog human power signal changes, C remains constant at the output point d, and an output signal with a bell amplitude can be obtained, and the gain is automatically adjusted. An AGC circuit that performs this will be realized.

As mentioned above, the output of the AGC according to the present invention is output from the converter 10, is passed through the converter 30 and the low-pass filter 31 that removes high-frequency components, and is extracted from the output point d, or is the input thereto. The level versus output level characteristic is almost constant at almost all levels, as shown by the dotted line in FIG. 4, and it is possible to greatly expand the dynamic range of the analog human input signal. In addition, in conventional 8GCs that use 1-run transistors and FETs in VCRs, the resistance value of the transistors and FETs also changes depending on the voltage between their collectors and emitters, so when AC signals are applied, distortion may occur. In the present invention, such a problem does not occur.

The low-pass filter 31 may be configured as a passive filter using a CR or an active filter using a CR and an operational amplifier.

Furthermore, as a feature of the present invention, this low-pass filter can be directly constructed from a switched capacitor filter without inserting an anti-aliasing filter. In this case, the frequency fs of the sampling clock of the converter lO and the jimping clock fCLK of the switched capacitor filter are set equal,
And the frequency is determined to be sufficiently high relative to the passband.

Since the frequency spectrum of the output (n) of the to-D converter lO does not have energy near an integral multiple of the frequency fS, ie, fcLy, the present invention does not require a folding filter.

Note that in the ΔΣAD converter, the quantization noise increases rapidly on the high frequency side, so in order to improve the frequency characteristics of the quantization noise, it is necessary to use an operational amplifier, for example, as in the circuit configuration shown in Figure 1. Connect integrators using multi-stage groups M,
Or change the DA converter 30 to 2 bits instead of 1 bit.
Make it multi-valued like ~ etc.

FIG. 3 is a block diagram of the conventional example, and FIG. 4 is a diagram of the human power level versus output bell characteristic of the present invention and the conventional example.

[Effects of the Invention] As is clear from the above, by using the ΔΣAD converter, the dynamic range of the analog human input signal can be greatly expanded compared to the case where an RCV using an l-run transistor or FET is used. It is not easily affected by noise, and there is no need to make the circuit configuration highly accurate, and it is suitable for implementing the entire circuit into an M[1S-LSI. Furthermore, since the ΔΣ-type converter has an output completely synchronized with the clock, it is also suitable for constructing a filter means for obtaining a GC output from which high frequency components have been removed using a switched capacitor filter.

10...Converter to ΔΣ type 8, 11, 12... operational amplifier, 13, 14...adder, 15, lli... capacitor, 17... comparator, 18...D type flip-flop, 20...mixing circuit, 21... rectification averaging circuit, 22...Inverter, 23... switch, 30...DA converter, 31...Low pass filter.

[Brief explanation of the drawing]

Claims (1)

[Claims] 1) An analog signal with a frequency of 10
ΔΣAD converter means for sampling at a frequency f_s that is more than twice as high as the frequency f_s to form a 1-bit digital signal, and branching the analog signal from the input to the ΔΣAD converter means, rectifying and averaging it, and then converting the analog signal into the 1-bit digital signal. a signal mixing means that switches between positive phase and reverse phase according to the signal and supplies it as a reference voltage to the feedback loop of the ΔΣ AD converter means; An automatic gain control circuit comprising filter means for extracting a signal whose gain is adjusted to a constant level despite fluctuations in the analog signal level.