JPH0256858B2 - - Google Patents

Description

[Detailed description of the invention] The present invention is a MOS type FET (field effect transistor)
It was used as an analog switch to select multiple sensors that generate minute currents as output, such as silicon photodiodes used in camera distance measuring devices.
This invention relates to a control device that controls the gate voltage of a MOS FET.

MOS configured as a conventional analog switch
In order to increase the noise margin of type FETs, especially CMOS-FETs, the positive and negative power supply voltages in the system are adjusted to give the gate that controls the switching action of the analog switch the maximum amplitude voltage that can be obtained in the system. I was adding it. An analog switch and its system constructed in this manner are shown in FIG.

BAT is a power source with internal resistance such as a battery, and its positive electrode side is connected to the line indicated by Vcc, and its negative electrode side is connected to the line indicated by Vcc.
Connected to the line indicated by GND. iRED is a near-infrared light emitting diode, and according to the output signal of the logic circuit CLC composed of CMOS-FET,
Flashed by iRED driver iD. SPD1 and
SPD2 is a silicon photodiode, and this diode is a sensor that converts the reflected light emitted to the outside world by iRED into a current, and SPD1 has an analog switch consisting of a MOS FET in parallel.
NS1 and PS1 are connected, and MOS type FET
Analog switch NS2 and NS2 consisting of
are connected in series.

fC is an impedance element connected to the feedback circuit of amplifier SA, AC is a signal processing circuit connected to the output terminal of amplifier SA, and calculates the distance to an object (not shown) according to the output signal of amplifier SA; MOS type that makes up the switch
The gates of NS1 and PS2 of FET are logic circuits.
NS2 and PS1 are connected to the signal line G1 of the CLC, and NS2 and PS1 are connected to the signal line G2, respectively, and when G1 is at a high level (hereinafter abbreviated as HL) and G2 is at a low level (hereinafter abbreviated as LL), NS1 and PS1 are electrically connected. NS2 and PS2
becomes non-conductive, and conversely, G1 becomes LL and G2 becomes HL.
When NS1 and PS1 are non-conducting, NS2 and PS
2 becomes conductive. Also, the back gates of NS1 and NS2 are connected to GND, and the back gates of PS1 and PS2 are connected to Vcc.

In this example, if you try to measure some quantity in the outside world by blinking the iRED at a constant cycle and emitting that light to the outside world, then detecting the light that is reflected from the outside world and entering SPC1 and SPC2, you will notice a large change in the load due to the blinking of the iRED. Along with this, the voltage on the line Vcc fluctuates. The power supply of logic circuit CLC is Vcc and GND
form a logic circuit from the given
Due to the nature of CMOS-FET, the high level of the logic circuit corresponds to the voltage of the line Vcc, and the low level corresponds to the voltage of the line GND. Therefore, the signal line G1 or G
Of the two, the one that becomes high level becomes a signal whose voltage fluctuates as the line Vcc fluctuates.

Now, let's consider the characteristics of the analog switch when the amplitude of the signal voltage applied to the gate changes in this way. FIG. 2a represents one of the analog switches shown in the first figure, where G is the gate, D is the drain, S is the source, and BG is the back gate, and its equivalent circuit is as shown in FIG. 2b. In Figure 2b, R _OFF is insulation resistance, R _ON is conduction resistance, D _DS is source-drain capacitance, C _GS is gate-source capacitance, C _GD is gate-drain capacitance, and C _BGS is backgate-source capacitance. capacity,
C _BGD is the back gate-drain capacitance, and isw is the ideal switch. As can be easily understood from this, if the drain D (see Fig. 2a) or the source S (see Fig. 2a) is connected to G (see Fig. 2a) or the back gate BG (see Fig. 2a) When the applied voltage changes, current flows from the gate or backgate to the drain or source through each of the capacitances mentioned above (see FIG. 2b).

Therefore, as mentioned above, when the voltage applied to the gate or back gate of the analog switch changes as the iRED blinks, current flows from the signal line G1 or G2 to the input of the photocurrent detection amplifier SA through each capacitance shown in Figure 2b. flows, and a false signal is generated.
In the example of FIG. 1, the erroneous signal components generated in this way have a certain correlation with the true signal components, and it is extremely difficult to remove the erroneous signal components in subsequent processing. In particular, when techniques such as synchronous rectification are used for signal processing, it becomes indistinguishable from the true signal component.
Such synchronous noise needs to be sufficiently small.

The present invention has been made in view of the above-mentioned circumstances, and is made by projecting a signal light from a light projecting means, receiving the reflected light by a light receiving means, and processing the output of the light receiving means by a processing circuit. A control device for an analog switch for inputting the output of the light receiving means to the processing circuit in a distance measuring device that measures distance, the FET constituting the analog switch;
A power source that drives the light projecting means, and a power source that converts the output of the power source into a constant voltage so that voltage fluctuations of the power source caused by driving the light projecting device do not affect the FET, and a constant voltage means for applying a constant voltage to the gate and back gate of the light projecting means, the control device is configured to prevent the analog switch from generating noise in response to fluctuations in the power supply voltage due to driving of the light projecting means. This is what we are trying to provide.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a circuit connection diagram of an embodiment of a distance measuring device to which the present invention is applied. It should be noted that elements having the same functions as those shown in the first figure are designated by the same reference numerals, and description thereof will be omitted. In FIG. 3, AC is a signal processing circuit having the same function as that shown in FIG. It has a constant voltage source (not shown) that outputs VC. The output of the constant voltage source is connected to a MOS FET that constitutes an analog switch via the power supply line LVc.
It is connected to the back gates of P channels PS1 and PS2, and also connected to the back gates of P channels PS1, PS2, NS1,
It is also connected to one end of resistors R1 and R2 for raising the gate voltage of NS2 to a constant voltage Vc. The other ends of the resistors R1 and R2 are N-channel with their sources and back gates connected to the line GND.
Connected to the drains of MOS type FETNB1 and NB2. The gates of NB1 and NB2 are CMOS as shown in Figure 1.
- Logic circuit composed of FET A logic circuit that controls the operating order of a rangefinder similar to the CLC.
Controlled by CLC, its drain voltage is NB1,
When NB2 is on, it has the potential of line GND,
When off, it has the potential of line LVc.

When the logic circuit CLC causes the gate voltage of NB1 to become the voltage of the line Vcc and the gate voltage of NB2 to become the line GND, the source and drain of NB1 become conductive, and the drain voltage becomes equal to the voltage of the line GND. At this time NB1
The gate voltage of NB1 is given a voltage that changes depending on the iRED blinking, but the source of NB1 is connected to the ground line.
Since the drain is connected to the line GND through NB1's own channel, the current flowing through the gate-drain and gate-source capacitance flows into the line GND, so the drain of NB1 is connected to the line GND, so the iRED flashes at the drain of NB1. There will be no impact. On the other hand, since the voltage of the earth line GND is applied to the gate of NB2, no current flows from the gate through each capacitor, and the drain and source are insulated, and the drain voltage becomes the voltage Vc of the line LVc due to the resistor R2. In this state, the gates of PS1, NS2 and NS1,
The voltage of the earth line GND is applied to the back gate of NS2, and the voltage Vc of the power line LVc is applied to the gates of NS1 and PS2 and the back gates of PS1 and PS2. NS1 and PS1 are in conductive state,
NS2 and PS2 are insulated and shoot out the current generated in SPD1. At this time, sensor SPD1,
SPD2, inverting (-) and non-inverting input (10) of amplifier SA, analog switch NS1, PS1, NS2,
The drain and source of PS2, and according to the present invention, all voltages at terminals related to minute currents, such as the gate and back gate of each analog switch, become constant voltages. ) becomes constant, and no current flows through this capacitor.

Therefore, the current generated in SPD2 is correctly connected to the amplifier
The voltage is transmitted to SA and converted into a voltage according to a constant determined by impedance element fc.

When the logic circuit CLC causes the gate voltage of NB1 to become the potential of the line GND, and the gate voltage of NB2 to the potential of the line Vcc, conversely, NS1 and PS1
is in an insulated state, NS2 and PS2 are in a conductive state, and the sum of the currents of SPD1 and SPD2 is transmitted to the amplifier SA and converted into a voltage in the same manner as in the above case.
The signal is then converted into a signal representing the distance to the object in the signal processing circuit AC.

If the resistors R1 and R2 are formed on the IC using base diffused resistors, etc., the analog switch can be made to have even lower noise by applying an appropriate constant voltage such as the constant voltage Vc to the epitaxial growth layer thereof. be able to.

Figure 4 shows the resistance R in the embodiment shown in Figure 3.
1, R2 is P-chan MOS type FET, PB1, PB2
Replace this part with CMOS configuration, and further
The gate signals of PB2 and NB2 are obtained from the output of the gate composed of PB1 and NB1. The back gates of PB1 and PB2 are connected to the signal processing circuit via the power supply line LVc as shown in Figure 3.
The voltage of G3 and G4, which are connected to an AC constant voltage source (not shown) and whose drains are connected, becomes the potential of line Vcc or line GND,
Similar to the embodiment shown in FIG. 3, no erroneous signals are generated.

According to this example, resistive loads R1 and R2 are active loads.
G3 and G4 by replacing PB1 and PB2
The time required for the voltage to change from the line GND level to the line Vcc level can be shortened, and the current consumption of the circuit can be reduced. The voltage must be as high as possible.

Theoretically, the threshold voltage V _T of a MOS FET
can be made to any value, but with the current process technology, the variation in the voltage V _T is large, and as the constant voltage Vc decreases, it is difficult to realize a circuit configured as shown in Figure 4 with an IC at a good yield. It becomes familiar.

The same thing can be said about PS1 and PS2, which are P-channel MOS FETs that make up the analog switch, but even if these two FETs are not conductive, NS1 and NS2 are enough to operate as an analog switch, so V _r and V _T Due to the variation in
Even if the configuration shown in the figure is forced, adding PS1 and PS2 may work for the better, but there will be no negative impact. Of course, a modification in which PS1 and PS2 are omitted in FIG. 3 is also conceivable.

Furthermore, NB1 and NB2 in FIG. 3 and NB1, NB2, PB1, and PB2 in FIG. 4 can each be constructed using bipolar transistors.

As explained above, according to the present invention, the distance is measured by projecting signal light from the light projecting means, receiving the reflected light from the light receiving means, and processing the output of the light receiving means in the processing circuit. In distance measuring equipment,
inputting the output of the light receiving means to the processing circuit;
The analog switch constituted by an FET can prevent noise from being generated due to fluctuations in the power supply voltage accompanying the driving of the light projecting means, thereby preventing malfunctions of the distance measuring device.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a conventional analog switch, Figure 2 a is a configuration diagram of a MOS FET, and Figure 2 b is a circuit diagram of a conventional analog switch.
FIG. 3 is an equivalent circuit diagram of the illustrated FET, FIG. 3 is a circuit diagram of a distance measuring device to which the present invention is applied, and FIG. 4 is a circuit diagram of another embodiment of the present invention. In the figure, NS1, NS2, PS1, PS2...
MOS FET, AC...A signal processing circuit that includes a constant voltage source.

Claims (1)

[Claims] 1. A distance measuring device that measures distance by projecting signal light from a light projecting means, receiving the reflected light by a light receiving means, and processing the output of the light receiving means in a processing circuit. A control device for an analog switch that inputs the output of the light receiving means to the processing circuit, the FET constituting the analog switch
and a power source for driving the light projecting means, and converting the output of the power source to a constant voltage so that voltage fluctuations of the power source caused by driving the light projecting means do not affect the FET. A control device comprising constant voltage means for applying a constant voltage to the gate and back gate of the FET. 2. The constant voltage means outputs the constant voltage.
The control device according to claim 1, characterized in that the control device includes a series circuit of a resistor and a transistor. 3. The constant voltage means outputs the constant voltage.
The control device according to claim 1, characterized in that the control device includes a series circuit of transistors. 4. The constant voltage means includes a first series circuit of transistors and a transistor, and a second series circuit of transistors whose gate is controlled by the output of the first series circuit and outputs the constant voltage. A control device according to claim 1, characterized in that: