JPH0256616A - Clock skew adjusting circuit - Google Patents

Abstract

PURPOSE:To decrease a clock skew between LSIs by measuring a delay time per one stage of a gate in one LSI, adjusting the capacity of a variable capacity diode connected to some path between a clock input part of the LSI and a register by its result and adjusting the delay time. CONSTITUTION:When a delay time per one stage of a gate of LSIs 1, 2 is Tg1,2 (s/1 piece) and the number of gates extending from a clock input part to registers F11,21 is (n) pieces, clock skews of ¦Tg1-Tg2¦X(n) appear between the LSI 1 and the LSI 2. By counting a pulse of ring oscillators 2, 3, a delay time per one stage of a gate is measured, and adjusted to Tg1Xn+a1=Tg2Xn+ a2=Td, and a certain value by an increase (a1 (s)) of the delay time caused by the capacity of a variable capacity diode D11 of the LSI 1. In such a way, clock skews of ¦Tg1-Tg2¦X(n) between the LSI 1 and the LSI 2 can be eliminated.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a clock skew adjustment circuit, and more particularly, to a clock skew adjustment circuit that completely reduces the clock skew between LSIs caused by the gate delay time of each L8I. .

(Prior art) Conventionally, clock skew adjustment between LSIs was performed at the clock input section.
One path is selected, and if a malfunction occurs, the system changes to another path in order to determine a good path.

(Problem to be solved by the invention) The liffer is the clock skew inside the LSI y4!1
cannot be performed, and the latter is the clock input 7[1 of L8I.
This method prepares several paths from to the register, selects all of one path in advance, and in case of malfunction, tries another bus No. lj.

The work is internally focused, and the control signal can be switched using L8I.
Since it is performed externally, there is a drawback that a plurality of I10 pins are required for control signals, and some method must be prepared.

The object of the present invention is to eliminate the above-mentioned drawbacks.

An object of the present invention is to provide a clock skinny adjustment circuit that can adjust clock skew between LSIs by providing a circuit that adjusts the delay time of gates within the LSI according to the capacity.

(Means for Solving the Problems) To achieve the above object, the clock skinny adjustment circuit according to the present invention has the following features:1. II includes a ring oscillator, a counting control circuit that counts the number of pulses of the ring oscillator for a certain period of time given by an external signal, and outputs a binary count value, and a binary count output line of the counting control circuit. , a plurality of differential amplifiers each having a control terminal connected thereto, a variable capacitance diode and a taff having one end connected to all the outputs of the plurality of differential amplifiers and the other end connected to a gate in the LSI, It is configured to reduce the clock Φ skinny between LsI.

(Example) The present invention will be described in more detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a clock skew adjustment circuit according to the present invention.

The one-shot circuit 1 generates a pulse whose logic is 1 for a certain period of time (assumed to be Ts) and whose logic is ````θ'''' at other times.

In the LSI 1, the gates 011 to 015 constitute an oscillator 2. A11 is an AND gate, which transmits the pulse of the ring oscillator 2 to the counting control circuit 4 for the time Ts during which the next pulse is in the logic "1" state.

A binary count bit output line 4a of the counting control circuit 4 is connected to the base of one transistor Q11 of the differential amplifier 6. Similarly, binary count bit output lines 4b, 4C
, 4d is one transistor Q of the differential amplifier 7.8.9
13. They are connected to the bases of Q15 and Ql7, respectively. The structure of each pair of transistors in each differential amplifier 6 to 9 is connected to the power source -V through a constant current circuit. On the other hand, the other transistor Q1 of each differential amplifier 6 to 9
2. Q14. Q16. The base of Ql8 is connected to a variable resistor VR that increases the reference voltage by 4, and its collector is connected to ground.

Transistors Qll, Ql3. Ql5. Q17ノ*
Il' is connected to ground via a resistor R, 11k, and to the anode of a variable capacitance diode D11. The cathode of the variable capacitance diode Dll is connected to the connection point between gates B11 and B12 to which a clock signal is input.

As the counting control circuit 4 counts the pulses of the ring oscillator 2, the bit output lines are turned on from time to time, so some of the bit output lines are turned on in response to the output of the one-shot circuit.
1” condition.

Connected to the output line, the transistor 7 is turned on.

Transistors Qll, Ql3. Ql5. Since the current flowing through the resistor all is determined by the number of Ql7 that is turned on, the node potential of the variable capacitance diode DIl is determined, and the capacitance of the variable capacitance diode Dll is determined.

(Goo) The waveform transmitted between Bll and gate B12 changes to h17! due to the change in the capacitance of the variable capacitance diode. ``! Since the directions are different, the delay time between the gate B11 and the gate B12 changes.

In LaI3, the delay time between B21 and B22 can be changed in the same way.

Here, the delay time t-T for one gate stage of LSII
Assuming that the delay time per gate stage of LII2 is Tgz (S/1), and the number of gates from the clock input section to the register is n, the number of gates from the clock input section to the register is n. ni l Tgx −
Tgz l Xn glue c'yle24 two-ka appears. By counting the pulse sounds of the ring oscillator, the delay time per gate stage is measured, and the increase in delay time due to the capacitance of the variable capacitance diode Dll of LSI1 (a
* The moon ζ is (s) * T g * X n+α
By directly adjusting mTgzxn+a2-wTd and a certain constant (p, lT between LSI1 and LSI2
gx-TgzlXn clock skew? You can do it without any problems.

Adjustment to the above-mentioned constant value is performed by adjusting the counting control circuit 4.

That is, this is done by changing the number of output bit lines turned on for a fixed number of pulse counts.

The result is a ring oscillator tuned as above,
Clock skew adjustment circuit 2LS consisting of AND gate, counting control circuit, differential amplifier, and variable capacitance diode
11. By providing it in LSI2, mutual clock
It can be made into LSII and LS I 2 without skew.

(Effects of the Invention) As explained above, the present invention measures the delay time of the gate 1st stage friend 9 in one LS machine, and uses the result to measure the delay time of the gate 1 stage friend 9.
By adjusting the capacitance of the variable capacitance diode connected to a certain path between the clock input section and the register of the LSI and adjusting the delay time due to this capacitance, the delay time between the clock input section and the register can be kept constant. LS can be set to the value of
This has the effect that the clock skew between I and I can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a clock skew adjustment circuit according to the present invention. 011-015, 021-025...Gates All,
A21...And gate Rt1. R2x...Resistance Bll, B12. B21, B22...gate F1
1. F21...Registers Q11 to Q18. Q21-Q28...Transistor...One-shot circuit 2.3...Ring oscillator 4.5...Counting control circuit 6-13...Differential amplifier

Claims (1)

[Claims] In the LSI, a ring oscillator, a counting control circuit that counts the number of pulses of the ring oscillator for a certain period of time given by an external signal and outputs a binary count value, and each binary count output line of the counting control circuit, A plurality of differential amplifiers each having a control terminal connected thereto, and a variable capacitance diode having one end connected to all outputs of the plurality of differential amplifiers and the other end connected to a gate in the LSI, A clock skew adjustment circuit configured to reduce clock skew between LSIs.