JPH025642A - Error correcting system - Google Patents

Abstract

PURPOSE:To convert a burst error into a random error and to eliminate the deterioration of the error correcting capability caused by the burst error by transmitting signals encoded by an error correcting coder after dividing them into plural carriers of a multi-carrier system. CONSTITUTION:Signals of a code speed f0 are encoded in an error correcting state by a coder 1 and transmitted by different carriers after they are converted into (n) series of signals of code speeds f0/n by a series/parallel converter 6. Received signals are converted into one series of signals of the code speed f0 by means of a parallel/series converter 6 after they are respectively demodulated by demodulators 51-5n. While clock synchronization is required between each series of signals when the signals are transmitted in such way, apparent synchronization can be obtained when signals for frame synchronization are added to each series. The converted signals are decoded by means of a decoder 7. In digital radio communication, a possibility of simultaneous occurrence of deterioration in error rate at each transmission line by phasing is extremely small.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an error correction method in the field of digital wireless systems using multi-carrier communication systems. In order to prevent deterioration of line quality due to phase song, multi-carrier communication may be adopted.

FIG. 7 is a diagram showing the principle of multicarrier communication.

As shown in the figure, in this method, by dividing the transmission signal into multiple carriers 5050n with small frequency bandwidths and transmitting them, the overall 7-anong tolerance value can be greatly reduced compared to the case of a single carrier 51. In this case, the allowable value xdB becomes r+-xdB), and the aim is to reduce the influence of 7 A songs (Reference 1-Y).

Saito eLal, “Feasibility
Con5ideraLio++sof Higb-le
vel QAM Multi-Carrier Syst
em ICC'84 1984 pp 665-6
71 J).

On the other hand, in digital wireless communication, an error correction circuit is sometimes used in order to remove residual errors during steady state due to imperfections in relay devices.

FIG. 8 shows a block diagram showing an example of the configuration of a conventional digital radio system that uses multicarrier communication and error correction.

In the figure, 52. ~52n is an encoder, 531~53
11 is a modulator; 54. ~547. are the first carrier to the nth carrier, 55, ~55o are demodulators, and 561~
5 (3rd represents the decoder.

However, even with such a configuration, errors due to the 7-enong occur in bursts, which degrades the error correction ability.

Furthermore, the multicarrier method requires a plurality of encoders and decoders, which has the drawback of increasing circuit scale and cost.

On the other hand, coded modulation is a technology that combines error correction and modulation/demodulation (Reference [Q, Clugerbeock “C
hannel coding with Mul
Lilevel/phasesignals r
I E E E T trans, I 11for
mationTI+cory, vol I T
-281) I), 55-67Jun, 1982 J
reference). This is a method in which when arranging the signal space a, a method called set partition is used to set the minimum free distance between each code word as a large Euclidean distance on the signal space.

In addition, in order to obtain a larger coding gain than the conventional code ratio change: 11M, we have developed a multidimensional (2° dimension, n=2
, 3 ・・・・・・) The code is being considered.
(Text 'IRrA, R, Calderbank and
N.J.

S Ioclane ”Four-dia
+national modulation+ij
l+ an eiglit-state tre
llis code ″ AT&T Tecb,
Jour, vol 64 ppl 005-1
017 + May-June 1985 J) In order to further increase the minimum free distance, the conventional n
From the coded signal corresponding to 77 ping circuits, n
Output symbols as a set.

Next, these sets of symbols are subjected to parallel-to-serial conversion and transmitted (i) on one carrier. An example of the configuration of the transmitting side of such a multidimensional code is shown in a block diagram in FIG.

In the figure, 56 represents a multidimensional encoder, 57 a mapping circuit, 58 a serial rejection-serial converter, and 59 a modulator.

With such a configuration, a code with a larger minimum free distance can be obtained by optimizing the mapping method of n symbols.

For example, in a four-dimensional group code, redundant bits are added to two series of signals or consecutive 2y imshit signals.

In the example shown, three bits, which are two series of binary signals plus one redundant bit, are transmitted in two 4PSK symbols. At this time, the 3-bit signal, 000.001, .
. . . 111 is mapped (signal arrangement) to two 4PSK symbols. A feature of multidimensional codes is that this mapping method allows a large Euclidean distance between code words.

An example of the manping method is shown in FIG.

In the figure, (a) shows the case of the first symbol, (b
) indicates the case of the second symbol. For example, when the 3 bits including the redundant bits are 1.1°0, the first symbol becomes the symbol of the signal point indicated by the alphabetic character A in (,),
The second symbol is the symbol of the signal point indicated by the upper left alphabetical character B in (1)).

Problem to be solved by the invention C] In the coded modulation system as described above, when a burst error due to the 7-song occurs, multiple symbols of the - group symbols will be erroneous, and the error rate will decrease. leading to an increase.

Further, when configuring a circuit, parallel/serial conversion is required as explained with reference to FIG.

FIG. 11 shows a block diagram of a transmission system using a combination code.

In the figure, 60 is a first encoder, 61 is an interleaver, 62 is a second encoder, and 63 is a variable III! I, 64
is a carrier, 65 is a demodulator, 66 is a second decoder, 67
represents a de-interleaver, and 68 represents a first decoder.

Combination codes are a method of increasing error correction ability by placing two or more different types of error correction codes in series with information signals.In this case, after decoding the inner code, the error rate is However, the error 9 in the decoder output of 12 becomes bursty because the error caused by the error correction in the decoder is added to the error occurring in the propagation path.

Therefore, it is generally necessary to interleave the first code and the @2 code. However, when this combination code is applied to a system for high-speed signal transmission such as a digital microwave system, it is extremely difficult to construct an interleave circuit due to the access time of the memory and control circuit.

An object of the present invention is to provide an error correction system in a multicarrier zoinotal wireless communication channel that is capable of resolving the deterioration of correction ability due to burst errors mentioned above.

[Means to solve the problem]

According to the invention, the above-mentioned object is achieved by the measures defined in the claims.

That is, the first invention provides a multi-carrier communication method in which a transmission signal is divided into a plurality of carriers with a small frequency bandwidth and transmitted in digital wireless communication, on the transmitting side.
Code speed f. (bit/5ec) and an error correction encoder that outputs a signal of (bit/5ec), and each encoder output has a code rate f. /
A serial-to-parallel converter for converting into n-series parallel signals of n (bit/5ee) and a means for dividing and transmitting the n-series parallel signals to each carrier of a multicarrier communication system are provided, and a receiving side is provided with a , a receiver that receives the signals of each carrier, and a receiver that receives the n series of parallel signals at a code rate f. The second invention is an error correction method that is provided with a parallel-to-serial converter that converts the signal into a (bit/5ee) signal, and an error correction decoder that decodes the converter quantity Chi3. Divide 8 signals into multiple carriers with small frequency bandwidth; 17'! In a multi-carrier communication system that transmits data at a code rate f on the transmitting side. (bit/s
An error correction encoder outputs a signal of ec), and the encoder output is each encoded at a code rate f. / n (bit/se
c) a serial-to-parallel converter that converts the r1 series of parallel signals into 1249-detection encoders; , a means for dividing and transmitting the output of the column into each carrier of the multicarrier communication system, and a receiver for receiving No. 43 of each carrier on the receiving side, and the n
An error detection decoder detects errors in the 9F column signal of the series using the parity bits generated by the error detection encoder, and the output of the n series of the error detection decoder is set at a coding rate ∫0 (bit/sec ), an error correction decoder that decodes the error correction decoder output and the output of the parallel to serial converter before being decoded. The output of the error detection decoder is used as a control signal, and the output of the error correction decoder is output for the signal of the carrier in which an error has been detected. - is an error correction method that is equipped with a circuit that outputs the output of Moe's parallel-to-serial converter to be decoded, and the third invention is an error correction method that divides a transmission signal into multiple carriers with a small frequency bandwidth in digital wireless communication. In a multicarrier communication system that transmits a code rate f, the transmitting side has a code rate f. (bit/sec), and an error correction encoder that outputs a signal of
o / n (bit/sec) non-n series 4
A serial-parallel converter for converting into F-series signals, and a means for dividing and transmitting the n-series parallel signals into each carrier of a multicarrier communication system are provided, and the receiving fg side is provided with a means for transmitting the signals of each carrier. Ukei 88 to receive! and the n-series parallel signals are encoded at a code rate f. (1) A parallel-to-serial converter that converts into a signal of self/5ee, an error correction Viterbi decoder that decodes the converter output signal, and a circuit that determines whether there are many errors for each carrier. This is an error correction method that includes means for changing the branch metric of the Viterbi decoder depending on whether or not there are many errors for each carrier.

[For production]

The main feature of the present invention is that a signal encoded by an error correction encoder is divided into a plurality of carriers in a multi-kina 9 format and transmitted.

That is, in digital wireless communication using multicarrier transmission, each carrier transmits at a different center frequency. Therefore, even if frequency selective 7-enong occurs in the propagation path, the probability that errors will occur simultaneously in a plurality of carriers is extremely low. By dividing the signal into carriers using this property, burst errors can be converted to random errors, making it possible to make full use of the error correction ability.

Furthermore, when one beach correction device is used for each carrier as in the prior art, the number of devices increases, and the circuit scale and cost increase.

In contrast, in the present invention, one error correction device j1 performs error correction of No. 43 transmitted on multiple carriers.
It is possible to reduce the circuit scale and cost. Error correction was originally applied to microwave systems to eliminate residual bit errors, which are Langum errors. Therefore, random error re-correction is adopted.

However, this configuration is different from the conventional configuration in that the error correction ability can be fully demonstrated even in the 7-enong propagation path by randomizing burst errors using the uncorrelation of each carrier of a multicarrier.

〔Example〕

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In the figure, 1 is an encoder, 2 is a serial-parallel converter, and 3 is a serial-to-parallel converter.
1 to 3o represent modulators, 41 to 1.1 each represent the nth carrier of the first carrier, 5 to 5o represent demodulators, 6 represents a 1F sequence-to-serial converter, and 7 represents a decoder. .

Code speed f. The signal is error-corrected and encoded by encoder 1,
The code rate f in the serial-to-4L string converter 2.

/n is converted into 11 series signals, each of which is transmitted on a different carrier. Each received signal is sent to a demodulator 51.
~5. ．． The signal demodulated by the parallel-to-serial converter 6 has a symbol rate f. is converted into one series of signals.

At this time, the signals of each series must be clock synchronized, but by adding frame synchronization A and No. 1 to each series, apparent L synchronization can be achieved. Further, the converted signal is decoded in a decoder 7.

FIG. 2 shows the relationship between errors in each carrier and errors in the decoder input. Here, the case of 4 multi-carriers is taken as an example.

As mentioned above, in digital wireless communication, error rate degradation occurs simultaneously on each transmission path, and the probability is extremely small.

, 2 shows the case where only the second carrier 732 of the .t carriers is degraded by facing.

In the figure, the locations marked with an X indicate errors in each carrier i. There is no error in carrier 8))) 184 of No. 1.3.4. However, there is an error r in the 1-1 second carrier 8°
) Errors occur at a rate of 1/2, and continuous errors also occur.

Generally, in an error correction device, the higher the error rate, the smaller the coding gain. Further, it is difficult to correct continuous errors with Langum error correction, and if error correction is performed for each carrier in the figure, it is considered that no coding gain can be obtained for the second carrier 82.

On the other hand, the decoder manual input 9 in the PttJ2 diagram is an error when four carriers are parallel-to-serial converted. As shown in the figure, the error rate is 1 of the error rate of the second carrier 82.
/4 times it becomes 1/8, and there is no continuous error.

Therefore, the correction ability of the error correction Vcrf1 can be exerted and a sufficient coding gain can be expected.

FIG. 3 is a block diagram showing a second embodiment of the present invention, in which a four-dimensional (n=2) code is taken as an example.

In the figure, 10 is a multidimensional encoder, 11 is a mapping circuit, 12. ．． 122 is a modulator, 13, . 132 are a first carrier and a second carrier, respectively; 14. ．．
142 represents a decoder 511, and 15 represents a decoder.

The multidimensionally encoded signal outputs a set of n symbols. If two symbols are simultaneously erroneous at this time, the probability that the decoded signal will be erroneous increases. In contrast, in the present invention, since n symbols are transmitted using different carriers, the probability of simultaneous errors is low, and a sufficient error correction effect is expected.

FIG. 4 is a block diagram showing a third embodiment of the present invention, in which 16 is a first encoder, 17 is an IF sequence-to-parallel converter, 181 to 18, 1 is a second encoder, 1 !31~19n
is a modulator, 201-20° is a first carrier, n-th carrier, 21-214. is a demodulator, 22. ~22.
+ represents a second decoder, 23 represents a parallel-to-serial converter, and 24 represents a first decoder.

In this example, the sign of fISl and ! An error correction code based on a code combination of ¥S2 codes is used. Instead of conventional interleaving, the uncorrelation of each carrier is used to obtain the same result as interleaving.

In this embodiment, the same effects as in the first embodiment described above can be obtained.

FIG. 5 is a block diagram showing a fourth embodiment of the present invention.

In the figure, (a) shows the configuration of the transmitting side, (b) shows the configuration of the receiving side, 25 is an error correction encoder, 2
6 is a serial-parallel converter, 271-27.1 is an error detection encoder, 281-284. is a modulator, 291-29n is a demodulating IF4 unit, 3 (1, -30 is an error detection decoder, 31
32 is a first parallel-serial converter, 32 is a second parallel-serial converter, 33 is an error correction decoder, 34 is a delay circuit, and 35 is a selection circuit.

In this embodiment, if a 7-enong occurs on one of the multicarriers and an error occurs,
In order to prevent errors from propagating to the carriers in the pond as a result of error correction, an error detection circuit is provided for each carrier.

Detection of l"l<l can be performed using a simple circuit such as a parity check.

Furthermore, if a systematic code is used, the demodulated signal becomes the signal before error correction decoding as it is, and if there is no error, it matches the decoded signal.

Therefore, by not decoding the carrier for which the error detection circuit has determined t++ that there is no error and outputting the demodulated signal as it is, it is possible to prevent the propagation of the error in the carrier in which the 7-A song has occurred.

In the figure, the delay circuit 34 delays the decoded signal by the time necessary for the error correction decoder 33 in order to match the phase with the output of the error correction decoder 33. However, the delay time between the two differs by the amount of delay at the decoder.

Further, the parallel-to-serial converter 32 of fjS2 converts each error detection circuit output so that it becomes the same order as the decoder output.

FIG. 6 is a block diagram showing a fifth embodiment of the present invention.

In the figure, (,) indicates the configuration of the sending side, and (
b) shows the configuration of the receiving side.

Further, 36 is an error correction encoder, 37 is a serial-parallel converter, 38. ~38n is a modulator, 3939 is a demodulator, 40
41 is a Viterbi decoding circuit, 42 is a branch metric generator, 43 is an AC8, 44 is a bus memory, and 45 is a circuit for determining whether there are many errors in each carrier.

The Viterbi decoding circuit 41 in the figure calculates the probability of each symbol (hereinafter referred to as branch metric) from the received signal point for each time slot, and calculates this probability based on the probability of the past code word. , and selects the most probable codeword.

At this time, when the signal is divided into carriers and sent as in the present invention, the error rate differs for each carrier.

Therefore, the reliability of branchometry is also different. Therefore, in the branch metric generator 42, the branch metric is reduced because the signal of the carrier in which 7 anonyms are generated is considered to have low reliability. As a result, a highly reliable bus metric can be obtained as a whole, and a higher coding gain can be expected.

Examples of circuits that determine whether there are many errors for each carrier include a method using an error detection circuit, a method using the reception level of each carrier, and a method determined from past branch metric values.

〔Effect of the invention〕

As explained above, since the error correction method of the present invention utilizes the non-correlation between each carrier in a multi-carrier method, any one of the A signals may be degraded by the 7 A song, and a burst IZ (R) may occur. Errors in the signal input to the outer decoder are randomized when burst errors are generated by the inner decoder of the combination code.

As shown in Figure 2, K (K=2, 3 ・
...) Among the carriers, (K -1) carriers have 7 errors, and even if an error occurs with a probability of P in one carrier and many consecutive errors occur,
As a decoder input, the error rate is as low as 1/PK, and there are no continuous errors. Therefore, a sufficient error correction effect can be expected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
FIG. 3 is a block diagram showing the second embodiment of the present invention, and FIG. 4 is a prong diagram showing the third embodiment of the present invention. , FIG. 5 is a block diagram showing the fourth embodiment of the present invention, f: PJG diagram is a block diagram showing the fifth embodiment of the present invention, FIG. 7 is a diagram showing the principle of multicarrier communication, 8
FIG. 9 is a block diagram showing an example of the configuration of a conventional digital radio system, FIG. 9 is a diagram showing an example of the configuration of the transmitting side of a conventional multidimensional code, and FIG. 10 is a diagram showing an example of the Mampingtu method.
FIG. 11 is a block diagram showing a transmission system using the Ml combination code. 1...Encoder, 2...Serial-parallel converter, 3+-3n, 191 to 19o. 28, -28n, 38. ~38□ ...Modulator, 41~4. ,．． 20. ~2On ・・・・・・ 1st
carrier nth carrier, 55
+++141-142. 21. ~21n, 29'-2
9n 1391-39n ・""' 55I device, 6.
23.40 Parallel-to-serial converter, 7.
15...Decoder, 8, ~8. ...
...First career, fourth career, 9 ・
・・・・・・Decoder input, 10 ・・・・・・
Multidimensional encoder, 11... Mapping circuit, 12, ~122... Modulator,
131...tpJl carrier, 1
3.・・・・・・ Second career, 16
...... [1 encoder, 17.26.37 ・
...Serial-parallel converter, 181-18. ...
... second encoder, 22-22. , ・・
...Second decoder, 24...
- First decoder, 25, 36...
...Error correction encoder, 271-270...
...Error detection encoder, 30. ~30n
...Error detection decoder, 31 ...
...first parallel-to-serial converter, 32...
...Second parallel-to-serial converter, 33...
...Error correction decoder, 34 ...Delay circuit, 35 ...Selection circuit, 41 °
・Pa Viterbi decoding circuit, 42 ・・・・・・
Branchometric link generator, 43...
... AC3゜44 ...Pass memory,
45 ・・・・・・ Circuit for determining whether there are many errors for each carrier Diagram 3 Agent Patent attorney Takashi Honma 4th (a) (b) Diagram (a) (b) Graduation diagram Shireguru book Yaria multi-carrier map

Claims (1)

[Claims] 1. In a multicarrier communication system in which a transmission signal is divided into a plurality of carriers with a small frequency bandwidth and transmitted in digital wireless communication, a signal with a code rate of ∫_0 (bit/sec) is sent to the transmitting side. an error correction encoder that outputs an error correction encoder, a serial-parallel converter that converts the output of the encoder into n series of parallel signals each having a code rate ∫_0/n (bit/sec), and a serial-parallel converter that converts the n series of parallel signals. In addition to providing a means for dividing and transmitting to each carrier of a multicarrier communication system, a receiver for receiving signals of each carrier on the receiving side;
The n-series parallel signals are coded at a code rate ∫_0 (bit/se
An error correction system comprising: a parallel-to-serial converter for converting into the signal of c); and an error correction decoder for decoding the output signal of the converter. 2. In a multicarrier communication system in which a transmission signal is divided into multiple carriers with a small frequency bandwidth and transmitted in digital wireless communication, an error correction method that outputs a signal with a code rate of ∫_0 (bit/sec) to the transmitter side. an encoder, a serial-parallel converter that converts the output of the encoder into n series of parallel signals each having a coding rate ∫_0/n (bit/sec), and an n series that encodes each of the n series of parallel signals with an error code. and a means for dividing and transmitting the n-sequence output of the error detecting encoder into each carrier of a multicarrier communication system, and on the receiving side, receiving the signals of each of the carriers. a receiver to
An error detection decoder detects errors in the n series of parallel signals using parity bits generated by the error detection encoder; ), an error correction decoder that decodes the output signal of the converter, and an output of the error correction decoder and the output of the parallel to serial converter before being decoded as inputs. The output of the error detection decoder is used as a control signal, and the output of the error correction decoder is output for the signal of the carrier in which an error has been detected.For the signal of the carrier in which no error is detected, it is parallelized before being decoded. - An error correction method characterized by providing a circuit for outputting the output of a serial converter. 3. In a multicarrier communication system in which a transmission signal is divided into multiple carriers with a small frequency bandwidth and transmitted in digital wireless communication, the code rate ∫_0 (bit/
sec), a serial-parallel converter that converts the encoder output into n series of parallel signals each having a code rate ∫_0/n (bit/sec), and the above n series In addition to providing a means for dividing and transmitting the parallel signals of /sec)
A parallel-to-serial converter for converting into a signal of An error correction method characterized by comprising means for changing a branch metric of a Viterbi decoder depending on whether or not there are many errors.