JPH0256159A - Voice response device - Google Patents

Abstract

PURPOSE:To rapidly execute a voice response to a transmitter by little memory capacity by accessing one memory by time division at a period which human ears cannot hear and sending messages to plural receptions. CONSTITUTION:One common voice response memory 10 is provided for plural office lines 1-n. An address generating means 9 responds to a receiving signal from plural office line trunks 31-3n and accesses the above-mentioned memory 10. That is to say, when the plural office line trunks detect the receiving signal at the same time, the above-mentioned address generating means 9 accesses the memory 10 by time division at the period which human ears cannon hear. The read-out voice response messages are sent to the trunks in which there is the reception. Thus, the messages can be sent to the transmitter by the little memory without time lug.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a voice response device that sends messages to a plurality of lines, such as a private branch exchange.

2. Description of the Related Art A conventional voice response device of this type will be explained with reference to FIG. In FIG. 3, 41 is a telephone set, and 42 is a subscriber circuit. 43.44.45 is the central office trunk, 50
is a control unit which receives signals from the office line trunks 43 and 44 and controls a memory group to be described later. 51.52.53 is a memory that stores message data; 61.6
2.63 is an address generation circuit. The address generation circuits 61, 62, and 63 are operated by the memory 5 under the control of the control circuit 50.
1.52.53 to generate the address of the data to be read. 71 is a demultiplexing unit, each memory 51.52
．． 53 is converted into an audio signal. 8 is a time division switch, and the central office line trunk 43
．． A communication path between 44 and 45 is set under the control of the control unit 50.

The voice response device having such a configuration reads message data from the memory 51 when a call arrives on the central office line 1, and sends a voice message to the central office line 1, and when a call arrives on the central office line 2, the voice response device reads the message data from the memory 51 and sends a voice message to the central office line 1. 52, and sent a voice message to station M2.

Problems to be Solved by the Invention However, in this case, it is necessary to provide as many memories for storing message data as there are office lines connected to this voice response device, which makes the device expensive and also requires a memory for storing messages. The message data read from this is delayed by a multi-stage delay circuit, and multiple messages with different message start times are always prepared, starting from the time closest to the time when the call is received. Sometimes messages could be selected and sent, but in this case there was a time lag between the time the call was received and the time the message started, making it impossible to respond appropriately.

Means for Solving the Problem The present invention solves this problem in that the cycle required to access the memory is shorter than the read cycle required to read data to be transmitted as audio. Focusing on this, the transmission destination of the message read from the memory storing the message data is switched in a time-sharing manner so that each of the plurality of receiving means goes around at a predetermined cycle, and the message read from the memory storing the message data is sent. and an address generating means that receives signals from a plurality of receiving means and generates address data for accessing the memory in synchronization with the switching operation of the switching means. The message data read from the memory according to the address is sent to the line connected to the incoming call receiving means.

Effect With this configuration, there is only one memory that stores message data, and when a call is received, the message data is sent from the memory in a time-sharing manner for each receiving method, and the message is sent to each line without delay, allowing the caller to receive the message. Messages echo in my ears endlessly.

EXAMPLE Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

First, FIG. 1 is a block diagram showing the configuration of a voice response device that is an embodiment of the present invention. Here, 1 is a telephone equipped with a handset, and 2 is a subscriber circuit to which the telephone 1 is connected. 31 to 3n are office line trunks, and each office line trunk 3
1 to 3n are connected to the central office line. 4 is an n-bit shift register, which shifts the output signal one by one for each input of the clock signal. 5 is an oscillation circuit that generates a pulse signal at a predetermined period. 61 to 6n are AND gates, which open the gates and output signals from the shift register 4 when a call arrives at the central office line trunks 31 to 3n.

71 to 7n are counters that increment the count value by 1 each time the signals from the AND gates 61 to 6n are applied.゛Pa・1 Increment. Reference numeral 8 denotes a timing switch, which activates the counter 71 every time a signal from the oscillation circuit 5 comes to the clock terminal.
Select any one of ~7n and output the count value. Reference numeral 9 denotes an address pointer, which stores one data of one of the counters 71 to 7n outputted from the timing switch 8 as an address value. A memory 10 stores response messages as data in time series at each address, and outputs the data stored in an area corresponding to the address stored in the address pointer 9. Reference numeral 11 denotes a parallel/serial converter circuit that converts parallel data output from the memory 10 into serial data. A timing switch 12 sends the output data from the parallel-to-serial conversion circuit 11 to the subscriber circuit 2 and the office line trunks 31 to 3n every time the clock signal from the oscillation circuit 5 is applied.

The operation of the above configuration will be explained.

The oscillation circuit 5 always outputs a clock signal, and the shift register 4 receives this and shifts every time a signal of 0 output lights arrives. In this state, when there is an incoming call on the central office line trunk 31, the central office line trunk 31 issues a signal and opens the AND gate. Then, the counter 71 receives the output signal of the shift register 4 that has passed through the AND gate 61 as a clock signal, and starts counting. Other counter 7
2 to 7n are not counted because the AND gates 62 to 6n are closed. And timing switch 8
Each time a clock signal arrives from the oscillation circuit 5, one of the counters 71 to 7n is sequentially selected and the address pointer 9 is
Output to. Now, the output of the counter 71 passes sequentially counted up data, but other counters 72 to 7
The output of n remains O. The data of the counters 71 to 7n output from the timing switch 8 is stored in the address pointer 9 and becomes an address for accessing the memory 10, and audio data corresponding to the address stored in the address pointer 9 is output.

The audio data coming out from here is parallel to serial converter circuit 1
1 is converted into serial data.

The output from this parallel/serial conversion circuit is sent as audio to the office line trunk 31 at a predetermined timing by the timing switch 12.

To put it simply, when there is an incoming call on the central office line trunk 31,
A counter 71 generates an address in the memory 10, reads out the audio data, and sends it to the office line trunk 31.

Here, if there is an incoming call on the office line trunk 31 and while the message data is being sent, there is an incoming call on the office line trunk 32. When the office line trunk 321 receives the call, the AND gate 62 opens and the counter 72 starts counting from that time. The message is read out from the memory 10 using the count value of the counter 72 as an address and sent to the office line trunk 32 via the timing switch.

Here, explanation will be given with reference to the timing chart of FIG.

In FIG. 2, a) is a clock pulse signal generated by the transmitting circuit 5. In FIG. This clock pulse signal has a period of generating n pulses at 125/ILsec. Here, the periods determined by the clock pulses from the transmitting circuit 5 are defined as time slots TSI to TSn, as shown in b) of FIG. This time slot T S
, L to TSn are allocated to each office line trunk 31 to 3n, and the timing switches 8 and 12 operate to correspond to the time slots TSI to TSn. For example, C) in FIG. 2 is a time slot assigned to the office line trunk 31, d) is a time slot assigned to the office line trunk 32, and f) is a time slot assigned to the office line trunk 3n.

When there is an incoming call on the central office line trunk 31 at the beginning of this timing chart, messages are sent to the central office line connected to this at time slots A1, A2, and A3 in time slots C> in FIG.
, A4...

If an incoming call is received on the central office line trunk 33 on the way, messages A1, A2, A3, etc. are sent to the central office line connected to this in the time slot e) of FIG.

Here, messages A1 and A2 to be sent to the central office trunk
, A3... has free time between them, but this time is 1
25. To the ears of someone with Gsec level, this is a short time, and the caller hears A1, A2, A3, etc. as a continuous voice, so there is no problem.

Effects of the Invention The present invention accesses a single memory in a time-sharing manner at a frequency that is imperceptible to the human ear, and sends messages in response to multiple incoming calls. It is possible to realize a voice response device that can respond to messages with a small amount of memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a voice response device which is an embodiment of the present invention, FIG. 2 is a timing chart in an embodiment of the present invention, and FIG. 3 is a block diagram showing the configuration of a conventional voice response device. It is a block diagram. 31 to 3n... Office line trunks 71 to 7n... Counter 4... Shift register 8... Timing switch 9... Address pointer 12... Timing switch

Claims (1)

[Scope of Claims] A plurality of incoming call receiving means for generating a signal in response to an incoming call, a memory storing message data, and time-sharing switching so that each of the plurality of incoming call means makes a round at a predetermined cycle, the memory a switch means to which a message read from the message is to be sent; and in response to signals from the plurality of call receiving means, generating address data for accessing the memory in synchronization with the switch operation of the switch means; and access means for selecting the address data generated by the address generating means in synchronization with the switching operation of the switching means and accessing the memory according to the selected address, A voice response device characterized in that the message data read from the memory according to the address generated by the address generating means is sent to a line connected to the incoming call receiving means.