JP3497869B2 - Transmission data test circuit of tone generation circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission data test circuit of a tone generation circuit for testing the normality of tone transmission data transmitted by a tone generation circuit for generating various audible signals provided in an exchange.

Tones such as dial tone, busy tone, ringback tone, etc. are sent to the users of the originating side terminal and the receiving side terminal to an exchange such as a PBX, and the services of the current exchange are transmitted. The status (dial tone or ringback tone) and the status of the other party (busy) are reported. The tone generating circuit for generating such a tone signal is generated by reading digital signals (PCM signals) of various tones stored in the ROM in correspondence with each pattern. It is necessary to test whether the tone transmission data generated from this tone generation circuit is generated as designed in advance.

[0003]

2. Description of the Related Art FIG. 3 shows an example of a system configuration of a conventional exchange (PBX). In FIG. 3, 50 is a PBX, 51 is a local line interface, 52 is a network, 53 is a tone generating circuit, 54 is a central processing unit, 55 is a telephone interface, and 56 is an extension telephone.

When a call is made from the telephone set 56, the tone generation circuit 53 sends a dial tone selected from the tone generation circuit 53 to the telephone set 56 by the central processing unit 54 to notify that it is in a dialable state and dial. When the other extension number is sent by, the network 52 is switched under the control of the central processing unit 54 and the extension telephone (not shown) of the destination is captured.
Subsequently, a ringing tone is selected from the tone generation circuit 53 and sent to the telephone 56 on the calling side when a ringing signal is sent to the other party's telephone. Connected. Similarly, the tone generation circuit 53 also generates a corresponding tone in connection of outgoing and incoming calls through the station line interface 51. Also, when performing services such as interrupts, various tones with different frequencies and intermittent patterns are generated.

FIG. 4 shows a block diagram of a conventional tone generating circuit.

In FIG. 4, reference numeral 60 is a tone generating circuit, and 61 is a sampling frequency of the PCM code, 8K.
The counter clock of Hz (125 μs cycle) is counted,
Each count value of 1600 is assigned to one address a of the tone ROM.
Is a tone counter that occurs as. Reference numeral 62 is an interval counter which counts the counter clock generated at the 12.5 ms cycle which is the minimum timing for controlling the interval (intermittent) of tones, and generates the address b of the interval ROM by each count value of 240, 63 is the interval counter 62 The output of the address b and the time slot number (there are 16 numbers corresponding to TS0 to TS15) c, the interval of various tone signals corresponding to each time slot number (representing a pattern of signal generation and pause time). Interval ROM 6 for storing the address d in which the pattern (signal sequence) of (signal) is stored for 3 seconds, 6
4 is a tone R for generating tone transmission data by an address a generated from the tone counter 61 and an address d corresponding to an interval signal (each signal indicates one of eight blocks) generated from the interval ROM 63.
OM.

FIG. 5 is an explanatory diagram of the interval ROM.

Referring to FIG. Interval ROM 63 shown in
Is provided with a plurality of time slots (TS) corresponding to interval signals of various tones (silence, dial tone, ringback tone, trunk busy tone, call waiting tone, etc.). In this example, 16 time slots are provided. (TS0 to TS15) is used and TS
2 for each time slot from 0 to TS15
40 words of tone control data are stored. The address of the interval ROM 63 is designated by the time slot number c and the output of the interval counter 62,
The word (tone control data) of the interval ROM 63 stored at that address is read. Each word stored in the interval ROM 63 has 3 bits.

Eight kinds of data "00" represented by the 3 bits
0 "to" 111 "correspond to the B. The eight blocks shown in are displayed. For example, "000" represents Norton (silence), and "001" has frequencies of 350 (HZ) and 440.
(HZ) is combined to represent a signal with a level of −10.0 dBm (decibels), and “010” has a frequency of 440 (HZ).
It is a combination of 480 (HZ) and the level is -10.0dBm.

The interval (silence) time and the duration of a specific tone are displayed by these 3-bit signal sequences, and the sequence of address d (pattern signal) corresponding to the tone of each time slot number is output from the interval ROM. To be done.

The operation of the interval ROM 63 will be described. The interval ROM 63 operates in a frame structure, and one frame is TS0 to TS.
15 consists of 2 cycles (for 32 time slots), and the input of the time slot number c changes at 3.9 μsc for one time slot. Therefore, while the interval counter 62 makes one count at 12.5 ms, 10
0 frames occur. Therefore, each time slot occurs 200 times within 12.5 ms.

FIG. 6 is an explanatory diagram of the tone ROM.

The tone ROM 64 is divided into eight blocks corresponding to eight kinds of addresses d generated from the interval ROM 63 shown in FIG. 5, and each block has 16 blocks.
The tone data of 00 words is stored. The word in each block is designated by the address a of the tone counter 61, and the address sequentially changes at 125 μsc. On the other hand, from the interval ROM 63, the address d in which one time slot changes at 3.9 μsc is generated.
An address for one frame (32 time slots) is generated during the period when one address a of the tone counter 61 is generated, and tone transmission data e is sequentially output from the tone ROM 64, and the necessary tone data is controlled by the control of the exchange. Are selected and supplied to the lines in the network.

Since the tone data generated from the tone generating circuit as described above is always used in the control operation of the exchange, it is necessary to test whether the tone data is normally transmitted.

The conventional tone generator circuit is tested as follows.

When the circuit shown in FIG. 4 is a normal circuit with no error, the circuit to be tested 80 shown in FIG. 7 is simultaneously operated for testing by using this as a reference circuit. That is, the counter clock (8 KHz) for driving the tone counter 61 of FIG. 4 is input to the tone counter 81 of FIG. 7 through the connection path indicated by. In addition, FIG.
The counter clock (12.5 ms) for driving the interval counter 62 is input to the interval counter 82 of FIG. 7 through the connection path indicated by, and the two tone generating circuits are driven simultaneously. At this time, the tone ROM 6 of FIG.
Tone transmission data generated from No. 4 and the tone RO of FIG.
A comparison circuit (not shown) compares the tone transmission data generated from M84 to confirm whether they match.

[0017]

In the conventional tone transmission data testing method described above, tone data is assigned to each time slot, and it takes about 3 seconds to confirm one time slot. That is, the counter clock is 1
Frames TS0 to TS15 are repeatedly generated 100 times while changing in a cycle of 2.5 ms, but it is possible to completely match the frames of the interval ROMs of both the reference circuit of FIG. 4 and the circuit under test of FIG. Since it is difficult, it takes a test time of 3 seconds to output 240 words at a cycle of the counter clock of 12.5 ms for one time slot so that there is no problem even if the frames do not completely match. Therefore, it takes about 48 seconds to test all the time slots (16TS), and the test time is long.

It is an object of the present invention to provide a tone transmission data test circuit which can quickly test whether tone transmission data generated from the tone generation circuit is normal or not.

[0019]

FIG. 1 is a block diagram showing the principle of the present invention.

In FIG. 1, 4 is a tone generation circuit to be tested which is tested for normality, 5 is a standard tone generation circuit for generating standard tone data at a higher speed than during normal operation, and 6 is a tone generation circuit. It is a comparison unit that compares the output of the tone generation circuit 4 to be tested with the output of the standard tone generation circuit.

In the tone generating circuit 4, 4a and 4b are selectors for switching one of a normal operation clock and a test counter clock by a test signal, 4c is a tone counter, 4d is an interval counter, 4e is an interval ROM, and 4f is It is a tone ROM. The standard tone generation circuit 5 is a circuit guaranteed to send normal tone data. The internal 5a is a tone counter, 5b is an interval counter, 5c is an interval ROM, and 5d is a tone ROM.

The principle configuration of the present invention is that the tone generation circuit to be tested is driven at a speed higher than the speed during normal operation, and the tone transmission data and the tone generated from the standard tone generation circuit 5 operating at the same high speed. It is to compare with the transmitted data.

[0023]

In the configuration of FIG. 1, the test operation of the tone generating circuit 4 is executed after stopping the normal operation. When performing a test, a test signal instructing the test is supplied to the selection units 4a and 4b. As a result, the selector 4a switches the tone counter 4c from the normal counter clock a1 to the high-speed counter clock a2. Similarly, the selection unit 4b switches the interval counter 4d from the normal counter clock b1 to the high-speed counter clock b2.

On the other hand, in the standard tone generating circuit 5 for generating standard tone data, the selecting sections 4a, 4 are also provided.
The high-speed counter clock a2 is supplied to the tone counter 5a in synchronization with the test signal for b and the high-speed counter clock b2 is supplied to the interval counter 5b.
Is supplied. By synchronizing the operations of the two tone generation circuits 4 and 5, the tone counters 4c and 5a operate at high speed with the same high-speed counter clock a2. At the same time, the interval counters 4d and 5b also have a high speed counter clock b of a speed corresponding to the high speed counter clock a2.
2. High speed operation. However, the interval counter 4
The time slot number supplied to d is fixed by the time slot number because the interval counter 4d has a high speed.

Tone counter 4c, interval ROM
The tone data read from the tone ROM 4f by 4e is supplied to the comparison unit 6 and compared with the tone data generated from the tone ROM 5d of the standard tone generation circuit 5 to check whether the data match or not. .

This test is performed by sequentially changing the time slot numbers supplied to the interval counter 4d of the tone generating circuit 4 and is executed for all time slots (the time slot number of the interval counter 5b of the standard tone generating circuit 5 is Fixed).

[0027]

FIG. 2 is a block diagram of an embodiment. This embodiment corresponds to the principle configuration of the present invention shown in FIG. However, FIG. 2 shows only the configuration of the tone generation circuit under test (corresponding to 4 in FIG. 1), and the standard tone generation circuit (see FIG. 1).
5) and the comparison section (6 in FIG. 1) are the same as the configuration shown in FIG.

In FIG. 2, reference numerals 30 and 31 designate a selection unit, and 32.
Is a tone counter that generates 1600 words (each word represents a part of the address of the tone ROM), and 33 is 24
An interval counter for generating 0 words (each word represents a part of the address of the interval ROM), and 34 for each time slot number (4 bits represent a number from 0 to 15) by the address of the interval counter 33. Interval ROM that stores 240 3-bit signal patterns (signal generation and pause patterns),
Reference numeral 35 is a tone ROM that generates 1600 tone data for each of the eight types of signals generated from the interval ROM 34.

In a normal operation state, a control signal "0" is supplied from a central processing unit (not shown) to the selection units 30 and 31 of the tone generation circuit of FIG.
31 selects the input indicated by "0". That is, the selection unit 30 selects the counter clock of 8 KHz (indicated by a) for performing the normal operation to select the tone counter 3
2 and the selection unit 31 selects the counter clock of 12.5 ms (indicated by d) to select the interval counter 33.
Supply to.

When conducting a test, a central processing unit (not shown) selects "1" as the control signals c and f,
31 is supplied. At this time, the selection unit 30 selects the test high-speed clock shown in b. This test high-speed clock is
For example, a clock of 256 KHz, which is 32 times the speed of a normal counter clock (8 KHz), is used. Also,
The selection unit 31 selects the test high-speed clock indicated by e and supplies it to the interval counter 33. This test high-speed clock e also uses a clock of 390 μs, which is 32 times as fast as 12.5 ms of the normal operation, for example.

When the tone generating circuit operates at high speed, the time slot number indicated by g also increases in speed, which makes it difficult to change the time slot number at high speed during the test operation. Therefore, the number is fixed at each test. Set and change the time slot number in order to perform the test.

The test is performed according to the same principle as described with reference to FIG. 1 above. The tone generation circuit to be tested in FIG. 2 is operated by the high speed clock by the control signal to the selection units 30 and 31, and the tone ROM 35 is operated. The tone transmission data of (1) and the tone transmission data of the standard tone generating circuit (5 of FIG. 1) which operates at high speed are compared by the comparison section (6 of FIG. 1).

In this case, the tone ROM 35 has a higher speed than the normal operation, and if a 32 times counter clock is used as the high-speed clock for testing b and e shown in the figure, it is 1
Regarding the time slot, the test time that required 3 seconds in the conventional example can be shortened to 3/32 seconds (about 0.1 second).

[0034]

According to the structure of the present invention, the test time of the tone transmission data from the tone generating circuit can be greatly shortened and the test efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment.

FIG. 3 is a system configuration example of a conventional exchange (PBX).

FIG. 4 is a configuration diagram of a conventional tone generation circuit.

FIG. 5 is an explanatory diagram of an interval ROM.

FIG. 6 is an explanatory diagram of a tone ROM.

FIG. 7 is a configuration diagram of a tone generation circuit to be tested.

[Explanation of symbols]

4 tone generation circuit 4a selection section 4b selection section 4c tone counter 4d interval counter 4e Interval ROM 4f tone ROM 5 Standard tone generator 5a tone counter 5b Interval counter 5c Interval ROM 5d tone ROM 6 comparison section

Front page continuation (72) Inventor Hiroshi Toshioka 1-21-1 Akebono-cho, Tachikawa-shi, Tokyo Inside Fujitsu ACE Co., Ltd. (56) References JP-A-64-49358 (JP, A) JP-A-62- 257556 (JP, A) JP-B 64-4627 (JP, B1) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04M 3/02-3/14 H04M 3/22-3/36 H04M 19/00-19/08 H04Q 1/20-1/26

Claims (2)

(57) [Claims] 1. A tone ROM which stores tone data corresponding to a plurality of types of tones, and a tone counter which generates addresses of a plurality of tone data in the tone ROM.
Interval ROM and interval RO for generating generation patterns including tone type addresses in the tone ROM
In the transmission data test circuit of the tone generating circuit in the exchange having the interval counter for driving M, the tone counter and the interface of the tone generating circuit to be tested are
The cows supplied for normal operation to the respective global counters.
Input clock that is faster than the counter clock.
Steps are provided, and standard tone data is generated at a higher speed than during normal operation
A standard tone generation circuit is provided, and the tone counter of the tone generation circuit to be tested is tested during testing.
High-speed counters for data and interval counters
Supply standard clock and drive standard tone generation circuit
The tone generation circuit and standard tone generation circuit to be tested
A transmission data test circuit for a tone generation circuit, comprising a comparison unit for comparing the outputs of the above . 2. A tone counter and an image counter of a tone generation circuit to be tested according to claim 1.
The counter clock input section of the
Control signal for normal operation and test signal
Includes a selection unit that selects one of the high-speed counter clocks
Sending the data test circuit of the tone generating circuit, characterized in that.