JPH0256133A - Line switching system - Google Patents

Abstract

PURPOSE:To switch an active line or transmission line into a standby line or transmission line by switching the active line or transmission line into the standby line or transmission line at delimiters of consecutive idle cells without momentary interruption so as to prevent missing of information. CONSTITUTION:A real cell arrival interval detection circuit 23 of a sender side equipment 1 always detects the real cell arrival interval in a line or a transmission line being an object of switching and sends a switching control signal 25 of the line or the transmission line to a changeover switch 24 when the real cell does not arrive for a time over a transmission delay difference between the active line or transmission line and the standby line or transmission line at the switching section of the line or transmission line. The changeover switch 24 uses a switching control signal 25 to switch the line or transmission line from the active to the standby line or transmission line at the delimiter of the cell. An idle cell detection circuit 29 of the receiver side equipment 12 separates the idle cell in the line or transmission line and sends only the real cell to an OR circuit 30.

Description

[Detailed description of the invention] [Industrial application field] The present invention is utilized for time division multiplexed digital transmission.

The present invention relates to a line switching system for switching a working line or transmission line for transmitting information strings in units of cells to a protection line or transmission line in time division multiplexing digital transmission. Line or transmission line switching refers to switching and switching back transmission lines in the event of node or transmission line failures, relocating and switching back transmission lines due to node expansion or transmission line construction, load balancing on transmission lines, or installation of new lines. This is necessary for line accommodation replacement, etc.

[Conventional technology]

11 and 12 are block diagrams showing an example of a conventional digital transmission device, with FIG. 11 showing the case of transmission line switching and FIG. 12 showing the case of line switching.

First, FIG. 11 will be explained. 1 is a transmitting side device, 2 is a cross-connect switch that switches time slots, 3 is a multiplexing conversion device (MUX), 4 and 14 are transmission line changeover switches, and 5 and 15 are transmission line changeover switches 4 and 140 control circuits, respectively. , 6 is an interface circuit (INF) for electrical-optical conversion, etc., 7a, 7b, and 7
d is a working transmission line, 8 is a protection transmission line, 9 and 10 are data links, 11 is a center attachment that sends control signals to control circuits 5 and 15, 12 is a receiving side device, 13 is an optical-to-electrical conversion and bit synchronization interface circuit (INF) such as
and 16 is a demultiplexer (D-MUX).

In the transmitting side device 1, the multiplexing conversion device 3 multiplexes the digital information string from the cross-connect switch 2,
It is sent to the working transmission lines 7a, 7b and 7d via the transmission line changeover switch 4 and the interface circuit 6.

In the receiving side device 12, is the current transmission line? a, 7b and 7d
The signal is received by the interface circuit 13 and supplied to the demultiplexer 16 via the transmission path changeover switch 14.

The demultiplexer 16 separates the multiplexed information string,
It is sent to cross-connect switch 2.

Current transmission line? If the line or transmission equipment breaks down in a, 7b, or 7d, if it is necessary to stop operation for maintenance, or if you want to switch back after repairing the faulty part, the data link The working transmission line is switched to the protection transmission line 8 by the transmission line changeover switches 4 and 14 via 9 and 1O and the control circuits 5 and 15. The figure shows switching from the working transmission line 7d to the backup transmission line 8.

Next, FIG. 12 will be explained. 17 is a control circuit for the cross-connect switch 2 of the sending device 1; 18 and 19;
1 is a relay device, 20 and 21 are data links, 22 is a control circuit for the cross-connect switch 2 of the receiving device 12, and the other circuits are the same as those shown in FIG.

In the transmitting device 1, the signal from the current transmission line 7 is received by the interface circuit 13, and the signal is multiplexed and separated! 16.

The demultiplexer 16 separates the multiplexed information string,
The signal is sent to the cross-connect switch 2 as a highway signal time-slot multiplexed within a frame. The cross-connect switch 2 fixedly connects to the multiplexing converter 3 corresponding to the working transmission line 7 of the outgoing route in units of one time slot or multiple time slots (corresponding to a line) according to the time slot position in the frame. do.

The connection destination of the line can be changed under the control of the control circuit 17. The multiplex conversion device 3 multiplexes the highway signal from the cross-connect switch 2 and sends it to the current transmission line 7 via the interface circuit 6. The receiving device 12 and the relay devices 18 and 19 have the same configuration as the transmitting device 1.

When it is necessary to stop the operation of the current transmission line for maintenance, or when the fault is repaired and then switched back on,
When it is necessary to change the capacity of a line to distribute the load on a transmission line or install a new line, it is necessary to switch the working line to a protection line.

The figure shows switching from a working line passing through working transmission lines 7e-7f-7g-7h to a protection line passing through working transmission lines 7e-7i-7j-7h. In this case, line switching is performed by first switching the data link 20 according to an instruction from the center device 11.
A control signal is sent to the relay device 19 via the working transmission line 7.
1 and the empty line in the working transmission line 7. Next, according to an instruction from the center device 11, a control signal is sent to the control circuits 17 and 22 via the data links 9 and 10, and the control circuits 17 and 22 change the path in the cross-connect switch 2 from ■ to ■. The working transmission line 7 set above
Connect to the empty line between 1 and 7J.

[Problems to be Solved by the Invention] However, in the transmission line switching system described in FIG. 11, switching from the working transmission line 7d to the protection transmission line 8 is performed regardless of the main signal. Therefore, even if the sending device 1 performs parallel transmission on the working and protection transmission lines at the time of switching, the delay difference between the working transmission line 7d and the protection transmission line 8 cannot be absorbed, and the switching At times, momentary interruptions occurred, and synchronization was lost due to main signal loss, duplication, etc., making it impossible to maintain normal transmission conditions. In particular, in high-speed optical fiber communication equipment, there is a propagation time difference greater than the frame length or cell length between the working transmission line and the protection transmission line, and frames or cells may be dropped or duplicated when switching between the working and protection transmission lines. there is a possibility. This essentially results in a momentary interruption of the transmission path. For example, in a backbone transmission line with a speed of several hundred Mb/s or more, even a very short momentary interruption when switching the transmission line has a major effect on all equipment and terminals in the downstream group, resulting in deterioration of transmission quality. was there.

Furthermore, in the line switching system explained in FIG. 12, switching from the working line to the protection line is performed regardless of the main signal. Therefore, even if the sending device 1 performs parallel transmission between the working line and the protection line at the time of switching, it is not possible to absorb the delay difference between the working line and the protection line, resulting in momentary interruptions at the time of switching. However, there was a drawback that the main signal may be omitted or overlapped. In this case, frame synchronization patterns are inserted and removed by the multiplex converter 3 and the demultiplexer 16, so line switching does not cause synchronization loss on the transmission path. This has the drawback of deteriorating transmission quality due to synchronization loss.

SUMMARY OF THE INVENTION An object of the present invention is to provide a line switching system that eliminates the instantaneous interruptions caused by switching and that can always maintain a normal transmission state by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The present invention provides a line switching system that includes a transmitting side device and a receiving side device including a switching means for switching a working line or transmission line that transmits an information string in units of cells to a backup line or transmission line. The transmitting device includes at least:
Actual cell arrival interval detection that detects the actual cell arrival interval in the working line or transmission line is detected, and in a predetermined line switching section, the transmission delay of the working line or transmission line is the same as the transmission delay of the protection line or transmission line. If the delay is large, switching is performed at an arbitrary cell break, and if the transmission delay is smaller on the protection line or transmission line than on the working line or transmission line, the actual cell arrival interval detection is lost and switching is performed on the working line or transmission. and a line switching control means for switching at a cell break when the arrival of an actual cell is not detected for a time corresponding to the delay difference between the line and the backup line or the transmission line, and the transmitting side device or the receiving side device at least The present invention is characterized in that it includes real cell multiplexing means for multiplexing real cells among the cells transmitted by the working line or transmission line and the protection line or transmission line into one line.

[Effect]

The real cell arrival interval detection method always detects the real cell arrival interval within the currently used line or transmission path.

The line switching control means performs predetermined line switching control in response to the magnitude relationship between the transmission delay of the working line or transmission line and the transmission delay of the backup line or transmission line in a predetermined line switching section. In other words, if the delay for protection is larger than that for working, switching is made at an arbitrary cell break, and if the delay for protection is smaller than that for working, the actual cell arrival interval is detected manually and the delay difference between working and protection is exceeded. When the arrival of a real cell is not detected for a corresponding period of time, control is performed to switch between cells.

The real cell multiplexing means multiplexes only real cells among the cells transmitted on the working and protection lines or transmission lines into one line and transmits the multiplexed cells.

Therefore, if empty cells that appear on a line or transmission path are used to switch from active to backup, if cells overlap, switching can be performed using the continuous empty cells that correspond to the number of cells. It becomes possible to switch lines or transmission paths in the event of a momentary interruption.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, and shows the basic configuration of the present invention. FIG. 2 is an explanatory diagram showing the format of an information string (cell) on a transmission path. Figures 3 and 4 are explanatory diagrams showing the cell position relationship at the time of switching. This shows a case where the transmission delay of the backup line (transmission line) is smaller than that of the line (transmission line).

According to FIG. 1, the present embodiment includes a changeover switch 24 as a switching means for switching a working line or transmission line 26 for transmitting an information string in units of cells to a protection line or transmission line 27. Sending side device 1 and receiving side device 12
In the line switching system, the transmitting side device 1 includes a real cell arrival interval detection circuit as a real cell arrival interval detection circuit that detects the real cell arrival interval of the input information sequence a in the current line or transmission path. 23, in a predetermined line switching section, if the transmission delay of the working line or transmission line is greater than the transmission delay of the protection line or transmission line, switching is performed at an arbitrary cell break, and the transmission delay is changed to the working line or transmission line. If the protection line or transmission line is smaller than the actual cell arrival interval detection, the actual cell arrival interval is When the arrival is not detected, the receiving device 12 includes a switching control signal 25 as a line switching control means for switching at cell divisions, and the receiving side device 12 can switch between the lines transmitted by the working line or transmission line and the protection line or transmission line. A real cell multiplexing conversion circuit (actual cell M
UX) Contains 28.

The actual cell multiplexing conversion circuit 28 includes empty cell detection circuits 29 connected to the working line (transmission line) 26 and the protection line (transmission line) 27, respectively, and the outputs of these two empty cell detection circuits 29 ( The OR circuit 30 performs the logical OR of the real cells) and outputs an output information string.

A feature of the present invention is that, in FIG. 1, a real cell arrival interval detection circuit 23 that outputs a switching control signal 25 and a real cell multiplexing conversion circuit 28 are provided.

Next, the operation of this embodiment will be explained with reference to FIGS. 2, 3, and 4.

The actual cell arrival interval detection circuit 23 of the sending device 1 constantly detects the actual cell arrival interval within the line or transmission line to be switched, and distinguishes between the current line or transmission line in the switching section of the line or transmission line. When a real cell does not arrive for a time longer than the transmission delay difference with the backup line or transmission line, a line or transmission line switching control signal 25 is sent to the changeover switch 24. The changeover switch 24 uses a changeover control signal 25 to change over the line or transmission line from the current use to the standby use at cell divisions.

The empty cell detection circuit 29 of the receiving device 12 separates empty cells in the line or transmission path, and sends only real cells to the OR circuit 30.
Send to. In this switching system, real cells do not arrive from the working line or transmission line and the protection line or transmission line at the same time, so no speed conversion is required on the empty cell detection line 29. The OR circuit 30 calculates the logical sum of the real cells that are sent, and in the case of transmission line switching, one is required for the current and backup use, and in the case of circuit switching, one is required for each output route.

Therefore, in the case of line switching, one OR circuit can be shared by multiple lines if the output routes are the same.

Next, FIG. 2 will be explained. In Figure 2, VCl
, 5VCI, and VCI3 are call identifiers (hereinafter referred to as VCI) assigned to each call indicating a destination, and VPIo and VP I are route identifiers assigned to each line indicating a transmission route (hereinafter referred to as VPr). , H is the header, ■ is the main information, E is an empty cell identification bit string for identifying empty cells, and empty is an unused bit string, and the format of the information string is composed of real cells and empty cells. . Different subscripts in VCI or VPI indicate different calls or lines. The flow of cells given the same VPI becomes a line.

VPI allows a relay device to handle multiple calls in a uniform manner by assigning the same value to multiple calls transmitted to the same destination. Same-VPI
The transmission speed of the line can be arbitrarily selected depending on the number of calls to be assigned.

The same VCI is assigned to the main information of the same call from the call origination to the end of the call. Therefore, the flow of cells assigned the same VCI can also be viewed as one line. Furthermore, since the transmission line is treated as one line or multiple lines in a unified manner, it can also be seen as one line.

A line configured by VCI or VPI is not a physical line that always exists on a transmission path, but a logical line that exists only when a call occurs.

Therefore, in the middle m device, only when a cell arrives, sends it to the intended outgoing route according to the VCI or VPI in the header of each cell. For this reason, each relay device has VCI
Alternatively, each VPM has a table in which exit route numbers are written.

Next, FIG. 3 will be explained. FIG. 3 shows the input information string a of the transmitting side device l in FIG. This shows the Figure 3 shows that in the case of a line, the actual cells constituting the line to be switched are extracted from a transmission line in which many lines are multiplexed, and are operated at a clock speed corresponding to the maximum transmission speed of that line. This diagram assumes a state in which cells are lined up on a multiplexed highway; in reality, processing of cells configuring a line is performed in a time-division manner on a multiplexed highway. A to 0 indicate real cells in the line or transmission path to be switched,
Empty indicates no signal.

In the case of FIG. 3, since the transmission delay of the backup line or transmission line is larger than that of the current line or transmission line, it is possible to switch at any cell break on the transmitting side, and by switching, the OR circuit of the receiving side device 12 At 30, the information string from the working line or transmission path and the information string from the protection line or transmission path do not collide. Therefore, due to switching, there is no dropout, duplication, or order reversal of real cells, and normal information transmission is performed.

Next, FIG. 4 will be explained. Figure 4 is similar to Figure 3,
The input information sequence a on the transmitting side of FIG. 1 and the output information sequence after multiplexing on the receiving side are shown. In the case of FIG. 4, since the transmission delay of the protection line or transmission line is smaller than that of the working line or transmission line, the actual cell arrival interval detection circuit 23 of the sending device 1 detects the transmission delay time difference between the working line or the protection line. When a real cell does not arrive for the time corresponding to the above, that is, when an empty cell continues, it is necessary to switch from the active cell to the backup cell. As a result, in the OR circuit 30 of the receiving device 12,
The information string from the working line or transmission path and the information string from the protection line or transmission path never collide. Therefore, there is no dropout, duplication, or order reversal of real cells due to switching, and normal information transmission is performed.

The switching principle explained above also holds true when the cell multiplexing circuit 28 for only real cells is provided in the transmitting device.

In addition, the cell configuration to which the switching principle explained above can be applied is as follows:
Not only fixed length cells but also variable length cells may be used.

The switching principle of the present invention has been described above, but in order to make it possible, continuous empty cells must exist in the information string of the line or transmission path. Therefore, Tables 1 and 2 show the time intervals at which continuous empty cells occur, assuming that the probability of occurrence of real cells containing main information applied to a transmission path or line follows a Poisson distribution. Table 1 shows the average actual cell occupancy rate of 0.2. This shows the interval at which consecutive empty cells occur. Table 2 shows that in the case of a fixed length cell with a maximum transmission speed of 1.5 Mb/s and a cell code length of 500 bits, the average line usage rate for the maximum transmission speed of the line is 0.2.0.5.0. 8 shows the average continuous empty cell generation interval in the case of 8.

As mentioned above, a line is configured with real cells only when a call occurs, so empty cells are not included, but the continuous empty cells shown in this table constitute the line to be switched from the transmission path. This figure shows the continuous empty cells that would appear on the highway, assuming that real cells were extracted and lined up on a highway operating at a clock speed corresponding to the maximum transmission speed of the line.

Tables 1 and 2 also show the difference in transmission path length between the active and backup transmission paths or lines that allows switching of the transmission path or line corresponding to the number n of consecutive empty cells. In the case of line switching, the occupancy time on the transmission line of the real cells constituting the line differs depending on the transmission speed of the multiplexed transmission line, so the switchable transmission line length difference also differs.

Table 2 shows the cases where the maximum transmission speed of the line and the transmission speed of the transmission line are equal, and when the line is 6 Mb/s or 100 Mb/s.
The figure shows the case of multiplexing on a transmission line with a transmission speed of .

In addition, in Tables 1 and 2, the transmission path delay time is 5
ns/m is used. From these tables, it can be seen that the smaller the average actual cell occupancy rate of the transmission path or the average usage rate of the line, and the lower the transmission speed of the transmission path or the maximum transmission speed of the line, the wider the applicable range of the line switching method of the present invention becomes. I can understand that. Alternatively, in the case of line switching, it can be understood that the higher the transmission speed of the multiplexed transmission line is relative to the maximum transmission speed of the line to be switched, the wider the applicable range becomes.

(Hereinafter, this page margin) Table 1 Average continuous empty cell generation interval (in the case of transmission line switching) Next, an actual embodiment based on the switching principle of the present invention explained in FIGS. 1 to 4 will be described.

FIG. 5 is a block diagram showing a second embodiment of the present invention.
A case is shown in which the above principle is applied to transmission path switching between nodes.

In FIG. 5, 31 is a cross-connect switch that switches on a cell-by-cell basis, 32 is a continuous empty cell number detection circuit,
33 is a cell synchronization button insertion circuit, 34 is an empty cell generation circuit, 35 is a station clock, 36 is a station cell phase pulse, 3
7 is a station clock source, 38 is a transmission line changeover switch, 39 is a control circuit, 40 is a continuous empty cell number designation signal or continuous empty cell number detection signal, 41 is a switching control signal for the transmission line changeover switch 38, 42 is data Link transmission/reception circuit, 43 and 44 data link, 45 center device, 46 regenerated clock, 60 cell synchronization circuit, 47 cell phase pulse,
48 is a write clock, 49 is a FIFO memory (first-in-first-out memory), 50 is an empty signal, 51 is a read clock, 52 is an AND circuit, 53 is an AND circuit 520 control signal, 54 is a clock control circuit,
55 is a control signal for the clock control circuit 54, 56 is a control circuit, 57 is a write clock, and 58 is a real cell multiplexing converter (
(actual cell MUX section) and 59 is a switch section of the cross-connect switch 31, and the other circuits are the same as those used in FIG.

The features of the present invention are, as shown in FIG. 5, a continuous empty cell number detection circuit 32 for detecting the actual cell arrival interval and a control circuit 3 for outputting a switching control signal 41 as a line switching control means.
9, an OR circuit 30, an AND circuit 52, a clock control circuit 54, and a control circuit 56 as real cell multiplexing means.

Next, the operation of the second embodiment will be explained.

In the configuration shown in FIG. 5, switching from any working transmission line to the protection transmission line and switching back can be performed without momentary interruption; however, here, switching from the working transmission line 7d to the protection transmission line 8 Switching will be explained.

The continuous empty cell number detection circuit 32 of the transmitting device 1 counts the number of continuous empty cells in the information string output from the cross-connect switch 31, and the value is set by the continuous empty cell number designation signal 40 from the control circuit 39. When the number of cells reaches the specified number, it is sent to the control circuit 39 as a continuous empty cell number detection signal 40. The control circuit 39 receives a transmission line switching signal sent from the center device 45 via the data link 43 and the data link transmitting/receiving circuit 42, and when the transmission delay of the protection transmission line 8 is smaller than that of the working transmission line 7d to be switched, , continuous empty cell number designation signal 4 corresponding to the transmission delay time difference of the image transmission path or more
0 to the continuous empty cell number detection circuit 32 corresponding to the current transmission line 7d to be switched, and immediately after receiving the continuous empty cell number detection signal 40 from the empty cell number detection circuit 32, control is sent to the transmission line changeover switch 38. Send signal 41.

On the other hand, when the transmission delay of the backup transmission line 8 is larger than that of the current transmission line 7d to be switched, the control signal 41 is directly sent to the transmission line changeover switch 38. After sending the control signal 41 to the transmission line changeover switch 38, the control signal 41 is sent to the center device 45 via the data link transmitting/receiving circuit 42 and the data link 43.
Sends a switching completion signal to

The empty cell generation circuit 34 always outputs empty cells. The cell synchronization pattern insertion circuit 33 inserts a cell synchronization pattern into the empty cells output from the continuous empty cell number detection circuit 32. If an empty cell does not arrive even after a certain number of cells has been exceeded, the arriving real cell is delayed by one cell, and a cell into which a cell synchronization pattern has been inserted is inserted. The delay is removed by removing empty cells as they arrive.

Therefore, when continuous empty cells necessary for transmission line switching have arrived, there is no delay in the cell synchronization button insertion circuit 33, so the control circuit 39 knows the control timing of the transmission line changeover switch 38. The transmission line changeover switch 38 quickly switches the working transmission line 7d to the backup transmission line 8 at cell separation based on the control signal 41. The interface circuit 6 performs electrical-to-optical conversion on the input signal and sends it to the optical transmission line.

The interface circuit 13 of the receiving device 12 performs optical-to-electrical conversion on the received signal, performs bit synchronization, reproduces a recovered clock 46, and outputs the optical-to-electrical converted information string. The cell synchronization circuit 60 performs recell synchronization using the reproduced clock 46 and the cell synchronization pattern in the information string, and outputs a cell phase pulse 47.

The empty cell detection circuit 29 detects empty cells in the information string using the reproduced clock 46 and the cell phase pulse 47, and outputs a write clock 48 so that only real cells are written to the FIFO memory 49. In this empty cell detection circuit 29, since the bit string for identifying an empty cell and the cell synchronization pattern are the same bit string, the cell containing the cell synchronization pattern is determined to be an empty cell.

The actual cells written in the FIFO memory 49 are read out by the read clock 51 from the clock control circuit 54. When there is no real cell in the FIFO memory 49, an empty signal 5G is sent to the clock control circuit 54.

Since the FIFO memory 49 can operate the write clock and successive clock independently, the FIFO memory 49 allows the clock and cell phase of the information string received from each transmission path to match the phase of the local clock source 37. can.

The clock control circuit 54 normally controls the FI of the corresponding transmission line.
When the empty signal 50 does not come from the FO memory 49,
A successive clock 51 synchronized with the station clock 35 and cell phase pulse 36 of the station clock source 37 is transferred to a corresponding FIFO.
The information string read out from the FIFO memory 49 is sent to the memory 49 using the same write clock 57 as the successive clock 51.
As a result, the data is written to the FIFO memory 49 in the cross-connect switch 31. Further, after the control signal 55 for switching the transmission path is received from the control circuit 56, the clock control circuit 54 inputs an empty signal 50 in the FIFO memory 49 of the active transmission path corresponding to the FIFO memory 49 of the backup transmission path 8.
The successive clock 51 is sent to the FFO memory 49 that is not outputting the same write clock 5.
Outputs 7. When switching transmission lines, the active and backup FIs
Since real cells are not written to the FO memory 49 at the same time, an empty signal 50 is always output from at least one FIFO memory 49.

After switching back from the backup transmission line 8 to the working transmission line 7, the clock control circuit 54 returns to the normal state in response to the control signal 55 from the control circuit 56. Since the OR circuit 30 controls the read clocks of the FIFO memories 49 of the working and protection transmission lines, only one of the received information strings from the working and protection transmission lines passes through. Control circuit 56
Normally, all the AND circuits 5 are controlled by the control signal 53.
2 is turned off, and the control signal 55 is not output to the clock control circuit 54.

When a transmission line switching request is received from the center device 45 via the data link 44 and the data link transmitting/receiving circuit 42, the two AND circuits 52 corresponding to the current transmission line to be switched are kept in the on state, and the switching is performed. A transmission line switching control signal 55 is sent to the clock control circuit 54 corresponding to the target working transmission line. The two AND circuits 52 are kept in the ON state until switching back from the backup transmission line 8 to the working transmission line is completed.

Next, a procedure for switching from the working transmission line 7d to the protection transmission line 8 will be explained. First, in response to an instruction from the center device 45, the control circuit 56 turns on the two AND circuits 52 corresponding to the working transmission line 7d, and also instructs the clock control circuit 54 corresponding to the working transmission line 7d to A switching control signal 55 is sent.

Thereafter, a transmission line switching preparation completion signal is sent to the center device 45.

After receiving the transmission line switching preparation completion signal, the center device 45 sends a transmission line switching signal to the control circuit 39 on the transmission side. As described above, the control circuit 39 controls the transmission line changeover switch 38 to switch the transmission line from path (2) to path (2) at high speed.

Thereafter, a transmission line switching completion signal is sent to the center device 45, and the transmission line switching is completed. When switching back the transmission line, the receiving side device 12 is kept in the previous state, and the transmitting side device 1 switches from path ■ to path ■ using the transmission path changeover switch 38 in the same way as when switching the transmission path. Thereafter, in the receiving side device 12, the two AND circuits 52 are turned off, and the tarlock control circuit 54 corresponding to the working transmission line 7d is returned to the normal state, thereby completing the switchback.

Since it operates as explained above, no instantaneous interruption occurs due to transmission line switching or switching back.

In addition, in the configuration of FIG. 5, since the FIFO memory 49 is used in the real cell multiplexing converter 58 of the receiving side device 12, it can also operate in an asynchronous network. In addition, in FIG. 5, a cell synchronization button is inserted into an empty cell on the transmitting side, and cell synchronization is performed using the cell synchronization button on the receiving side.
It is also possible to insert a frame stamp into the information string, form a frame for several cells, and send it to the transmission path.On the receiving side, frame synchronization is performed using the frame stamp, and cell synchronization can also be achieved from the bit position within the frame. It is possible.

FIG. 6 is a block diagram showing a third embodiment of the present invention.
A case is shown in which the above principle is applied to line switching between nodes. In FIG. 6, 61a, 61b and 61C are designated VPI cell arrival interval detection circuits, 62a, 62b and 62G are designated VPI cell arrival interval designation signals or designated VPI cell arrival interval detection signals, and 63a, 63b and 639 are designated VPI cell arrival interval detection circuits. Header decoding tagging circuit, 66a, 66b and 66c are tag '7 memory (tag MAP) for each VPI, 64a, 64b and 64C are tag map memo for each VPI! Read signals or memory output signals of J66a, 66b and 66C, 65 is a control circuit, 6
Memory rewrite signals for tag map memories 66a, 66b and 66C for each 7a, 67b and 67C1tVPI,
68 is a cross-connect switch that performs switching on a cell-by-cell basis; 69a, 69b, and 69C are tag removal circuits; 7
0 and 71 are data links, 72 is a control circuit, 73a
, 73b and 73c are tag map memories (tag MAP) for each VPI, 74a, 74b and 74c are memory rewrite signals for tag 77p memories 73a173b and 73c, and 75 is an interface circuit for optical-electrical conversion, bit synchronization, cell synchronization, etc. INF), 76 is an interface circuit (INF) for cell synchronization button insertion, electrical-to-optical conversion, etc., and the other circuits are the same as those used in the previous figure.

The feature of the present invention is that the cell arrival interval detection circuits 61a, 61b and 6 of the specified VPI as actual cell arrival interval detection failure
1C, header decoding tagging circuits 53a, 63b and 63c operating as line switching control means, and VPI
Tag map memo for 'J66a, 66b and 66C
This is because the receiving device 12 is provided with a control circuit 65 and a cross-connect switch 68 that operates as a real cell multiplexing means.

Next, the operation of the second embodiment will be explained.

The interface circuit 75 of the transmitting side device 1 performs bit synchronization and cell synchronization after optical-to-electrical conversion of the optical signal from the current transmission line, and an empty cell detection circuit (not shown) detects only real cells from the received information string as F, Write to TFO memory 49.

The actual cells written in the FIF◯ memory 49 are read out using a local clock synchronized with the phase of a local clock source (not shown). This FIFO memory 49 allows the clock and cell phases of the information strings received from each transmission path to match the phase of the local clock source, as in the case of FIG.

The designated VPI cell arrival interval detection circuits 61a, 61b, and 61G receive cell arrival interval designation signals 62a, 62 having the VPI that identifies the line to be switched from the control circuit 65.
Only when receiving b and 62C, the specified VP
The time interval in which the cell of I does not arrive is measured, and when the time interval reaches the value specified by the control circuit 65, the cell arrival interval designation signals 62a, 62b, and 62C of the specified VPI are sent to the control circuit 65. Send.

Tag map memo U66a, 66b and 6 for each VPI
6C is provided for each transmission line, and a tag indicating an output route for each VPI of all lines included in each transmission line is written in each tag map memory 66a, 66b, and 66C. Memory rewrite signals 67a, 67b and 67C are
According to instructions from the control circuit 65, the VP indicating the line to be switched
These are the VPI and tag write signals necessary for rewriting the I tag or switching the line.

The tag map memos J66a, 66b and 66c are rewritten by the header decoding tag adding circuits 63a, 63b and 63.
Tag map memo IJ66a, 66b and 66C from c
Performed when there is no access to. The header decoding tagging circuits 63a, 63b, and 63c read the VPI in the header of the arriving cell, and convert the VPI into a tag map memo for each VPI of the corresponding transmission path. J66a, 66b, and 66c, read the tag corresponding to that VPI from the same memory, bring it back, and insert the tag pit string into the empty bit position in the cell header, or attach the tag bit string externally to the cell, and write the tag. The cell assigned the bit string is sent to the cross-connect switch 68. When externally attaching a tag pit row to a cell, the header decoding tag attaching circuit 6
It is necessary to perform speed conversion at 3a163b and 63c to increase the sending clock speed. Further, in this case, it is necessary to increase the operating clock speed of the cross-connect switch 68, convert the speed using the tag removal circuits 69a, 69b, and 69C, and return to the transmission line speed.

The cross-connect switch 68 transfers each cell to the output route indicated by the tag bit string assigned to each cell. The cross-connect switch 68 is designed so that the order of cells that are manually transmitted from the same transmission path and transferred to the same output path will not be reversed. The tag removal circuits 69a, 69b, and 69C remove tags attached to cells, and when no real cells arrive from the cross-connect switch 68, insert empty cells.
to interface circuit 76. Interface circuit 7
At step 6, a cell synchronization pattern is inserted into an empty cell in the transmitted information string, and then electrical-to-optical conversion is performed and sent to the working transmission line 7f.

When the control circuit 65 receives a line switching signal sent via the data link 43 and the data link transmitting/receiving circuit 42 according to an instruction from the center device 45, the control circuit 65 selects a designated VPI corresponding to the transmission line including the line to be switched. The cell arrival interval detection circuits 61a, 61b, and 61c are provided with a VPI indicating the line to be switched and a specified VPI necessary for line switching.
Cell arrival interval designation signals 62a, 6 indicating the cell arrival interval of
Send 2b and 62c.

Specified VPI cell arrival interval detection signal 52a from designated VPI cell arrival interval detection circuits 61a, 61b, and 61c.
, 62b and 62C, the tag map memory 6 for each VPI containing the VPI indicating the line to be switched is
Rewrite the tag corresponding to that VPI in 6a, 66b and 66c. Thereafter, a line switching completion signal is sent to the center device 45.

The receiving device 12 and the relay devices 18 and 19 have the same configuration as the transmitting device 1. However, V in each device
Tag map memo J73a for each PI? 3b and 73
The contents of c correspond to the line passing through that device. The center device 15 has information on all the lines under its control and transmission delay difference information of information strings between working and protection lines due to line switching, and sends control signals to devices necessary for line switching. send.

In FIG. 6, the switching procedure when switching from the working line passing through the working transmission lines 7e-7f-7g-7h to the protection line passing through the working transmission lines 7e-7i-7j-7h will be described below. First, a circuit switching signal is sent from the center device 45 to the control circuit 72 of the receiving side device 120 via the data link 44 and the data link transmitting/receiving circuit 42 . In response to the line switching signal, the control circuit 72 generates a tag map memo for each VPI corresponding to the switching destination working transmission line 7j. j7
3c, a VPI for identifying the working line 7j to be switched;
A tag having a bit string transferred to the tag removal circuit 69a within the cross-connect switch 68 is written in correspondence with the VPI.

Next, the center device 45 sends a line switching signal to the relay device 19 via the data link 70. In the relay device 19,
In the tag map memory 66c for each VPI corresponding to the working line 71, a VPI that identifies the working line 7j to be switched and a tag having a bit string to be transferred to the working transmission line 7j in the cross-connect switch 68 are stored as the VPI. Write accordingly.

Next, from the center device 45, the sending side bag device 10
A line switching signal is sent to the control circuit 65. This line switching signal also includes transmission delay difference information of information strings between the working and protection lines due to line switching.

The transmission delay difference due to the line switching is the current transmission line 7f,
Assuming that the propagation delay times in 7g, 7i, and 7j are respectively 7ft, 7gt, 7it, and 7jt, and the worst transfer time difference between cells caused by different transfer times for each cell in one cross-connect switch 68 is α, then The formula holds true.

Q= (7it+7jt) −(7ft+7gt) −
3α In FIG. 6, the number of relay devices through which the working and protection lines pass is the same, but if they are different, it is necessary to consider the time required to pass through the relay devices.

When the control circuit 65 receives a line switching signal from the center device 45, if the value of Q is positive, that is, if the delay time of the protection line is larger than the delay time of the working line, the control circuit 65 immediately switches the free switching signal for each VPI. Map memo! The tag corresponding to the VPI identifying the working line in J66a is rewritten to a tag having a bit string such that the cell is transferred to tag removal circuit 69C in cross-connect switch 68. On the other hand, if the value of Q is negative, that is, if the delay time of the working line is greater than the delay time of the protection line, the designated VP
The VPI identifying the working line to be switched and the absolute value of Q are sent to the cell arrival interval detection circuit 61a of I.

In the cell arrival interval detection circuit 61a of the designated VPI, when the cell of the designated VP■ does not arrive for a time corresponding to the absolute value of Q, the cell arrival interval detection circuit 61a controls the control circuit 65.
A cell arrival interval detection signal 62a of the designated VPI is sent to the designated VPI. The control circuit 65 receives this cell arrival interval detection signal 62a.
Immediately after receiving this, the tag map memo IJ66a for each VPI is rewritten in the same manner as described above. Tag map memo! After the rewriting of J66a is completed, the control circuit 65 sends a line switching completion signal to the center device 45, thereby completing the line switching.

In addition, when it is necessary to stop the operation of the working transmission line 7f, for all lines passing through the working transmission line 7f,
The line may be switched to a line passing through another transmission line in the same manner as described above.

Since the third embodiment operates as described above, no instantaneous interruption occurs due to line switching.

In FIG. 6, the cross-connect switch 68 of the receiving device 12 serves as a real cell multiplexing conversion circuit.

Although FIG. 6 shows line switching identified by VPI, there is a tag map memo for each VPI in each of the sending device 1, receiving device 12, and relay devices 18 and 19. It has a tag map memory for each VCI instead of J66a to 66c and 73a to 73c, and
By providing a cell arrival interval detection circuit for a designated VCI in place of the cell arrival interval detection circuits 61a to 61C for I, it is also possible to switch lines for each call.

FIG. 7 is a block diagram showing a fourth embodiment of the present invention.
A case is shown in which the above-mentioned principle is applied to line switching in a subscriber ring transmission line, and the receiving side apparatus has means for multiplexing the working and protection lines into one line.

In FIG. 7, 77 is a clockwise ring transmission line, 78 is a counterclockwise ring transmission line, 79R and 79L are line separation circuits, 80R and 80L are line insertion circuits, 81 is a header decoding line separation circuit, and 82 is a VPI R/L route identification bit map memory (bit MAP) for each, 83 is its memory read signal, 84 is its memory output signal, 85 is a control circuit, 86 is a designated VPI cell arrival interval designation signal,
87 is a designated VPI cell arrival interval detection signal, 61 is a designated VPI cell arrival interval detection circuit, 88 is a memory rewriting signal for the R/L route identification bitmap memory 82, 89 is a header conversion circuit, 90 is a link transmission/reception circuit, 91 is a cell multiplexing highway on the transmitting side, 92 is a cell multiplexing circuit (PM
X), 93 is a cell multiplexing highway on the receiving side, 94 and 95 are data links, 96 is a center device, 97 is a working line, 98 is a protection line, 1 is a transmitting side device, and 12 is a receiving side device .

The transmitting side device 1 and the receiving side device 12 have the same configuration, and will hereinafter be referred to as ADD-DROP MUX.

There are two (7) ADD-DROP MUX in the configuration shown in Figure 7.
Although only a large number of ADDs are shown, there are usually many ADDs on a ring transmission path.
-DROPMUX is connected and each ADD-DRO
PMUX is connected to center device 96 by a data link. Although the ring transmission line interface circuit and the circuit necessary for cell synchronization are omitted in FIG. 7, circuits similar to those shown in FIGS. 5 and 6 are used as these circuits.

The characteristics of the present invention are as shown in FIG. 7, a cell arrival detection circuit 61 for a designated VPI as a real cell arrival interval detection failure, a control circuit 85 as a line switching control means, and a cell multiplexing circuit as a real cell multiplexing means. This is because the circuit 92 is provided.

The line separation circuits 79R and 79L decode the VPI in the header of each cell of the information string sent on the ring transmission lines 77 and 78, and the VPI is used as the ADD-DROP of the own station.
If the MUX identifies the line to be received, the cell is separated and sent to the cell multiplexing circuit 92 no matter which ring transmission path 77 or 78 the cell is sent from. Further, the cell multiplexing circuit 92 sends the received information string with empty cells inserted to the separated cell device to the line insertion circuit 8.
Send to 0R and 80L. Line insertion circuit 80R and 8
0L inserts the real cell sent from the header decoding line separation circuit 81 into the empty cell position in the received information string, and sends it out to the ring transmission paths 77 and 78. If there is no empty cell in the received information string, the actual cell sent from the header decoding line separation circuit 81 is delayed until an empty cell arrives.

Cells passing through line separation circuits 79R and 79L and line insertion circuits 80R and 80L only experience a fixed delay, and are not subject to delay variations as they would when passing through a cross-connect switch. Therefore, the cell transmission delay on ring transmission lines 77 and 78 can be easily known.

The cell multiplexing circuit 92 multiplexes the sent real cells and sends them to the cell multiplexing way 93 on the receiving side.

Each real cell on the cell multiplexing way 93 of the receiving side device 12 has each VCI in accordance with the VCI in the header of each cell.
is sent to the subscriber transmission line connected to the corresponding terminal.

An information string in which real cells sent from a plurality of subscriber transmission lines are multiplexed is sent to the cell multiplexing iz4 way 91 on the transmitting side. Only the VCI that identifies the call is written in the header in the actual cell sent from the subscriber transmission line.

The header conversion circuit 89 decodes the VCI in the header of each received real cell and converts the VPI in the header of the cell into a VPI for identifying the line including the call indicated by the VCI.
The cell arrival interval detection circuit 61 of the designated VP (2) receives the data written in the cell arrival interval detection circuit 61. Normally, the cell arrival interval detection circuit 61 simply passes the received cell and does nothing, but when it receives the cell arrival interval designation signal 86 for the designated VPI, it detects the arrival of cells for the designated VPI from then on. The interval is constantly measured, and when a cell of the designated VPI does not arrive at a designated time, a cell arrival interval detection signal 87 of the designated VPI is sent out.

R/L route identification bitmap memory 82 for each VPI
For all the lines sent out from the ADD-DROP MUX of the own station, each line is sent out to the clockwise ring transmission path 77 or counterclockwise ring transmission path, depending on the VPI that identifies each line. It has a route identification pin (R/L) indicating whether it is sent to route 78. R is clockwise, L
indicates counterclockwise rotation. The root identification pin (R/L) is rewritten from R to L or from L to R by the memory rewrite signal 88.

The header decoding line separation circuit 81 decodes the route identifier VPI in the header of each received real cell, sends the VPI as a memory read signal 83 to the identification bitmap memory 82, and sends the root identification bit R/ L is received as a memory output signal 84. If the route identification pin (R/L) is R, the actual cell is connected to the line insertion circuit 8.
If the signal is L, it is sent to the line insertion circuit 80L.

The center device 96 has information on all lines passing through the ring transmission paths 77 and 78, and sends a line switching signal to the ADD-DROP MUX on the transmitting side of the line to be switched.

Next, a procedure for switching from the working line 97 to the protection line 98 will be described. First, from the center device 96, the data link 94,
A line switching signal is sent to the control circuit 85 of the transmitting device 1 via the data link transmitting/receiving circuit 90. After receiving the line switching signal, the control circuit 85 of the transmitting side device 10 transfers the line switching section to be switched, that is, from the header decoding line separation circuit 81 of the transmitting side device 1 to the cell multiplexing circuit 9 of the receiving side device 12.
In the section up to the output terminal of No. 2, if the transmission delay of the information string on the protection line 98 is larger than that on the working line 97, the memory rewrite signal 88 is sent out as it is, and the Rewrite the route identification pin (R/L) corresponding to the VPI that identifies the line to be switched from R to L.

On the other hand, in the line switching section, if the transmission delay of the information string of the protection line 98 is smaller than that of the working line 97, the VPI for identifying the line to be switched and the information string of the working line 97 and the protection line 98 are The transmission delay difference is sent out as a cell arrival interval designation signal 86 for the designated VPI. Then designated VPI
Immediately after receiving the cell arrival interval detection signal 87, the memory rewriting signal 88 is sent out in the same manner as described above.
The R/L route identification bitmap memory 82 is rewritten. After sending the memory rewriting signal 88, the control circuit 85 sends a line switching completion signal to the center device 96,
Line switching is complete.

Since it operates as explained above, no instantaneous interruption occurs due to line switching. Line switching can also be performed without momentary interruption in the same manner as the line switching.

Also, if you want to stop the operation of one or both of the ring transmission lines 77 and 78 at point 0 in FIG.
For all lines in one or both of the ring transmission lines whose operation passing through the 0 point is to be stopped, a line switching signal is sent from the center device 96 to the ADD-DROP MUX on the transmitting side of each line, and in the same manner as above, instantaneous operation is performed. Line switching can be performed without disconnection.

Further, after the ring transmission line whose operation has been stopped at the 0 point is returned to a normal state, each line can be cut back without interruption in the same manner as described above.

FIG. 8 is a block diagram showing a fifth embodiment of the present invention.
As in the third embodiment, a case is shown in which the above principle is applied to line switching in a subscriber ring transmission line, and the transmitting side equipment has means for multiplexing the working and protection lines into one line.

In FIG. 8, 99 and 100 are loopback routes, 101 is a working line, and 102 is a protection line, and the other circuits are the same as those in FIG. 7. Therefore, the features of the present invention are also the same as in the case of FIG.

FIG. 8 shows both ring transmission lines 77 and 7 at point 0.
8 shows a state in which loopback transmission line switching has been performed in the ADD-DROP MUX at both ends. In this case, the working line 97 shown in FIG.
Automatically switches to the working line 101 shown in the figure. In line switching from the working line 101 to the protection line 102 in FIG. It will be done. When switching from the working line 101 to the protection line 102, the switching procedure can be performed in the same manner as in the case of FIG. 7, except that the line switching section is changed.

Therefore, the line can be switched from the working line 101 to the protection line 102 without momentary interruption.

Fig. 8 shows an example where the loopback position is within the ADD-DROPMUX on the transmitting side of the line, but it can also be performed without interruption in the same way when the loopback is performed within another ADD-DROPMUX. Line switching is possible.

Loopback routes 99 and 10 as described above
After performing line switching for all lines passing through 0 and eliminating all lines passing through loopback routes 99 and 100, both ring transmission lines 77 and 78 at point 0 are restored, and loopback routes 99 and 100 are transmitted. After the line is cut back to its original state, all lines removed from the loopback routes 99 and 100 are cut back in the same manner as the line cutback from line 98 to line 97 shown in FIG. By cutting back,
The ring transmission line can be switched back from the loopback state of the ring transmission line without momentary interruption.

7 and 8 show an example of switching lines identified by VPI, but in FIG. 7 or 8, the cell arrival interval detection circuit 61 of the specified VPI is R/L for each VPI in the reaching M interval detection circuit.
The route identification bitmap memory 82 is
The header decoding line separation circuit 81 decodes the VCI in the header of the actual cell that has arrived, and converts the route identification bitmap (R/L) corresponding to the VCI into the R/L route identification bitmap memory. If the arrived real cells are read from the bitmap memory and sorted according to the route identification pin (R/L), it is possible to switch the line for each call identified by VC, I.

FIG. 9 is a block diagram showing a sixth embodiment of the present invention.
A case is shown in which the above principle is applied to line switching in a subscriber ring transmission line, and loopback switching is performed for each line.
Method for performing switchback without momentary interruption % Formula % In FIG. 9, 103 is a control circuit, 104 is an operation start signal or an operation stop signal, 105 is a header decoding line separation circuit, 106 and 107 are line loopback circuits,
108 is the working line, 109 is the protection line, 110 is the VP
R/L route identification bitmap memory for each I,
The other circuits are the same as those in FIG.

The features of the present invention are as shown in FIG. 9, a cell arrival interval detection circuit 61 for a designated VPI as an actual cell arrival interval detection failure, a control circuit IQ3 as a line switching control means, and an R/L route identification bit for each VPI. The loopback circuits 106 and 107 including a map memory 110, a header decoding line separation circuit 105, and a line insertion circuit 80L or 80R as real cell multiplexing means are provided.

Next, the operation of the sixth embodiment will be explained.

The control circuit 103 is connected to the data link 9 from the center device 96.
4 and 95 and the operation start signal 104 for receiving the line switching signal sent via the data link transmitting/receiving circuit 90.
Or send the operation stop signal 104, memory rewrite signal 88
, a designated VPI cell arrival interval designation signal 86 , and a designated VPI cell arrival interval detection signal 87 are received. R/L route identification bitmap memory 1 for each VPI
10 is a header decoding line separation circuit 105 in a state where line loopback is not performed in all ADD-DROP MUXs connected to ring transmission lines 77 and 78.
For all the lines passing through the clockwise ring transmission line 77, each line
It has a route identification pin (R/L) indicating whether to send it to the ring transmission line 78 or to the counterclockwise ring transmission line 78.

R indicates clockwise rotation, L indicates counterclockwise rotation. Route identification beep) R/
L is rewritten from R to L or from L to R by the memory rewrite signal 88. R/L route identification bitmap memory 11 for each VPI of line loopback circuit 106
The root identification bit R/L of 0 usually indicates the ADD-
All are set to L in preparation for disconnection of the clockwise ring transmission line 77 on the output side of the DROPMUX.

On the other hand, R for each VPI of the line loopback circuit 107
/L The route identification bit R/L of the route identification bit map memory 110 is normally the ADD-DROP MUX of the local station.
In preparation for disconnection of the counterclockwise ring transmission line 78 on the output side, all the lines are set to R. In the normal state, the header decoding and line separation circuit 105 allows each arriving cell to pass through as is and sends it out to the ring transmission path 77 or 78. However, empty cells that arrive are always allowed to pass through as they are and sent out to the ring transmission path 77 or 78. When the header decoding line separation circuit 105 receives the operation start signal 104, it decodes the VPI in the header of each real cell in the information string that arrives thereafter, uses the VPI as a memory read signal 83, and uses the R/VPI for each VPI as a memory read signal 83. The route identification bit R/L corresponding to the VPI should be sent to the L route identification bitmap memory 110 and received as the memory output signal 84, and each of the arrived real cells should be separated by the route identification bit R/L. If it is a cell that should be separated, it is separated and sent to the line insertion circuit 80L or 80R, and an information string with an empty cell inserted at the separated cell position is sent to the ring transmission path 77 or 78.

On the other hand, in the header decoding line separation circuit 105 of the line loopback circuit 107, the route identification bit R/
If L is R, the arrived real cell is inserted into the line insertion circuit 8.
Sends to 0R, and in the case of L, counterclockwise ring transmission line 78
Send to. When the header decoding line separation circuit 105 receives the operation stop signal 104, it returns to the normal state.

Cells passing through the designated VPI cell arrival interval detection circuit 61 and header decoding line separation circuit 105 are only subjected to a fixed delay, and are not subject to delay fluctuations as when passing through a cross-connect switch. Therefore, also in Figure 9,
The cell transmission delay on the ring transmission path can be easily determined.

Next, a procedure for switching from the working line 108 to the protection line 109 will be described. First, the center device 96 sends a line switching signal via the data link 94 and the data link transmitting/receiving circuit 90 to the control circuit 103 of the line loopback circuit 106 of the transmitting device 1 that is the line switching source.

When the control circuit 103 receives the line switching signal, if the header decoding line separation circuit 105 is not in an operating state,
After sending the memory rewriting signal 88 and rewriting all the route identification pins (R/L) in the R/L route identification bitmap memory 110 for each VPI to R, an operation start signal is sent to the header decoding line separation circuit 105. 104 is sent.

If the header decoding line separation circuit 105 is already in operation, the above operation is not performed.

Next, in the control circuit 103, the loopback circuit 106 of the line switching section to be switched, that is, the line of the transmitting side device 10
If the transmission delay of the information string on the protection line 109 is longer than that on the working line 108 in the section from the header decoding line separation circuit 105 to the output terminal of the cell multiplexing circuit 92 of the receiving side device 12, the memory rewriting signal is directly transmitted. 88 to rewrite the route identification bit R/L corresponding to the VPI identifying the line to be switched from R to L in the R/L route identification bit map memory 110.

On the other hand, in the line switching section, if the transmission delay of the information string of the protection line 109 is smaller than that of the working line 108, the VPI for identifying the line to be switched and the information string of the working line 108 and the protection line 109 are transmitted. The delay difference is sent as a cell arrival interval designation signal 86 for the designated VPI. After that, when the cell arrival interval detection signal 87 of the specified VPI is received,
Immediately thereafter, the memory rewrite signal 88 is sent in the same manner as described above to rewrite the R/L route identification bitmap memory 110 for each VPI.

After the control circuit 103 sends out the memory rewrite signal 88,
A line switching completion signal is sent to the center device 96, and the line switching is completed.

Since it operates as explained above, m
Wr does not occur. The switching back of the line can also be carried out without momentary interruption in the same way as the above-mentioned line switching.

If you want to stop the operation of one or both ring transmission lines at point 0 in Figure 9, loop the lines on the transmitting side of all lines in the ring transmission line whose operation passing through point 0 is to be stopped. In the back circuit, line switching is performed without momentary interruption in the same manner as described above. This makes it possible to loop back all lines in the ring transmission line whose operation is to be stopped without momentary interruption. In addition, after returning the ring transmission line whose operation has been stopped to the normal state, each line is cut back without an instantaneous interruption in the same way as above, so that the ring transmission line in the loopback state can be cut back instantaneously. It becomes possible to do this without cutting.

Note that when the control circuit 103 is in a state where no line loopback is performed in the loopback circuit of the line to which the control circuit 103 belongs, after sending out the operation stop signal 104,
A memory rewriting signal 88 is sent to rewrite all route identification bits (R/L) in the R/L route identification bit map memory 110 for each VPI to values in preparation for transmission line disconnection as described above. When a transmission line disconnection occurs due to this,
Simply by sending the operation start signal 104 from the control circuit 103, all lines can be put into the loopback state. If a transmission line disconnection occurs while the header decoding line separation circuit 105 is operating, all route identification bits that do not indicate a loopback state in the R/L route identification bit map memo 'J 110 for each VPI are It is necessary to rewrite L to the loopback state at high speed.

In the above explanation, an example was shown in which the line identified by VPl is switched, but if the cell arrival interval detection circuit 61 of the designated VPI is replaced with the cell arrival interval detection circuit of the designated VCI
R/L route identification bitmap memory 11 for each VPI
0 to the R/L route identification bitmap memory for each VCI, and the header decoding line separation circuit 105 decodes the VCI in the header of the arrived real cell, and the VCI
If the route identification bit R/L corresponding to the VCI is read from the R/L route identification bit map memory for each VCI and the arrived real cells are sorted according to the route identification bit R/L, the call identified by the VCI is Line switching is also possible.

FIG. 10 is a block configuration diagram showing a seventh embodiment of the present invention, in which the above principle is applied to line switching in a subscriber ring transmission line, and each line is switched using an ADD-DROP MUX cross-connect switch. This figure shows a method for performing loopback switching and switching back without momentary interruption.

In FIG. 10, 111 is a header decoding line separation circuit;
112 is a memory read signal, 113 is a memory output signal, 1
14R and 114L are map memories for line separation, 11
5 is a control circuit, 116 is a memory rewrite signal, 117R and 117L are loopback line map memories, 118
R and 118L are header conversion circuits, 119 is a memory read signal, 120 is a memory output signal, 121 is a cross-connect switch that switches in units of cells, 122.
123 and 124 are cross connect switches 1210
Input terminals 125, 126 and 127 are output terminals of the cross-connect switch 121, 128 is the working line, 12
9 is a protection line, and 130 is a header decoding/header converting circuit, and the other circuits are the same as those shown in FIG.

The feature of the present invention is that, in FIG. 10, a cell arrival detection circuit 61 for a designated VP ■ as a failure to detect an actual cell arrival interval;
control circuits 85 and 115 as line switching control means;
Line separation map memory 1J114R and 114L, loopback line map memory 117R and 117L
, header conversion circuits 118R and 118L, a header decoding/header conversion circuit 130, and a cross-connect switch 121 as an actual cell multiplexing means.

Next, the operation of the seventh embodiment will be explained.

In the header decoding line separation circuit 111, empty cells of each cell of the arriving information string are passed through as is, and for real cells, the VPI in the header is decoded, and the VPI is used as a memory read signal 112 for line separation. Map memory 11
Send it to 4R or 114L and note its VPI! J1
A memory output signal 113 is received indicating whether it is within 14R or 114L. This will change the VPI to Memo 1.
If the real cell is in J114R or 114L, the real cell is separated and sent to the header conversion circuit 118R or 118L, and an information string in which an empty cell is inserted at the cell position from which the real cell was separated is sent to the line insertion circuit 80R or 80L. Send.

On the other hand, if the VPI is not in the line separation map memory 114R or 114L, the actual cell is passed through as is. The header decoding line separation circuit 111 only adds a fixed delay to passing cells. The line separation map memories 114R and 114L usually have VPI written therein to identify all the lines to be received by the ADD-DROP MUX of the own station, and the line separation map memories 1J114R and 114L usually have the same VPI. VPI is written. When it becomes necessary to loop back a line within the ADD-DROP MUX of the own station, the memory rewrite signal 116 causes the VPI for identifying the line to be looped back to be written to the line separation map memory 114R or 114L. It will be done.

On the other hand, when the line in the loopback state is to be switched back to the normal state, the VPI for identifying the line in the loopback state is erased from the line separation map memo IJ 114R or 114L by the memory rewrite signal 116.

The control circuit 115 receives a line switching signal sent from the center device 96 via the data links 94 and 95 and the data link transmitting/receiving circuit 90, sends a memory rewriting signal 116, and sends a cell arrival interval designation signal 86 for a designated VPI. ,
Also, the cell arrival interval detection signal 87 of the designated VPI is received.

Map memo for loopback line! J 117R and 1
17L passes through the header decoding line separation circuit 111 corresponding to the loopback line map memo 1J117R and 117L, respectively, in a state where line loopback is not performed in any ADD-DROP MUX connected to the ring transmission line 77 or 78. A VPI for identifying each line is written for all lines.

The header conversion circuit 118R or 118L decodes the VPI in the header of the arrived real cell, and
Send I as a memory read signal 119 to loopback line map memo') 117R or 117L, and read its V
A memory output signal 120 is received indicating whether the PI is in the loopback line map memory 117R or 117L. As a result, in the header conversion circuit 118R, if the VPI in the header of the arrived real cell is in the loopback line map memory 117R, the route identification pin written in the empty bit position in the header of the real cell is converted. After rewriting /L from R to L, the actual cell is sent to the cross-connect switch 121. The above VPI is a map memo for the loopback line! If it is not in J117R, the actual cell is passed through as is. On the other hand, in the header conversion circuit 118L, the VPI in the header of the arrived real cell is mapped to the loopback line map memo 'J117.
If the real cell is in L, the route identification pin written in the empty bit position in the header of the real cell) After rewriting R/L from L to R, the real cell is transferred to the cross-connect switch 12.
Send to 1. The above VPr is a map memo for the loopback line! 7117L, the actual cell is passed through as is.

The cross-connect switch 121 connects each input terminal 122 .
Each real cell is transferred to the target output terminal 125, 126 or 127 according to the root identification bit R/L written in the empty bit position in the header of each real cell input from 123 or 124. Regarding the actual cell input from the input terminal 122, if the root identification bit R/L is R, it is transferred to the output terminal 126, and if it is L, it is transferred to the output terminal 12.
Transferred to 5. Regarding the actual cell input from the input terminal 123, if the route identification pin (R/L) is R,
is transferred to the output terminal 127, and in the case of L, the output terminal 126
will be forwarded to. Regarding the real cell inputted from the input terminal 124, if the root identification bit R/L is R, it is transferred to the output terminal 127, and if it is L, it is transferred to the output terminal 125.

The header decoding header conversion circuit 130 decodes the VPr in the header of each arriving real cell, and sends the VPI as a memory read signal 83 to the R/L route identification bitmap memory 82 for each VPI, corresponding to the VPI. The route identification bit R/L is received as the memory output signal 84. After writing the route identification bit R/L into the empty bit position in the header of the arrived real cell, the real cell is sent to the cross-connect switch 121.

Since the seventh embodiment operates as described above, the root identification bit R/L in the empty bit position in the header of all real cells becomes R on the clockwise ring transmission path 77, and On the ring transmission line 78, all route identification pins (R/L) are set to L.

Next, the line switching procedure will be explained. Regarding the procedure for switching the line passing through the header decoding header conversion circuit 130,
The line switching point between the working and protection lines is from the header decoding line separation circuit 81 to the cross-connect switch 121, and the circuit that multiplexes the working and protection lines of the receiving side device 12 into one line is from the cell multiplexing circuit 92. Cross connect switch 12
1, it can be done in the same way as in the case of Fig. 7.

Here, as an example of line loopback switching, a procedure for switching from the working line 128 to the protection line 129 will be described. First, the center device 96 sends a line switching signal to the control circuit 115 corresponding to the clockwise ring transmission path 77 of the transmitting side device 1, which is a line switching light, via the data link 94 and the data link transmitting/receiving circuit 90. Send.

When the control circuit 115 receives the line switching signal, the control circuit 115 connects the line switching section to be switched, that is, the header decoding line separation circuit 111 on the clockwise ring transmission line 77 side of the transmitting side device 1 to the cross connect switch 121 of the receiving side device 12. If the transmission delay of the information string on the protection line 129 is larger than that on the working line 128 in the section up to the output terminal 126 of Map Memo 1J1
Add to 14R.

On the other hand, in the line switching section, if the transmission delay of the information string of the protection line 129 is smaller than that of the working line 128, the VPI for identifying the line to be switched and the information string of the working line 128 and the protection line 129 are transmitted. The delay difference is sent as a cell arrival interval designation signal 86 for the designated VPI. After that, when the cell arrival interval detection signal 87 of the specified VPI is received,
Immediately after that, a memory rewrite signal 116 is sent to the line separation map memory 114R to identify the line to be switched.
Add PI.

After sending the memory rewrite signal 116, the control circuit 115 sends a line switching completion signal to the center device 96,
Line switching is complete.

Since the seventh embodiment operates as described above, no instantaneous interruption occurs due to line switching. The switching back of the line can also be carried out without momentary interruption in the same way as the above-mentioned line switching. However, in this case, when switching back the line, identify the line to be switched and write the VPI in the line separation map memo! J11
It is necessary to delete it from 4R.

If you want to stop the operation of one or both of the ring transmission lines 77 and 78 at point 0 in FIG. The transmitting side of the line (D A D
D-D ROP MUX II: Perform loopback switching of the line without momentary interruption in the same manner as above. Furthermore, when stopping the operation of the clockwise ring transmission line 77 at the 0 point, the transmission side device 1 transmits,
The line inserted into the clockwise ring transmission line 77 is switched without interruption so that it is inserted into the counterclockwise ring transmission line 78. In addition, when the operation of the counterclockwise ring transmission line 78 is stopped at point 0, the line transmitted from the receiving side device 12 and inserted into the counterclockwise ring transmission line 78 is connected to the clockwise ring transmission line. 77, the line is switched without momentary interruption. As described above, it becomes possible to remove all lines from the ring transmission lines 77 and 78 whose operation is to be stopped without momentary interruption.

Furthermore, the ring transmission lines 77 and 7 whose operation has been stopped are
8 to the normal state, each line is cut back without momentary interruption in the same way as described above, thereby making it possible to cut back the ring transmission line in the loopback state without momentary interruption.

In addition, when a ring transmission line is disconnected, it is necessary to immediately loop back all the lines that passed through the ring transmission line. A map memory for line separation containing 1J114R or 114L is provided separately from the map memory for line separation 1J114R or 114L, and when the ring transmission line is disconnected, the map memory for line separation 1J114R or 114L is switched to the map memory for line separation, or the map memory for line separation is used. It is sufficient to quickly write the VPI identifying all the lines requiring loopback to the map memory 114R or 114L.

In the above explanation, an example has been shown in which a line identified by VPI is switched.
R/L route identification bitmap memory 82 for each VPI
into the R/L route identification bitmap memory for each VCI, and a map memo for line separation! I 114R and 114L
from VPI to VCI, and the contents of loopback line map memories 117R and 117L from VPI to VCI.
CI, and the header decoding header conversion circuit 130, header conversion circuits 118R and 118L, and header decoding line separation circuit 111 process the V in the header of each real cell.
By performing this according to the CI, it is also possible to switch lines for each call identified by the VCI.

The embodiments for switching the subscriber ring transmission line have been described above with reference to FIGS. 7 to 10, but these embodiments can also be directly applied to the switching of the relay ring transmission line. In that case, the header conversion circuit 89 becomes unnecessary.

〔Effect of the invention〕

As explained above, the present invention utilizes empty cells that appear continuously on a line or transmission path, and when switching from a working line or transmission line to a backup line or transmission line causes cell duplication. By switching from the working line or transmission line to the backup line or transmission line at the end of consecutive empty cells to prevent information loss, The line or transmission path can be switched to another line or transmission path without momentary interruption, and has the effect of preventing deterioration of transmission quality due to momentary interruption.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention. FIG. 2 is an explanatory diagram showing the format of an information string (cell) on the transmission path. FIG. 3 and FIG. 4 are explanatory diagrams showing the cell positional relationship at the time of switching. FIG. 5 is a block diagram showing a second embodiment of the present invention. FIG. 6 is a block diagram showing a third embodiment of the present invention. FIG. 7 is a block diagram showing a fourth embodiment of the present invention. FIG. 8 is a block diagram showing a fifth embodiment of the present invention. FIG. 9 is a block diagram showing a sixth embodiment of the present invention. FIG. 10 is a block diagram showing a seventh embodiment of the present invention. FIG. 11 is a block configuration diagram showing a first conventional example. FIG. 12 is a block configuration diagram showing a second conventional example. 1... Sending side device. 2.31.68.121...Cross connect switch, 3...Multiplex conversion unit (MU
X), 4.14.38...Transmission line selection switch, 5.
15.17.22.39.56.65.72.85.1
03.115...Control circuit, 6.13.75.76.
...Interface circuit (INF), 7.7a, 7b,
7 (L 7e, 7f, 7g, 7is7L7k...working transmission line, 8...protection transmission line, 9.10.20.21
．． 43.44.70.71.94.95...Data link, 11.45.96...Center device, 12...
Receiving side device, 16... demultiplexing circuit (D-MUX). 18.19... Relay device, 23... Actual cell arrival interval detection circuit, 24... Changeover switch, 25.41...
Switching control signal, 26... Working line (transmission line), 27.
...protection line (transmission line), 28...actual cell multiplexing conversion circuit (actual cell MUX), 29...empty cell detection circuit, 30...OR circuit, 32...number of consecutive empty cells Detection circuit, 33... Cell synchronization button insertion circuit, 34... Empty cell generation circuit, 35... Station blocker, 36.47...
・Cell phase pulse, 37... Local clock source, 40...
・Continuous empty cell designation signal or continuous empty cell number detection signal,
42...Data link transmission/reception circuit, 46...Regeneration clock, 48.57...Write clock, 49...F
IFO memory, 50... Empty signal, 51...
Successive clocks, 52...AND circuit, 53.55...
- Control signal, 54... Clock control circuit, 58...
Real cell multiplexing conversion unit (actual cell MUX unit), 59... Switch unit, 60... Cell synchronization circuit, 61.61a,
61b, 61C...Cell arrival interval detection circuit, 62
a, 62b, 62c...Cell arrival interval designation signal or cell arrival interval detection signal, 63a, 63b, 63C...
・Header decoding tag adding circuit, 64a, 64b, 64C・
...Memory read signal or memory output signal, 66a,
66b, 66c, 73a, 73b, 73C"I' map memory (tag MAP), 67a, 67b. 67c, 74a, 74b, 74c, 88.116...
・Memory rewrite signal, 69a, 69b, 69c...tag removal circuit, 77.78...ring transmission line, 79R, 7
9L...Line separation circuit, 80R, 80L...Line insertion circuit, 81.105.111...Header decoding line separation circuit, 82.110...R/L route identification bit map memory (Bit MAP> , 83.112.119
...Memory read signal, 84.113.120...Memory output signal, 86...Cell arrival interval designation signal, 87
...Cell arrival interval detection signal, 89.118R1118
L... Header conversion circuit, 90... Data link transmission/reception circuit, 91.93... Cell multiplexing highway, 92
...Cell multiplexing circuit (PMX), 97.101.10
8.128...Working line, 98.102.109.1
29... Protection line, 99.100... Loopback route, 104... Operation start signal or operation stop signal, 106.107... Loopback circuit, 114
R. 114L... Map memory for line separation (MAP for line separation), 117R, 117L... Map memory for loopback line (MAP for loopback line),
122.123.124...Input terminal, 125.12
6.127... Output terminal, 130... Header decoding header conversion circuit, A~○... Real Senope H... Header,
I...Main information, E...Empty cell identification bit string, VCI
, VCIO to VCI3... call identifier, VP Io,
VP I+...Route identifier, a...Manpower information string,
b...Output information string. Patent Applicant Nippon Telegraph and Telephone Corporation Agent Patent Attorney Nao Ide Filial Procedure Amendment 1. Display of the case 1986 Patent Application No. 207855 2, Title of the invention Line switching system 3, Person making the amendment Relationship to the case Patent applicant address 1-1-6 Uchisaiwai-cho, Chiyoda-ku, Tokyo Name (422) Nippon Telegraph and Telephone Corporation Representative Yamaguchi
Attorney 4, Agent 8, Contents of amendment (1) The scope of claims is amended as shown in the attached sheet. (2) On page 9, line 2 of the specification, "transmission delay" is amended to "transmission delay". (3) On page 11, line 18 of the specification, amend "transmission delay" to "transmission delay." (4) On page 19, line 6 of the specification, "if they are equal," is amended to "if they are equal." (5) On page 19, line 7 of the specification, "in the case of multiplexing" is amended to "in the case of multiplexing". 5. Date of amendment order (voluntary amendment) 6. Number of claims increased by amendment 7. “Claims” column of the specification not subject to amendment [Appendix] [Claims] 10. In a line switching system comprising a transmitting side device and a receiving side device including a switching means for switching a working line or transmission line that transmits an information string in units of cells to a backup line or transmission line, the transmitting device is at least a real cell arrival interval detection fault that detects the actual cell arrival interval in the working line or transmission line, and a transmission delay delay line or standby line or If the transmission delay of the transmission line is large, switch at an arbitrary cell break, and if the transmission delay is smaller on the backup line or transmission line than on the working line or transmission line, the actual cell arrival interval detection is missed. a line switching control means for switching at a cell break when the arrival of an actual cell is not detected for a time equal to or more than the delay difference between the working line or transmission line and the protection line or transmission line; The side device is
A line switching system comprising at least real cell multiplexing means for multiplexing real cells among cells transmitted by a working line or transmission line and a protection line or transmission line into one line.

Claims (1)

[Claims] 1. A line equipped with a transmitting side device and a receiving side device including switching means for switching a working line or transmission line that transmits an information string in units of cells to a backup line or transmission line. In the switching method, the transmitting device has at least a real cell arrival interval detection function that detects the actual cell arrival interval within the currently used line or transmission line, and a detection function that detects the actual cell arrival interval on the currently used line or transmission line in a predetermined line switching section. If the transmission delay is large on the protection line or transmission line, switching is performed at an arbitrary cell break, and if the transmission delay is smaller on the protection line or transmission line than on the current line or transmission line, the above-mentioned implementation is performed. line switching control means for switching at cell breaks when the cell arrival interval detection means does not detect the arrival of an actual cell for a time corresponding to a delay difference between the working line or transmission line and the protection line or transmission line; The transmitting side device or the receiving side device includes at least real cell multiplexing means for multiplexing real cells among the cells transmitted by the working line or transmission line and the protection line or transmission line into one line. A line switching method characterized by: