JPH0253969B2 - - Google Patents
Info
- Publication number
- JPH0253969B2 JPH0253969B2 JP55041419A JP4141980A JPH0253969B2 JP H0253969 B2 JPH0253969 B2 JP H0253969B2 JP 55041419 A JP55041419 A JP 55041419A JP 4141980 A JP4141980 A JP 4141980A JP H0253969 B2 JPH0253969 B2 JP H0253969B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- gate trigger
- trigger element
- output
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000001514 detection method Methods 0.000 claims description 5
- 230000002457 bidirectional effect Effects 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 10
- 239000003990 capacitor Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 2
- 230000003020 moisturizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M5/00—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases
- H02M5/02—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc
- H02M5/04—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters
- H02M5/22—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M5/25—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
- H02M5/257—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Circuit Arrangement For Electric Light Sources In General (AREA)
- Power Conversion In General (AREA)
- Thyristor Switches And Gates (AREA)
Description
【発明の詳細な説明】
本発明は、調光装置等に利用できるスイツチン
グ回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a switching circuit that can be used in a light control device or the like.
従来、この種のスイツチング回路においては、
第５図に示すように、交流電源１′にゲートトリ
ガ素子２′と負荷３′との直列回路を挿入し、前記
交流電源１′の出力端にインピーダンス７′を介し
て整流回路９′の交流端を接続し、前記整流回路
９′の直流端に直流電源回路５′を配置し、前記直
流電源回路５′の出力端に制御回路１４′を挿入
し、前記制御回路１４′の出力をフリツプフロツ
プ２５を介して発光ダイオード２６に与え、前記
発光ダイオード２６の発光をフオトトランジスタ
２７で受光し、適宜の回路を介してゲートトリガ
素子２′のゲートに与えることによりゲートトリ
ガ素子２′を駆動していたが、ゲートトリガ素子
２′のオンに関係なく発光ダイオード２６を連続
動作させてゲート電流を与えることは、直流電源
回路５′の容量を大きくする必要があり、不経済
であり、小型化に問題があつた。 Conventionally, in this type of switching circuit,
As shown in FIG. 5, a series circuit of a gate trigger element 2' and a load 3' is inserted into an AC power source 1', and a rectifier circuit 9' is connected to the output end of the AC power source 1' via an impedance 7'. The AC end is connected, a DC power supply circuit 5' is arranged at the DC end of the rectifier circuit 9', a control circuit 14' is inserted into the output end of the DC power supply circuit 5', and the output of the control circuit 14' is connected. The light emitted from the light emitting diode 26 is applied to the light emitting diode 26 via the flip-flop 25, the light emitted from the light emitting diode 26 is received by the phototransistor 27, and the light is applied to the gate of the gate trigger element 2' via an appropriate circuit to drive the gate trigger element 2'. However, continuously operating the light emitting diode 26 to provide a gate current regardless of whether the gate trigger element 2' is on requires increasing the capacity of the DC power supply circuit 5', which is uneconomical and requires miniaturization. There was a problem.
また、直流電源回路５′の容量を小さくするた
めゲート電流をパルス化することも提案された
が、ゲートトリガ素子２′のオンが失敗すると半
サイクルの間完全に不導通となり調光装置として
は制御が不安定となる問題がある。 It has also been proposed to pulse the gate current in order to reduce the capacity of the DC power supply circuit 5', but if the gate trigger element 2' fails to turn on, it becomes completely non-conductive for half a cycle, making it difficult to use as a dimming device. There is a problem that control becomes unstable.
本発明は上記の欠点を改善するために提案され
たもので、その目的は、スイツチング素子のオン
動作に失敗しても、引き続き再びスイツチング素
子のオン動作を行うことのできるスイツチング回
路を提供することにある。 The present invention was proposed in order to improve the above-mentioned drawbacks, and its purpose is to provide a switching circuit that can continue to turn on the switching element again even if the switching element fails to turn on. It is in.
また、本発明ではフオトカプラを使用せず、従
つて小型化、低コスト化を実現するスイツチング
回路を提供することにある。更に本発明では、ゲ
ートトリガ素子のオン時にはそのゲート電流を停
止させて、省電力化を実現するスイツチング回路
を提供することにある。 Another object of the present invention is to provide a switching circuit that does not use a photocoupler and can therefore be made smaller and lower in cost. A further object of the present invention is to provide a switching circuit that stops the gate current when the gate trigger element is turned on, thereby realizing power saving.
以下、本発明の実施例を図面に沿つて説明す
る。 Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例を示す回路図であ
る。図において、１は交流電源で交流電圧V1（図
示の矢印方向の電圧をそれぞれV1a，V1bとす
る。）を出力する。交流電源１にはゲートトリガ
素子２と負荷３とが直列に挿入されている。４は
ゲートトリガ素子２にゲート信号を与えるトリガ
回路で、直流電源回路５と論理回路素子からなる
論理回路６とで構成される。また、７はトリガ回
路４に適正な電圧を与えるためのインピーダンス
である。 FIG. 1 is a circuit diagram showing one embodiment of the present invention. In the figure, 1 is an AC power supply that outputs an AC voltage V 1 (the voltages in the arrow directions shown in the figure are V 1a and V 1b , respectively). A gate trigger element 2 and a load 3 are inserted in series in an AC power supply 1. A trigger circuit 4 provides a gate signal to the gate trigger element 2, and is composed of a DC power supply circuit 5 and a logic circuit 6 made up of logic circuit elements. Further, 7 is an impedance for applying an appropriate voltage to the trigger circuit 4.
直流電源回路５はツエナーダイオード８，ダイ
オード９及びコンデンサ１０で構成され、コンデ
ンサ１０の両端に平滑化され、図示の極性の直流
を出力する。 The DC power supply circuit 5 is composed of a Zener diode 8, a diode 9, and a capacitor 10, and is smoothed across both ends of the capacitor 10, and outputs DC with the polarity shown.
また、論理回路６は一方の端子のみ反転した入
力が加えられるオア回路１１（以下オア回路とい
う），アンド回路１２，トランジスタ１３及び制
御回路１４で構成される。オア回路１１の一方の
入力端は、直流電源回路５のコンデンサ１０の一
端とゲートトリガ素子２と負荷３との接続点に直
列に挿入された抵抗１５と抵抗１６との接続点に
接続し、オア回路１１の他方の反転入力端は同様
にコンデンサ１０の一端とゲートトリガ素子２と
負荷３との接続点に直列に挿入された抵抗１７と
抵抗１８との接続点に接続し、オア回路１１の出
力はアンド回路１２の入力の一端に接続される。
また、制御回路１４の出力はアンド回路１２の入
力の他端に入力され、アンド回路の出力は抵抗１
９を介してトランジスタ１３のベースに接続され
る。トランジスタ１３のコレクタは抵抗２０を介
してゲートトリガ素子２のゲートに接続され、エ
ミツタはコンデンサ１０の一端に接続される。な
お、制御回路１４は負荷３（例えば白熱ランプ）
に対し、給電制御の条件に応じて信号（デジタル
信号ハイ／ロー）を出力する。 The logic circuit 6 is composed of an OR circuit 11 (hereinafter referred to as an OR circuit) to which an inverted input is applied to only one terminal, an AND circuit 12, a transistor 13, and a control circuit 14. One input end of the OR circuit 11 is connected to a connection point between a resistor 15 and a resistor 16 inserted in series between one end of a capacitor 10 of the DC power supply circuit 5, the gate trigger element 2, and the load 3, The other inverting input terminal of the OR circuit 11 is similarly connected to the connection point between a resistor 17 and a resistor 18 which are inserted in series between one end of the capacitor 10 and the connection point between the gate trigger element 2 and the load 3. The output of is connected to one end of the input of AND circuit 12.
Further, the output of the control circuit 14 is input to the other end of the input of the AND circuit 12, and the output of the AND circuit is input to the resistor 1.
9 to the base of transistor 13. The collector of the transistor 13 is connected to the gate of the gate trigger element 2 via the resistor 20, and the emitter is connected to one end of the capacitor 10. Note that the control circuit 14 is connected to a load 3 (for example, an incandescent lamp).
A signal (digital signal high/low) is output according to the power supply control conditions.
次に、第２図ａ及びｂの波形図を用いて第１図
に示した実施例の動作について第１図を参照して
説明する。また、第２図ａ及びｂにおけるV1a，
V1b，V6は第１図の矢印方向側が＋電位のとき正
として示す。まず第２図ａを用いて、制御回路１
４の出力V4がロー（ゲートトリガ素子がオフの
場合）について述べる。 Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 1 using the waveform diagrams of FIGS. 2a and 2b. Also, V 1a in Fig. 2 a and b,
V 1b and V 6 are shown as positive when the side in the direction of the arrow in FIG. 1 has a positive potential. First, using FIG. 2a, control circuit 1
4 output V4 is low (when the gate trigger element is off).
まず、第２図ａにおいて、交流電圧V1，直流
電源回路５のV2，V3は、交流電圧V1がV1aの場
合、ツエナーダイオード８にはツエナー電圧V2
が発生し、V1bの場合、ツエナー電圧V2は零とな
り、このツエナー電圧V2はダイオード９とコン
デンサ１０で整流・平滑されてコンデンサ１０の
両端に直流化された電圧V3を出力する。電圧V3
により制御回路１４及びゲートトリガ素子２のゲ
ート電流供給を行う。 First, in FIG. 2a, the AC voltage V 1 and V 2 and V 3 of the DC power supply circuit 5 are such that when the AC voltage V 1 is V 1a , the Zener diode 8 has a Zener voltage V 2 .
occurs, and in the case of V 1b , the Zener voltage V 2 becomes zero, and this Zener voltage V 2 is rectified and smoothed by the diode 9 and the capacitor 10, and a DC voltage V 3 is output across the capacitor 10. Voltage V 3
The gate current is supplied to the control circuit 14 and the gate trigger element 2.
次に、オア回路１１の入力V5，V6は、交流電
圧V1がV1aの場合、点ａは点ｂより電位が高い。
また、点ｃは点ｂより負荷３を介しているため、
ほぼ点ｂと同様の電位となり、点ａより電位が低
くなる。この時電圧V5，V6は電圧検出用抵抗１
５又は１７を通し、入力しきい値（ハイ又はロー
と判断する電圧レベルで、破線で示す）より低く
なる。この時オア回路１１出力は、入力（V6）
によりハイ出力となる。 Next, regarding the inputs V 5 and V 6 of the OR circuit 11, when the AC voltage V 1 is V 1a , the potential at point a is higher than that at point b.
Also, since point c is connected to point b via load 3,
The potential is approximately the same as that at point b, and the potential is lower than that at point a. At this time, voltages V 5 and V 6 are voltage detection resistor 1
5 or 17, and becomes lower than the input threshold (voltage level determined to be high or low, indicated by a broken line). At this time, the OR circuit 11 output is the input (V 6 )
This results in high output.
次にV1bの場合、同様に点ｃが点ａより高く、
電圧検出用抵抗１５，１７を通して電圧V5，V6
はオア回路１１入力のしきい値より高くなる。こ
の時オア回路１１出力は、入力（V5）によりハ
イ出力となる。 Next, in the case of V 1b , point c is higher than point a, and
Voltage V 5 , V 6 through voltage detection resistors 15 and 17
becomes higher than the threshold of the OR circuit 11 input. At this time, the output of the OR circuit 11 becomes a high output due to the input (V 5 ).
以上のように電圧V1の各半サイクル（V1a，
V1b）でオア回路１１出力はハイとなり、アンド
回路１２入力V7はハイであるが、電圧V4はロー
で、アンド回路出力はローとなり、トランジスタ
１３はオンせず、従つてゲートトリガ素子２もま
たオフ状態を保つ。電圧V7がハイであるため、
制御回路１４出力（V4）がハイとなればアンド
回路出力はハイとなり、それによりトランジスタ
１３がオンし、ゲートトリガ素子２にはゲート電
流（抵抗２０により限流）が流れオンする。 As shown above, each half cycle of voltage V 1 (V 1a ,
V 1b ), the output of the OR circuit 11 becomes high, the input V 7 of the AND circuit 12 is high, but the voltage V 4 is low, the output of the AND circuit becomes low, and the transistor 13 is not turned on, so the gate trigger element 2 also remains off. Since the voltage V 7 is high,
When the output (V 4 ) of the control circuit 14 becomes high, the output of the AND circuit becomes high, thereby turning on the transistor 13, and a gate current (current limited by the resistor 20) flows through the gate trigger element 2, turning it on.
ゲートトリガ素子２がオンした後の動作につい
て第２図ｂを用いて説明する。 The operation after the gate trigger element 2 is turned on will be explained using FIG. 2b.
電圧V4がｔにおいてローからハイになり、ゲ
ートトリガ素子２がオンすると、点ｃは点ａとほ
ぼ同電位となる。点ａは直流電源回路５の＋と共
通しているので、抵抗１５−１６，１７−１８間
には直流電圧がかかる。 When the voltage V 4 changes from low to high at t and the gate trigger element 2 is turned on, point c becomes approximately at the same potential as point a. Since point a is common to + of the DC power supply circuit 5, a DC voltage is applied between the resistors 15-16 and 17-18.
電圧V5はゲートトリガ素子２がオンすると、
しきい値より低い電圧になるように抵抗１５，１
６により設定されている。 When the gate trigger element 2 is turned on, the voltage V5 is
Resistor 15,1 so that the voltage is lower than the threshold value
It is set by 6.
また、電圧V6はしきい値より高い電圧になる
ように抵抗１７，１８により設定されている。 Further, the voltage V 6 is set by resistors 17 and 18 so as to be higher than the threshold value.
オア回路１１出力は電圧V5がしきい値より高
いか又は電圧V6がしきい値より低い時、出力V7
がハイとなるものであるから、ゲートトリガ素子
がオンするまでハイとなつていた電圧V7は、ゲ
ートトリガ素子がオンするとローとなり、アンド
回路１２出力はローとなり、ゲートトリガ電流は
停止する。 OR circuit 11 output is when voltage V 5 is higher than the threshold or voltage V 6 is lower than the threshold, output V 7
Since the voltage V 7 is high until the gate trigger element is turned on, the voltage V 7 becomes low when the gate trigger element is turned on, the output of the AND circuit 12 becomes low, and the gate trigger current stops.
ゲートトリガ素子は半サイクルオンした後、電
圧V1がゼロ（電流ゼロ）においてオフする。オ
フすると、オア回路１１の出力はハイとなり、電
圧V4がハイであるため１３はオンし、ゲートト
リガ電流が流れ、ゲートトリガ素子２がオンす
る。 The gate trigger element turns on for half a cycle and then turns off at zero voltage V1 (zero current). When turned off, the output of the OR circuit 11 becomes high, and since the voltage V 4 is high, 13 is turned on, a gate trigger current flows, and the gate trigger element 2 is turned on.
以上の説明のように、アンド回路１２の一端入
力は制御回路１４の信号により、ゲートトリガ素
子をオン／オフ制御すると共に、アンド回路の他
入力端は、オア回路を含む電圧検出回路により、
ゲートトリガ素子がオフの場合、アンド回路入力
V7はハイとなり、電圧V4によりオンしようとす
る待機状態を提供し、ゲートトリガ素子がオンし
た時は、ゲートトリガ電流を停止させる作用があ
るため、仮りに、最初のゲート電流により、ゲー
トトリガ素子２のオンが失敗したとしても、ゲー
トトリガ素子２がオフしている間は、常に電圧
V7がハイとなつているので、電圧V4がハイであ
れば再びゲート電流が流れ、ゲートトリガ素子２
をオンさせることができる。 As described above, one end input of the AND circuit 12 controls the gate trigger element on/off by a signal from the control circuit 14, and the other input end of the AND circuit is controlled by a voltage detection circuit including an OR circuit.
If the gate trigger element is off, the AND circuit input
V 7 becomes high and provides a standby state in which the voltage V 4 tries to turn on, and when the gate trigger element turns on, it has the effect of stopping the gate trigger current. Even if trigger element 2 fails to turn on, the voltage remains constant while gate trigger element 2 is off.
Since V 7 is high, if voltage V 4 is high, the gate current flows again and gate trigger element 2
can be turned on.
すなわち、本発明のスイツチング回路はゲート
トリガ素子２が一旦オンすれば、ゲート電流は停
止し、またゲートトリガ素子２のオンが失敗した
場合は、交流電源１の半サイクルの間に再度ゲー
ト電流を流してゲートトリガ素子２をオンするこ
とができる。 That is, in the switching circuit of the present invention, once the gate trigger element 2 is turned on, the gate current is stopped, and if the gate trigger element 2 fails to turn on, the gate current is restarted during a half cycle of the AC power supply 1. The gate trigger element 2 can be turned on by allowing the current to flow.
第３図は本発明の他の実施例を示す回路図、第
４図は第３図に示す回路の動作を説明する波形を
示す図である。第３図は第１図の回路において、
オア回路１１とアンド回路１２との間に積分回路
２１を付加したものである。積分回路２１は抵抗
２２，コンデンサ２３及びダイオード２４で構成
される。積分回路２１の動作は第４図の波形で示
すように、オア回路１１の出力V7を積分してア
ンド回路１２の入力V7′とし、アンド回路１２の
出力V8の位相を制御する。この位相制御は積分
回路２１の抵抗２２の値を可変とすることにより
位相制御ができる。 FIG. 3 is a circuit diagram showing another embodiment of the present invention, and FIG. 4 is a diagram showing waveforms for explaining the operation of the circuit shown in FIG. 3. Figure 3 shows the circuit in Figure 1,
An integrating circuit 21 is added between an OR circuit 11 and an AND circuit 12. The integrating circuit 21 is composed of a resistor 22, a capacitor 23, and a diode 24. As shown by the waveforms in FIG. 4, the operation of the integrating circuit 21 is to integrate the output V 7 of the OR circuit 11 and use it as the input V 7 ' of the AND circuit 12, thereby controlling the phase of the output V 8 of the AND circuit 12. This phase control can be performed by making the value of the resistor 22 of the integrating circuit 21 variable.
叙上のように本発明によれば、交流電源と負荷
との間にゲートトリガ素子を接続した回路におい
て、直流電源回路の両端にゲートトリガ素子を介
して２組の直列抵抗素子を接続し、前記２組の直
例抵抗素子を構成する夫々の抵抗の接続点をオア
回路の入力端に接続し、前記オア回路の出力と給
電条件に応じて信号を出力する制御回路の出力と
をアンド回路に加え、前記アンド回路よりの出力
を前記ゲートトリガ素子のゲートに与えるように
構成してあるので、たとえゲートトリガ素子のオ
ンに失敗があつても、引き続き、再びゲートトリ
ガ素子のオン動作を行いうる効果を有する。 As described above, according to the present invention, in a circuit in which a gate trigger element is connected between an AC power supply and a load, two sets of series resistance elements are connected to both ends of the DC power supply circuit via the gate trigger element, The connection point of each of the resistors constituting the two sets of direct resistance elements is connected to the input end of an OR circuit, and the output of the OR circuit and the output of a control circuit that outputs a signal according to power supply conditions are connected to an AND circuit. In addition, since the configuration is such that the output from the AND circuit is applied to the gate of the gate trigger element, even if there is a failure in turning on the gate trigger element, the gate trigger element will continue to turn on again. It has a moisturizing effect.
また本発明によれば、フオトカプラを使用せ
ず、従つて小型化、低コスト化のスイツチング回
路をうることができ、さらにゲートトリガ素子の
オン時には、そのゲート電流を停止させて省電力
化が図れるスイツチング回路をうる効果を有す
る。 Further, according to the present invention, it is possible to obtain a switching circuit that does not use a photocoupler and is therefore smaller in size and lower in cost.Furthermore, when the gate trigger element is turned on, the gate current is stopped, thereby saving power. This has the effect of providing a switching circuit.
第１図は本発明の一実施例を示す回路図、第２
図ａ，ｂは第１図の回路動作を説明する波形図、
第３図は本発明の他の実施例を示す回路図、第４
図は第３図の回路動作を説明する波形図、第５図
は従来例を示す回路図である。
１…交流電源、２…ゲートトリガ素子、３…負
荷、４…トリガ回路、５…直流電源回路、６…論
理回路、１１…オア回路、１２…アンド回路、１
３…トランジスタ、１４…制御回路、２１…積分
回路。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
Figures a and b are waveform diagrams explaining the circuit operation of Figure 1,
FIG. 3 is a circuit diagram showing another embodiment of the present invention;
This figure is a waveform diagram explaining the circuit operation of FIG. 3, and FIG. 5 is a circuit diagram showing a conventional example. DESCRIPTION OF SYMBOLS 1...AC power supply, 2...Gate trigger element, 3...Load, 4...Trigger circuit, 5...DC power supply circuit, 6...Logic circuit, 11...OR circuit, 12...AND circuit, 1
3...Transistor, 14...Control circuit, 21...Integrator circuit.
Claims (1)
を検出する電圧検出手段の出力と負荷への給電制
御を行う制御回路の出力とのアンド構成と、この
アンド構成の出力によつて前記双方向のゲートト
リガ素子へのゲートトリガ電流を断続するスイツ
チ手段とを含み、前記制御回路の出力によつて前
記アンド構成を制御してゲートトリガ電流を供し
て前記双方向のゲートトリガ素子をオンすると共
に、前記双方向のゲートトリガ素子のオン状態に
応じて前記電圧検出手段がゲートトリガ電流を停
止させるよう前記アンド構成を制御することを特
徴とするスイツチング回路。1 AND configuration of the output of the voltage detection means that detects the on/off state of the bidirectional gate trigger element and the output of the control circuit that controls the power supply to the load, and the output of this AND configuration switching means for intermittent gate trigger current to the gate trigger element, controlling the AND configuration by the output of the control circuit to provide the gate trigger current to turn on the bidirectional gate trigger element; A switching circuit characterized in that the voltage detection means controls the AND configuration so as to stop the gate trigger current depending on the on state of the bidirectional gate trigger element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4141980A JPS56139074A (en) | 1980-03-31 | 1980-03-31 | Switching circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4141980A JPS56139074A (en) | 1980-03-31 | 1980-03-31 | Switching circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56139074A JPS56139074A (en) | 1981-10-30 |
| JPH0253969B2 true JPH0253969B2 (en) | 1990-11-20 |
Family
ID=12607828
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4141980A Granted JPS56139074A (en) | 1980-03-31 | 1980-03-31 | Switching circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56139074A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5478470A (en) * | 1977-12-02 | 1979-06-22 | Mitsubishi Electric Corp | Ignition equipment for dc breaker |
-
1980
- 1980-03-31 JP JP4141980A patent/JPS56139074A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5478470A (en) * | 1977-12-02 | 1979-06-22 | Mitsubishi Electric Corp | Ignition equipment for dc breaker |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56139074A (en) | 1981-10-30 |
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