JPH0253325A - Ad converter test instrument - Google Patents

Abstract

PURPOSE:To relieve the load of a CPU by using a successive approximation register, a counter and a comparator so as to detect an output change of an A/D converter (DUT) automatically and transferring an error between an ideal change point of the DUT and a real change point to the CPU. CONSTITUTION:The binary search detecting a change point of the A/D converter (DUT) 1 is implemented by the successive approximation register 12 and the comparator. Then by how many bits of deviation a change point of the DUT takes place from the ideal change point (e.g., the ideal change point is referred to as when a data of the loworder 4 bits of a data DA is 10000) able to be read from the conversion setting data DA with high resolution fed to a main DAC 2 is observed by using the hardware provided newly. Then the conversion setting data fed to the main DAC 3 at the said point of change is transferred to the CPU. Thus, the load of the CPU is relieved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an apparatus for testing the DC linearity of an AD converter. To explain in more detail, the AD converter to be tested (denoted as DOT; DUT; Device 11nd)
This invention relates to a device for testing linearity by applying an output signal of a DA converter having a higher output resolution than er Te5t to this DUT.

[Conventional technology]

To test the linearity of the AD converter, for example, as shown in FIG. 6, an output signal vA of the DA converter 2 having an output resolution higher than the conversion resolution of the DUT 1 is applied.

In FIG. 6, the linearity test for DOT 1 is performed as follows. First, as shown in FIG. 7, the output signal VA (0) of the DA converter 2 when the converted data corresponding to the zero point of DOT 1 changes from H to L H, and
The conversion data corresponding to the full scale of 1 is F' E 1
The output signal VA (FS-1) of the DA converter 2 when changing from 4 to FF'H is determined. Next, based on the following equation, an ideal value Va (n) at a point where arbitrary data n (for example, 7E) of DUT I increases by one step and changes to n±1 (for example, 7Fl) is calculated for all steps.

Then, the output signal of the DA converter 2 is changed so that the output signal of the DOT 1 changes one bit at a time to obtain the actual measured value Vi (n), and the ideal value V calculated as described above is obtained.
Find the error ■ε(n) from a(n). Expressing these relationships in a formula is: VE (n) −Va (n) VA (n) However, according to such a conventional example, it is necessary to calculate a huge number of times (for example, in the case of 2 bits) for every step of the output of DOT 1. It is necessary to perform multiplication and division operations (212 times), which requires a long test time.

Therefore, in view of these points, the present applicant has filed a patent application filed in 1986-
No. 171013 rA/D Conversion Testing Device" (hereinafter referred to as the "prior application") was filed. Figure 8 shows the principle structure of this earlier application.
FIG. 9 shows a specific example of the configuration of FIG. 8.

In the apparatus shown in FIG. 8, the main DAC 3 is a DA converter that outputs a main signal for testing the linearity of DUT i. This main DAC3 is an N-bit DUT.
It has a conversion resolution (N0M) bits higher than 1 and converts (N0M) bits of conversion setting data (see Figure 9) added from a central processing unit (hereinafter referred to as CPU) (not shown) into an analog value. This signal is converted and sent to the next stage FS/DAC4.
to DUT 1 via

l5-DAC4 is a DA converter for matching the full scale value of the output of the main DAC3 to the full scale input of the DUT 1. This FS.0^C4 is not limited to a DA converter, but can be configured with a programmable gain amplifier that amplifies the output of C3 to the main D introduced at a magnification specified by CP tJ (not shown).

The zero point DAC 5 is a DA converter that sets the zero point of the main signal output from the main DAC 3 according to the actual zero point of the DUT 1. The zero point DAC 5 is not limited to a DA converter, but may be of any type as long as it can output a constant voltage under control from a CPU (not shown).

6 is a summing amplifier. Main DAC3 output is FS-
It is applied via DAC 4 to summing amplifier 6 where it is summed with the output of zero point DAC 5 and applied to DUT 1.

In FIG. 9, numerals 3 and 4.5 represent the two-main DAC 3, FS-DAC 4, and zero-point DAC 5 shown in FIG. 8, respectively. In the same figure, the main DAC3 and the zero point DAC5 have reference voltage sources vr3 and vr, respectively.
5 is provided, and its DA conversion is performed by a resistor network RN.
3 and RN5. That is, in the resistor network, the resistor elements corresponding to each bit are selectively connected according to the bit data applied from the CPU (not shown), and the reference voltage Vr3 is connected.
+vr5 is converted into an analog signal by applying a predetermined weight.

On the other hand, FS-DAC4 uses the main DA as a reference voltage source.
The converted output of C3 is added. This FS-DAC4
operates as a programmable gain amplifier. That is, by setting constant data from the CPU to the resistor network RN4, the output of the main DAC3 changes to rs-DAC4.
is multiplied according to the set magnification and output. Then, from the summing amplifier 6, this FS, the output of the DAC 4, and the output of the zero point DAC 5 corresponding to the zero point are added and added to the DOT 1.

The apparatus shown in FIGS. 8 and 9 operates as follows. 0υ
■1, as shown in Fig. 4, is the offset error Voe with respect to the ideal zero input VBo, the ideal input width SP,
Based on the actual input width SP2 for (SP2/SP
, )1.

These errors are caused by the AD converter (
Since it has nothing to do with the linearity of DOT), it is necessary to correct it before testing the linearity characteristics. Therefore, the actual input of DOT 1 including these errors and the main DAC
FS/DAC4 and zero point D so that the outputs of 3 match
Perform correction with AC5. The FS-DAC 4 corrects the gain error Ge, and the zero point DAC 5 corrects the offset error.

I will explain in detail. It is assumed that DOT 1 has a resolution of 8 bits and an actual input of 0.9V to 2.1V. On the other hand, if the output of main DAC3 is set to θ~10V, zero point DAC5 is set to 0.9v, and FS・0^C4
It is sufficient to set 0.12 times. With this setting, when the main DAC3 outputs 0 to 10 V, the DU
TI Ni is 0.9V~2. IV is added.

Here, if the resolution of main DAC 3 is 12 bits, which is 4 bits higher than that of DUT 1, then the
The lowest hit of the upper 8 bits of the setting data of No. 3 (see Figure 9) is the ideal 11-3B (4,706
rmV). Then, the lower 4 bits of the conversion setting data added to this main DAC3 become DU
This coincides with the ideal change point of the conversion output data of T1, and by changing the conversion setting data added to the main DAC 3, the conversion setting data of the point where the conversion output data of DUT 1 actually changes (1/16) [3B accuracy (approximately ±0
．． 151'Ill+l), the error from the ideal change point can be measured.

To summarize, the device of the prior application (devices in Figures 8 and 9) observes how many bits shift from the lower 4 bits of the conversion setting data added to the main DAC 3 to produce the change point of 011. By doing so, the linearity of DUTI can be measured without requiring complicated calculations.

[Invention or problem to be solved]

The first AD converter test equipment as described above has a much higher performance compared to the equipment shown in Figure 6. ! /8 It becomes almost unnecessary to fill in the time, and an extremely large effect can be obtained, but there is a problem that it takes too much time for the CPU that controls the device of this prior application.

That is, the CPU of the device of the prior application is connected to the main DAC3 and the FS-D.
It controls AC4 and zero point DAC5. Here FS-D
The control of AC4 and zero point DAC5 is only set once at the beginning of the test, so it does not put a burden on the CPU, but the control of main DAC3 is controlled by changing #1i! without observing the output change of []lIT L! ! It is a burden to add setting data to the main DAC 3 one by one. As the resolution of recent AD converters (DUTs) has been increasing, this burden is on the rise.

The purpose of the present invention is to automatically detect a change in the output of DOT 1 and transfer the conversion setting data added to the main DAC 3 at this change point to the CP tJ to reduce the burden on the CPU.
An object of the present invention is to provide a D converter testing device.

[Means to solve the problem]

In order to solve the above problems, the present invention has a function with higher resolution ((N+M) bits) than the N-bit AD converter to be tested (hereinafter referred to as 011), and the output DC of the counter described later is Conversion setting data DA with the output DS of the successive approximation register as the lower digit
A counter that outputs a digital signal DC with the same number of bits as the number of output bits (N) of the DUT; Counter output D
A comparator that compares C and the output 00 of DOT and outputs a signal SC when the contents are different, and a so-called binary - a successive approximation register that uses a search method to determine all bit values of the M bits at the output change point of the DUT.

[Effect]

In the present invention, the DUT 1σ) is a binary
The search is performed using a successive approximation register 12 and a comparator. Then, the ideal change point that can be read from the high-resolution conversion setting data DA added to the main DAC2 is, for example, the lower 4 bits of data DA is 1000.
By using this newly installed hardware to observe how many bits the old IT's changing point deviates from the ideal changing point), the error voltage from the ideal value can be measured, reducing the burden on the CPU. be done.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a diagram showing an embodiment of the AD converter testing device according to the present invention, FIG. 2 is a flowchart showing the operation of the device shown in FIG. 1, and FIG. FIG. 5 is a diagram showing the relationship between the input/output signals of the main 0^C3 and the output of the DUT 1.

In FIG. 1, numeral 1 is a DUT, which is the same AD converter as the test target as explained in FIGS. 8 and 9.

2 is main 0^C13 is FS-DAC, 4 is zero point DAC
, '6 are summing amplifiers, which may be the same as those explained in the ninth factor of FIG. 8.

To clarify, assuming that the DUT has an N-bit output, main 0^C2 has a higher resolution (N+M) bit function than DUT 1. Normally, in linearity tests, , DUT as main DAC2
Since it is sufficient to have a resolution higher than 1 to 4 bits, in this specification, M = 4 bits (DUT
= 6 bits, go to main 〇 C2 is 10 bits).

The FS-DAC 3 may be one that amplifies the main signal introduced from the main DAC 2 by any magnification (including an amplification factor of 1 or less) under the control of the CPU 7.

The zero point DAC 4 sets the zero point of the main signal according to the actual zero point of the DUT 1. This zero point DACJ
Any configuration may be used as long as it is a means that can output a constant voltage under control.

In this way, as in the previous application, [S DAC 3 corrects the gain error Ge of DOT, and the zero point DAC 4 corrects the offset error VOe, so that the DU from the summing amplifier 6
The main signal applied to T 1 can match the range of DUT 1's actual input.

Furthermore, in the present invention, exactly half of the output of SAR12, which will be described later,
That is, the zero point DAC 4 is set so that the point of 8 LSB (8 steps) becomes the ideal change point of the DUT 1 (Voe 1 V).

. 8) is generated, and the point where the lower 4 bits of the conversion setting data DA applied to the main DAC 2 become 1000 is the ideal change point of the DUT 1.

Voltage of V 06 B: Voltage generated from main DAC2 when 8H of conversion setting data DA- is added to main 0^C2 In this way, the position of the ideal change point of 0101 is determined by the lower 4 bits of conversion setting data DA. Describe the reason for shifting to the point where
The voltage at the actual change point of DUT 1 is searched by SAR12, but the ideal change point of DUT 1 is located at the center of the search range by SAR12, that is, the center of 16 divisions, and ±8 steps from the ideal change point are searched. This is because it is a reasonable design.

This is a new configuration of the present invention, which will be explained below.

Reference numeral 7 denotes a CPU, which controls the apparatus shown in FIG. 1 by transmitting and receiving signals to and from each section via a data control bussler (hereinafter simply referred to as bussler).

Although the CPU 7 is also provided in the device of the prior application, the CPU 7 of the present application is
There is no need to set the conversion setting data DA to be added to the main DAC2.

11 is a programmable counter (hereinafter referred to as counter)
This outputs a digital signal DC having the same number of bits as the output bit number (N) of the DOT. Since various resolutions (number of output bits) of DUT 1 to be inspected by the apparatus shown in FIG. is sent from the CPU 7 via the bus router. To explain, for example, if the highest number of bits of 0UT1 that can be measured by the device shown in FIG. ).

In such a device, if the DUT i to be tested is a 6-bit one, the signal Sp
As a result, the counter 11 selects the bit output from IsB to the 6th bit and uses it as a signal DC.

Further, a data signal sF corresponding to the total number of steps of the DUT 1 is set from the CPU 7 via this bus router. Note that since the number of output bits of D[IT1 and the total number of steps are known in advance, the CPU can set the signals sP and sF prior to the test according to instructions from the operator of the apparatus. The counter 11 is connected to a switching circuit 15 to be described later.
Every time the clock is input, the contents set by the signal sF are subtracted and an N-bit signal DC is output.

12 is a successive approximation register (hereinafter referred to as SAR).
C, tSUCCESSIVE APρFIOX REG
ISTER) III) The content of M bits (hereinafter described as 4 bits) at the output change point of DOT 1 is determined by the binary search method.

To explain, 5AR12 is 113 of DOT 1.
B is further finely divided into 4 bits (resolution of 16 steps) to measure the linearity error. This SAR
12 sets 1" in order from the most significant bit of the 4-bit signal at this timing when the tarok signal is applied from the switching circuit 15, and if the signal SC from the comparator 14 to be described later is active, this most significant bit is set to 1". set the bit to '0'
Set it to °′ (set it to “1” if it is passive),
When the next clock is applied, the next most significant bit is “1”.
” is set and the values of all 4 bits are determined by the same motion. After applying 4 clonks in this way, the value of 4 bits is determined, and this value is sent to CP IJ via busra.
A determination method such as that read in No. 7 is known as a binary search method. This will be described later using FIG. 5. In addition, 5Alt 12 with such functions
is currently commercially available as an IC.

13 is a bit connection switch, which outputs the counter output DC (
N bits) and SAR12 output DS (M bits)
is introduced, and the conversion setting data DA ((N0M
) bit) to the main DAC2. The operation of the bit connection switch 13 will be explained with reference to FIG. As shown in FIG. 3(b), the bit connection switch 13 is
The 4 bits of the output D9 of the SAR 12 are arranged on the lower bit side, and the output DC of the counter 11 is arranged on the upper bit side. The counter shown in FIG. 3 has an output counting resolution of (8 x 2) bits, but is controlled by the above-mentioned signal sP to use only N bits (the upper two bits are 0). Introducing such signals DC and DS, the bit connection switch 13 sends the conversion setting data DA(N+4 >
Adding bits. That is, H3B of the output DC of the counter 11 is added to the 888 power of the main DAC 2. below,
Each bit of the signals DC and DS is sequentially applied to the main DAC2/\. When added in this way, no signal is added to the LSB of the main DAC 2 and the bits next to it (ie, the lower two bits). If the inputs of these 2 bits are left open, there is a risk that the main DAC 2' will malfunction due to noise, etc., so the bit connection switch 13 sets these 2 bits to the circuit common potential as shown in Figure 3. Connected.

The reason why there are 2 empty bits in the main DAC 2 in Fig. 3 is that, assuming the total number of input bits of the main DAC 2 H, the maximum number of bits of the counter 11 (N+2), and the number of bits of the 5AR12 M, H= (N+2) 10 A reasonable design would be to have a relationship of M. in this case,
Since the output of the counter 11 is set to N bits by the signal Sp, two bits remain.

Note that since FIG. 1 shows an example of the configuration of a device that can support DUT' 1 of various resolutions, this bit connection switch 13 is necessary.
If there is, the number of bits of the (N+M) bit signal input to the main DAC 2 will be constant, and there is no need to provide the bit connection switch 13.

14 is a comparator, and the output DC of the counter 11
(N bits) and output DD of DUT 1 (N bits)
and when the contents are different, a signal SC to that effect is sent.
It is output to AR12. Comparison 14 is
For example, an exclusive OR gate is provided, and the signal D is
The bit signals constituting C and DO are compared to see if they are different or the same.

15 is a switching circuit which records the clock signal applied from the clock generator 16 under the control of the CPU 7.
or to the counter 11. For example, S.A.
After adding 4 clocks to R12, add 1 clock to counter 1.
It operates to add to 1. With these 4 clocks, S^1 (
This is because the value of M bits (4 bits) in 12 is determined. Note that the clock signal applied to SAR 12 and counter 11 and the tarock signal applied to DOT 1 are synchronized, but normally (SAR 12° counter 11) →
Bit connection switch 13 → Main DAC 2 → FS-1)A
Since there is a delay time of the signal due to the circuit of C3 → summing amplifier 6, in order to match this delay time, delay circuit 1
A tarok signal is applied to DUT 1 via 7.

The operation of the apparatus shown in FIG. 1 configured as above will be explained.

(1) First, search for the zero point of DUT 1. Since this search for the zero point is only performed once at the beginning of the test, it is searched as follows using the binary search method using the software of the CPU 7 as in the previous application.

Main DAC2, FS, and DAC3 outputs are OV, and C
While observing the converted output data of the DOT 1, the P U 7 adds data from the CPU 7 to the zero point DAC 4 to generate a predicted voltage near the zero point of the DUT 1. DUTl
Since the standard value of DOT 1 is known in advance, the value of the zero point of 0 (1
(0) (see Figure 7).

(2) Next, perform a full scale search while maintaining the output of the zero point DAC 4 at the voltage searched at (+).

In this case, the output of the main DAC 2 is set to the rated output.

For example, if the main DAC 2 has an output of 0 to 10 V, it outputs 10 V. And as in the case of (+), C
Find the full scale point using the binary search method using the PU7 software. And FS-DAC3
maintains the current settings. This operation (2) is also performed only once at the beginning of the test, so it is not a burden to CPtJ 7.

(3) Next, find the ideal change point of DUT 1 and the main [] AC
The correlation with conversion setting data DA added to 2 is determined. In the present invention, the 4-bit SAR 12 is used to measure the error voltage between the ideal change point and the actual change point of the DUT 1. Therefore, the data < 1000) located at the center of the 4-bit SAR12 is set as the ideal change point of the old 111,
It is appropriate to take a measurement range of ±8 steps to measure the error voltage obtained from this. Therefore, the middle point of the 16 steps of SAR12, that is, the lower 4 of the conversion setting data DA.
Adjustment is made so that when the bit is 1000, it is the ideal changing point of []tlT1.

This adjustment adds 8H of data DA from the CPU 7 to the main AC2 via the bus 5 while maintaining the states (+) and (2) above. The main AC2 converts the 8th day of this data DA- into an analog signal Voo day, and further sends it to the DUT via the FS/DAC3 and the summing amplifier 6.
Add to 1. In this state, CPU 7 again resets the zero point DAC.
4, and input voltage VA such that the converted output data of DUT 1 changes from "H" to "IH" as shown in FIG.
(0) is generated from the zero point DAC4.

That is, a voltage of a lower level corresponding to 8H is applied to the DUT 1 than the main signal applied from the main DAC 2.

Note that this process is also performed by the CPU 7, but since it is a process that is performed only once before measurement, it does not place a burden on the CPU 7.

The above (1) to (3) are pre-processing, and FS・08C3
The zero point DAC 4 maintains the values set in (2) and (3).

(4) The CPU 7 selects [1lIT 1 output bit number (N
) is applied to the counter 11 so as to output the same number of bits (N). Then, the CPU 7 sets data corresponding to the total number of steps of DOT 1 to the counter 11 as a signal sF. In this case, I) the analog inputs applied to IIT 1 are tested sequentially from the full scale value of DUT 1 down towards zero;

(5) The switching circuit 1 is controlled by the control signal S1 from the CPU 7.
5 operates to apply a clock signal to the SAR 12 side.

(6) SAR12 is calculated based on the main [ ] at the actual change point of DOT 1 using the binary search method described below.
Determine the value of conversion setting data DA to be added to AC2. Binary search will be explained with reference to FIG.

FIG. 5 shows a scene in which the search progresses from the full scale point of DUT 1 and data is searched when the output data of DUT 1 changes from 7FH to 7EH.

The left axis in Figure 5 is the main DAC with a setting resolution of 12 bits.
11 of 80 from 7E8H of the conversion setting data DA of 2
The horizontal axis shows the 2418B steps up to the main DAC.
The converted analog output voltage vA of 2 is shown.

Here, the conversion output data of DUT 1 is from 7EH to 7Fl.
Conversion setting data D at the ideal change point for changing to
A (left axis) is <7F8H as described above. That is,
In the present invention, after adjusting the gain error Ge by preprocessing,
Since the point of DOT 1 and the 8th day of conversion setting data DA-〇 added to main DAC 2 are matched, DUT 1
If it has ideal linearity, then 1. of the conversion setting data DA. When the value is 4 bits or 1000 from S B,
The value of DUT 1 should change by one step. Therefore, the error from the ideal value can be measured by observing how many bits the output of DUT 1 changes from the lower four bits of the conversion setting data DA or the state of 1000.

In addition, in the device shown in Figure 1, the linearity error of DOT 1 is as follows:
It is assumed that the signal exists within 11.8B of this DUT 1 (the search range shown in FIG. 5). To explain, in Figure 1, the conversion output data 1188 of DUT 1 is divided into 16 by the conversion setting data DA added to the main [lAC2, and the voltage is within ±8 steps of this conversion setting data DA from the ideal change point of lllll71. It is assumed that there is a linearity error voltage at The reason for this is that DUT 1 that deviates from this range (that is, DUT 1 with an extremely large linearity error) has little commercial value and there is no need to measure the linearity error voltage. 'Therefore, even if the contents of 5AII 12 are changed from 0000 to 1111, the old I71
If there is no changing point, as explained in Figure 5, even if the conversion setting data DA is changed in the range of
If there is no actual change point of UT 1, the linearity error voltage cannot be measured, and the CPU 7 determines that the DOT is out of specification.

Binary-search in 5AII 12 relies on the following operations. The following description will be made assuming that the actual change point of DUT 1 is at the conversion setting data DA=7F 3 t+ as shown in FIG.

(a) If one tarok shot is added to SAR12 according to the above (5), SAR12 becomes H2S out of 4 pintos.
is set to 1, and the other bits are set to 000. That is, 5
AI112 makes its output 1000, therefore,
The conversion setting data DA added to the main DAC 2 uses the output cuff FH of the counter 11 as the upper bit, and the SAR12
Since the output 814 (-1000) is used as the lower bit, it becomes 7F8H. In this case, 7 F 3 u <
Since 7 F 8 ++, the output of DLIT 1 is 7FH, which is the same as the output cuff FH of the counter 11. Therefore, the output SC of the comparator 14 becomes active, and (0) II! in FIG. This means that an actual change point exists in the region of l. In this case, the SAR 12 sets its H2S to '0'.

(b) When the next clock signal is applied to the SAR 12, the SAR 12 outputs 0100 (=48). Therefore, the conversion setting data DA=7F4)1. In this case, since 7F3H<7F4H, the output of DOT 1 is 7F, and as before, the output of counter 11 is Fl.
is the same, so the output SC of the comparator 14 is active. This means that the actual change point exists in the region (d) in FIG. 5. In this case, SAR12
sets the second bit from H2S to “0”.

(C) When the next clock signal is applied to 5AI112, SAR1:1. t 0010 (= 2 u
) is output. Therefore, conversion setting data DA=7F2H
becomes. In this case, 7 F 3 u > 7 F 2
Since u, the output of DOT 1 is 7EH,
Since it is different from the output signal F of the counter 11, the output SC of the comparator 14 becomes passive. Therefore, (
We can see that there is no real change point in the region of ). In this case, 5Af112 sets the third bit to '1
“.

(d) When the next tarok signal is applied to SAR12, SAI? 12 outputs 0011 (=3 u). Therefore, data DA=7F3H. Fifth
In the diagram, the actual change points are 7F38 to 7F of main DAC2.
4H, the output of the DUT 1 becomes 7E11, which is different from the output of the counter 11, so the output SC of the comparator 14 becomes passive. In this case, SA
R12 sets the fourth bit to “1pa.” As a result,
SAR12 determines 4 bits to be 0011.

This SAR 12 data is read into the CPU 7 via the bus router, and the change point of DUT 1 is found to be 7 F 311.

As a result, the measured data of 7F3H is (-5LSB) lower than the ideal change point of 7F8H of DOT 1 (that is, there is an error of 5 steps), and this (-5LS8) is the linearity error.

As shown in equation (1), the error voltage corresponding to ILSB is (VA (1'5-1)-VA (0)) / (F
S 1 ), the CPU 7 can be expressed as S 1 ).
After reading the error IsB value from the output of AR12, the error voltage can be easily calculated.

After adding 4 clocks to R12 to S in this way, the CPU 7 switches the switching circuit 15 to apply one clock to the counter 11, and moves to the next H of 7E to H of 7F.

The above operations are repeated until the contents of the counter 11 become as follows, and the error ISB is measured for all steps of DOT.

[Effects of the present invention]

As described above, according to the present invention, the SAR 12, counter 11, and comparator 14 automatically detect the output change of DUT i, and transfer the error 13B between the ideal changing point and the actual changing point of DOT 1 to the CPU. Therefore, the CPU is freed from calculation operations that sequentially control the main DAC 2.

In other words, the load on the CPU 7 is reduced.

As a result, the CPU 7 no longer needs to perform the arithmetic processing that has been required up to now, so that the DOT measurement time can be relatively reduced (high-speed measurement can be performed).

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the AD converter testing device according to the present invention, FIG. 2 is a flowchart showing the operation of the device shown in FIG. 1, and FIG. 3 is a diagram showing the counter output and successive approximation register (SA
R) A diagram showing the relationship between the output and the input of the main [] AC, Figure 4 is an error explanation diagram of the DUT, Figure 5 is the main DAC3
6 is a block diagram of a conventional test device, FIG. 7 is an explanatory diagram of DOT test operation by the conventional device, and FIGS. 8 and 9 are diagrams showing the relationship between the human output signal and the output of DUT 1. It is a figure showing the composition of a prior application. 2... Main DAC, 11... Counter, 12...
・Successive approximation register (SAII), 14...
comparator. Figure 2 Figure 3 Figure 4 Irregularity (j2%oA) (7DH→7EH) (72H-)7FH Buff E++7F+-+J Figure 6 Figure 7

Claims (1)

[Claims] It has a function of higher resolution {(N+M) bits} than the N-bit AD converter to be tested (hereinafter referred to as DUT), and has a successive approximation register with the output D_C of the counter described later as the upper digit. means to introduce conversion setting data D_A with the output D_S as the lower digit, convert it into an analog main signal, and add a signal based on this main signal to the DUT, and the same number of bits as the output bit number (N) of the DUT. A comparator that compares the output D_C of this counter with the output D_D of the DUT and outputs a signal S_C to that effect when the contents are different, and each bit of the M-bit signal D_S. An AD converter testing device comprising: a successive approximation register that observes the comparator output S_C by changing the S_C, and determines all bit values of M bits at a DUT output change point using a so-called binary search method.