JPH0253288A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten read access time by providing first and second pre- amplifiers, and constituting them possible to perform a pipeline operation. CONSTITUTION:First selection means 30-1 to 30-4 function so that data on the data buses 28a and 28b of the pre-amplifier on the other side out of the first and second pre-amplifiers 31a, and 32b can be transmitted while the pre- amplifier on one side is operated based on first selection signals A1 and B1. Furthermore, second selection means 32-1 to 32-4 function so that the content of the pre-amplifier on which the data is held can be transmitted to a main amplifier 33 based on second selection signals A2 and B2. In such a way, it is possible to perform the pipeline operation and to shorten queue time at the time of starting the operation of the pre-amplifier due to the delay of a data transmission path.

Description

[Detailed Description of the Invention] <Industrial Application Fields> The present invention is directed to dynamic RAM (Random A
The present invention relates to a semiconductor storage device such as a serial access memory configured with a serial access memory (access+emory), and in particular to an access method for reading out data at high speed from a serial register having a parallel/serial conversion function.

(Prior art) Conventionally, technologies in this field include: ■ Nikkei Electronics, [362] (1985-2-11) Nikkei McGraw-Hill Publishing, original author Nagami, "320 lines x for field memory of TVs and VTRs" 700-column image-dedicated serial input/output dynamic memory JP, 219-23
9. (1) There were some that were recorded in Japanese Patent Application Laid-Open No. 62-99973. The configuration will be explained below using figures.

FIG. 2 is a diagram illustrating an example of the configuration of a conventional serial access type semiconductor memory device.

This serial access type semiconductor storage device is composed of a dynamic RAM, and includes a memory cell array 1 having a large number of memory cells and a differential amplification type sense amplifier. A row address decoder for decoding the addresses AO to AN is connected via the row address decoder. In the column direction of the memory cell array 1, a data register 6 consisting of an inverter is connected via a bit line 4 and a transfer gate 5 operated by an enable signal.
-0 to 6-N are connected. Furthermore, the data registers 6-0 to 6-N include an N channel M)S transistor (hereinafter referred to as NMO3) for data transfer.
Oa, 7-Ob to 7-Na.

7-Nb via the complementary first. Second data bus 8a
, 3b are connected. Each NMO37-Qa, 7-O
Address pointers 9-0 to 9-N for data register selection, which are shifted by a serial control clock signal φ, are connected to the gates of b to 7-Na and 7-Nb. These data registers 6-0 to 6-N
, NMO87-Oa, 7-Ob ~7-Na.

7-Nb and address pointers 9-0 to 9-N constitute a serial register for parallel/serial conversion.

1st. The second data buses 8a and 8b have drive signals @S1
A differential amplification type preamplifier 10 for auxiliary main amplifier operation operated by a main amplifier, a differential amplification type main amplifier 11 operated by a drive signal S2, and an output buffer 12 for serial output data transfer are connected.

Although not shown in FIG. 2, the first and second data buses 3a and 8b receive serial input data D1.
An input buffer etc. for inputting is also connected.

FIG. 3 is a data read timing chart of FIG. 2, and the read operation of FIG. 2 will be explained with reference to this diagram.

Row address decoder 3 selects a memory cell in the row direction of memory cell array 1, and the data of the memory cell in the row direction is stored in parallel through transfer gate 5 in data registers 6-0 to 6-N. Address pointers 9-0 to 9-N are controlled by clock signal φ, and when clock signal φ becomes “H”, for example, address pointer 9-(N-1> is selected and data register 6-(N- 1> content is NMO37-(N-1)a
, 7-(N-1)b to the first and second data buses 8a and 8b. 1st゜Second data bus 8
The data on a and 8b are differentially amplified by a preamplifier 10, roughly differentially amplified by a main amplifier 11, and then converted into serial output data DO by an output buffer 12 and output.

Note that in the write operation, after selecting the row direction of the memory cell array 1 by the row address decoder 3, serial input data Di is sent to the data buses sa, sb via an input buffer, etc.
Enter. Then, the data on the data buses 8a and 8b are NMO37-Oa, 7-Ob to 7-Na,
7-Nb to the data register 5, and the data in the data register 5 is transferred to the transfer games 1 to 1.
5 and bit line 4 in parallel to the row direction memory cells.

(Problems to be Solved by the Invention) However, with the apparatus having the above configuration, the following problems frequently occur.

Generally, a RAM requires a faster access time in a read operation than in a write operation. On the other hand, in the device shown in FIG. 2, for example, when reading an address (N-1>) using a clock signal
In the same cycle, address pointer 9- (N-1
), the amplification operation by the preamplifier 10, and the amplification operation by the main amplifier 11 are performed, or the read access time of the address (N-1) seen from the rising edge of the clock signal φ is delayed.

That is, since the data buses 8a and 8b are long lines, the load is heavy, that is, the capacitance component is large. Therefore, address pointer 9-(N-1) is set to NMO37-(
After turning on N-1>a and 7-(N-1)b,
The contents of data register 6-(N-1) are preamplifier 10
It takes a long time for the data to be transmitted. During this time, the preamplifier 10 must wait without operating, which slows down the read access time.

The present invention provides a semiconductor memory device that solves the problem of the prior art, which is the slow read access time.

(Means for Solving the Problems) In order to solve the above problems, the present invention inputs successive data from a memory cell array in parallel, and inputs it in the form of serial data to a complementary first . a serial register outputting to the second data bus; In a semiconductor memory device including a preamplifier that amplifies data on a second data bus, and a main amplifier that amplifies an output of the preamplifier, the preamplifier includes the first... The first and second preamplifiers each amplify the data on the second data bus. a second data bus and the first data bus; a first selection means for switching and connecting the input side of the second preamplifier using a first selection signal; A second selection means is provided for switching and connecting the output side of the second preamplifier and the input side of the main amplifier using a second selection signal.

(Function) According to the present invention, since the semiconductor memory device is configured as described above, the first selection means selects the first selection signal based on the first selection signal.
While one of the first and second preamplifiers is operating, it works to transmit data on the data bus to the other preamplifier. Roughly speaking, the second selection means operates to transmit the contents of the preamplifier in which data is held to the main amplifier based on the second selection signal.

This enables pipeline operation and reduces the waiting time for the preamplifier to start operating due to delays in the data transmission path. Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a block diagram of main parts of a serial access type semiconductor memory device showing an embodiment of the present invention.

This serial access type semiconductor memory device is composed of a dynamic RAM, and has a memory cell array 2 having a large number of memory cells and a differential amplification type sense amplifier.
1, and the memory cell array 21 has a word line 22.
A row address decoder 23 for selecting a row address is also connected via the row address decoder 23. The row address decoder 23 is a circuit that decodes row addresses or refresh addresses AO to AN output from an address generation circuit (not shown) and selects memory cells in the row direction through the word line 22. Furthermore, data registers 26-0 to 26-N are connected in the column direction of the memory cell array 21 via bit lines 24 and transfer gates 25, and the data registers 26-O to 26-N are connected to NMO327-Oa, 2
7-Ob to 27-Na and 27-Nb are connected to complementary first and second data buses 28a and 28b. The transfer gate 25 is a circuit that is turned on and off by the enable signal EN and receives and transfers data between the bit line 24 and the data registers 26-0 to 26-N.

Data registers 26-O to 26-N are registers configured with inverters and used to hold data. Zarani NM
O327-Oa, 27-Ob ~27-Na, 27-N
b is the data register 26-O to 26-N and the first .b. Second
The NMO 327-Oa is a switch that receives and transfers data between the data buses 28a and 28b of the NMO 327-Oa.

Address pointers 29-0 to 29-N are connected to the gates 27-Ob to 27-Na, 27-NM). The address pointers 29-O to 29-N are circuits that perform a shift operation in response to a serial control clock signal φ and determine which register from among the data registers 26-O to 26-N is selected. These data registers 26-0 to 26-N, NMO 327-Oa.

27-Ob to 27-Na, 27-Nb, and here address pointers 29-O to 29-N constitute a serial register for parallel/serial conversion.

Complementary first. a second data bus 28a;

28b is used because a differential amplification type sense amplifier is used.
8a through NMO 330-1 and 30-3 respectively. The input sides of the second Brian 731a and 31b are connected, and the second data bus 28bk[NMO33
0-2° through 30-4 respectively. The input sides of second preamplifiers 31a and 31b are connected.

The output side of the first preamplifier 31a or NMO332-1,
32-2 to the input side of the main amplifier 33, and the output side of the second preamplifier 31b is connected to the NMO3
It is connected to the input side of the main amplifier 330 via 32-3 and 32-4, and the output side of the main amplifier 33 is connected to the output buffer 34.

NMO330-1, 30-2 and 30-3°30-4 are
1st. Second data bus 28a.

28b and 1st. The input sides of the second preamplifiers 31a, 31b are connected to the input sides of the first selection signals A1. It has a function as a first selection means that switches and connects at B1. NMO332
-1, 32-2 and 32-3°32-4 are the first. Second preamplifier 31a.

The output side of 31b and the input side of main amplifier 33 are connected to the second
selection signal A2. It has a function as a second selection means that switches and connects at B2. 1st. 2nd preamplifier 3
1a and 31b are drive signals SA.

By SB, 1st. Second data bus 28a.

An amplifier that differentially amplifies the complementary signals on 28b,
A large data bus 28a with 8 components.

It has a function of amplifying the signal on 28b in advance and supplying it to the main amplifier 33. main amplifier 33
is an amplifier that differentially amplifies the output of the preamplifier 318, 31b using the drive signal $2, and an output buffer 734 is a circuit that sends out the complementary output of the main amplifier 33 as serial output data D○.

J3, although not shown in FIG. 1, for example, J3.
An input buffer for inputting serial input data Oi is also connected to the second data buses 28a and 28b.

FIG. 4 is a data read timing chart of FIG. 1, and the read operation of FIG. 1 will be explained with reference to this diagram.

When addresses AO-AN are supplied to the row address decoder 23, the row address decoder 23 outputs the addresses AO-AN.
is decoded and sent to the memory cell array 21 through the word line 22.
Select memory cells in the row direction. The memory cell data in the selected row direction is transferred to the bit line 24 and the transformer 71 gate 25 turned on by the enable signal EN.
Data registers 26-0 to 26-N in parallel via
is stored in The address pointers 29-0 to 2-N are controlled by the clock signal φ, and the clock signal φ is H1.
For example, if a read access is executed to address (N-1), the address pointer will move to the next Nth 2nd address pointer.
9-N is selected. When the address pointers 29-, N are selected, the contents of the data register 26-N are transferred to the first. NMO for transferring to the second data bus 28a, 28b
327-Na and 27-Nb are turned on, and the contents of the data register 26-N are passed through the NMO 327-Na and 27-Nb to the first. The data are transferred to the second data buses 28a, 28b. After that, in order to transfer it to the second preamplifier 31b, the selection signal B1 rises and the NMO330-3, 30-
Turn on 4 and turn on 1st. Second data bus 28a.

The data on 28b is sent to the preamplifier 31 by the drive signal 3B.
amplified by b. The amplified data is held by the preamplifier 31b.

When a read access is made to the address (N-1>), the output data Do must of course output the contents of the address (N-1), but the contents of this address (N-1> are determined by the clock signal φ (N -2) When an address is read accessed, it is stored in the first preamplifier 31a.In other words, the address voitor 29- (N=2>
is selected, NMO827-(N-1)a.

27-(N-1)b turns on and data register 26-
(The contents of N-2> are the first and second data buses 28a, 2
Transferred to 8b. The data on the data buses 28a and 28b are transferred to the NMO 830-, which is turned on by the selection signal A1.
1, 30-2 to the first preamplifier 31a,
There, it is held after being amplified by the drive signal SA.

The data stored in the first preamplifier 31a is transmitted by the clock signal φ (NMO 332-1゜32-2 turned on by the selection signal @A2 when accessing address N-1>
The signal is sent to the main amplifier 33 through.

This main amplifier 33 is operated by the drive signal S2, amplifies the output of the second preamplifier 31a, and sends it to the output buffer 34. The output buffer 34 outputs the output of the main amplifier 33 in the form of output data [)0.

Read access to the Nth address, etc. is performed in the same manner as above.

Note that in the write command or refresh operation, after selecting the row direction of the memory cell array 21 with the row address decoder 23, serial input data D1 is inputted to the data buses 2'8a and 28b via an input cover sofa or the like. . Then, the data on the data buses 28a and 2ab are NM
O327-Oa, 27-Ob ~27-Na, 27-N
The data in the data registers 26-O to 26-N are sequentially stored in the data registers 26-O to 26-N via the transfer gate 25 and the line 24 in parallel to the memory cells in the row direction. be included.

This embodiment has the following advantages.

Two first. 20th) 7') 731 a, 31
b is provided, so when reading a certain address, 1
In the previous read cycle, data registers 26-O to 2
By storing the contents of 6-N in one of the preamplifiers 31a or 31b, the read operation can actually be performed from amplification by the main amplifier 33, that is, a pipeline operation can be performed, so that the read access time can be increased. .

That is, for example, while the first preamplifier 31a is operating, it can be used as a waiting time for transmitting data to the second preamplifier 31b, making it possible to shorten the read access time.

Regarding the main amplifier 33, the preamplifiers 31a, 31
Since the wiring length with b is short, there is no need for waiting time. Therefore, one is sufficient.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of such modifications include the following.

(a) Any number of preamplifiers 31a and 31b may be used as long as they are 2@ or more. However, if the number is too large, the current consumption will only increase, and furthermore, the effect of shortening the waiting time will not be improved even if there are three or more, so two is preferable.

(b) Data registers 26-O to 26-N may be configured with circuits other than inverters, or NMO327-Oa, 2
7-Ob ~27-Na, 27-Nb as P channel MO
The address pointers 29-O to 29-N may be composed of S transistors or other switching elements, or may be composed of shift registers or the like.

(C) NMO830-1 to 30-4 as selection means
．． 32-1 to 32-4 may be configured with P-channel MOS transistors or other switching elements.

(d) The memory cell array 21 is divided into a plurality of blocks, and the corresponding transfer gates 25, serial registers, and data buses 28a are provided.

28b etc. may be provided, and data from the memory cell array of each block may be transmitted to the gate of each transfer gate. This makes it possible to further speed up read access time.

(e) Data writing configurations other than the above embodiments are also possible.

(f) FIG. 1 can be applied to other memories such as static RAM in addition to dynamic RAM.

(Effects of the Invention) As described above in detail, according to the present invention, the first and second preamplifiers are provided and configured to enable pipeline operation, so that one preamplifier is not operated. This time can be used as a waiting time for transmitting data to the other preamplifier, making it possible to shorten the read access time and expect faster access times.

[Brief explanation of the drawing]

1 is a block diagram of main parts of a semiconductor memory device showing an embodiment of the present invention, FIG. 2 is a block diagram of main parts of a conventional semiconductor memory device, FIG. 3 is a data read timing chart of FIG. 2, and FIG.
The figure is a data read timing chart of FIG. 1. 20... Memory cell array, 23...
Row address decoder, 25... Transfer gate, 26-O to 26-N... Data register, 27-Oa, 27-Ob to 27-Na, 27-N'
o・----NMO8, 28a, 2B'o------・1st. Second data bus, 29-0 to 29-N...
・Address pointer, 30-1~30-4.32-1~
32-N----NMO3, 31a, 31'
o-------1st ° 2nd preamplifier, 33...
...Main amplifier, -34...Output buffer.

Claims (1)

[Claims] Serial data inputting read data from a memory cell array in parallel and outputting it to complementary first and second data buses in the form of serial data; In a semiconductor storage device including a preamplifier that amplifies data on a data bus and a main amplifier that amplifies an output of the preamplifier, the preamplifier includes a main amplifier that amplifies data on the first and second data buses, respectively. 1 and a second preamplifier, the first and second data buses and the input sides of the first and second preamplifiers are switched and connected by a first selection signal.
and a second selection means for switching and connecting the output sides of the first and second preamplifiers and the input side of the main amplifier using a second selection signal. Device.