JPH0252908B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus that can be applied to document images and the like.

2. Description of the Related Art Conventionally, a method is known in which density information of a document is cut off using an appropriate threshold value in order to remove background noise from a reproduced image. This threshold value has been adjusted, for example, using a density adjustment dial of a copying machine.

In this case, there is a sufficient effect in binarizing and reproducing a good image, and good binarization can be expected. However, when the background level is high and the density difference between useful information and the background is small, good binarization cannot be performed. That is, when background noise is removed, there is a risk that useful information of the document may also be lost, and conversely, there are cases where noise cannot be removed sufficiently.

The present invention has been made in an attempt to eliminate the drawbacks of the prior art as described above, and provides an image processing device capable of high-quality image reproduction that can remove background noise without losing image information. be able to.

To achieve this objective, according to the invention:
a first binarization circuit that binarizes multivalued input image information with a predetermined threshold; and a second binarization circuit that binarizes the input image information with a threshold that is higher in density than the threshold. a binarization circuit; a pattern forming circuit that identifies and patterns image portions and non-image portions of an input image based on the output of the first binarization circuit; and an output of the second binarization circuit. a fusion processing circuit that forcibly changes a non-image portion adjacent to an image portion corresponding to the image portion into an image portion; and an AND condition for each output of the first binarization circuit, the pattern forming circuit, and the fusion processing circuit. and an AND processing circuit that takes .

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows each process according to an embodiment of the present invention. Each of the figures a to f actually appears as an electrical signal, but is visualized for ease of understanding.

First, according to the present invention, a document is read pixel by pixel using a scanner (not shown) or the like, and each pixel is quantized into a multi-value level, for example, 16 steps, via an AD converter or the like. The image quantized to this multi-value level is shown in Figure a, which includes document information 10 and background noise 1.
Also includes 1.

Figure b shows an image in which such an image is binarized by applying a threshold value that does not cause any document information to be lost. The background noise 11' is removed to some extent.

Based on the binary image (b in the same figure) or the input multivalued image (a) in the same figure, the character part and the interline part of the character information are distinguished, and the character part 12 is set to the black level, A pattern is formed in which the inter-line portions 13 correspond to the white level (FIG. 3(c)).

On the other hand, for the input multivalued image (a in the same figure), with a threshold value on the higher density side than the threshold value used in b in the same figure,
Perform binarization. At this time, the character information 14 itself is missing, resulting in what is called a skeletal image, but background noise 15 is significantly reduced.

Next, this skeleton image is subjected to a so-called fusion process in which pixels belonging to the non-image part adjacent to the image part are forcibly made black pixels, and the non-image part is changed to the image part (FIG. 4(f)). As a result, thicker character information 16 is obtained.

Finally, by applying the AND condition for each image in b, c, and f of the same figure, noise between lines can be removed and a desired image with character information 17 maintaining a predetermined quality can be obtained.

In the above description, the case where the image is a character image will be described, and it goes without saying that the present invention is most effective for this type of image.
However, it will be easily understood that the present invention is also effective when applied to other types of images that have similar patterns between text lines and lines, such as bar graphs.

Further, although each stage has been described as digital processing, it may be partially analog processing, for example, fusion processing may be analog processing, and pixel-by-pixel processing may not necessarily be required.

FIG. 2 shows a specific configuration for carrying out the above method. According to the same figure, the preprocessing circuit 3
0, binarization circuit 40, pattern creation circuit 50, 2
A valorization circuit 60, a fusion processing circuit 70, and an AND processing circuit 80 are shown.

The preprocessing circuit 30 converts the analog image signal S ₀ read by a scanner (not shown) or the like into digital image information S ₁ quantized into other values, such as the one shown in FIG. It can be configured as follows. That is, it has a maximum value detection circuit 31, an average value detection circuit 32, and an AD converter 33. The maximum value detection circuit 31 and the average value detection circuit 32 are analog detectors that detect the analog image signal S ₀ and the peak level and average level, respectively, and output detected level signals S ₀₁ and S ₀₂ , respectively.

The AD converter 33 takes the signals S ₀ , S ₀₁ , and S ₀₂ as input signals, and allocates the lowest value of the quantization level to the average level S ₀₂ at that point in time, and the maximum value to the peak level S ₀₁ at the same point in time, and outputs an analog image. The signal S ₀ is converted into a multivalued digital signal S ₁ .

The detection time constants of the peak level and average level can be arbitrarily selected according to the reading speed of the device and the processing unit. The maximum value and the average value may be detected.

The binarization circuit 40 binarizes the multivalued input image information _S1 using a predetermined threshold, and includes, for example, a comparator 41 and a memory 42 as shown in FIG. .

The comparator 41 receives input image information at a predetermined timing.
Compare S ₁ with threshold TH ₁ , and if the signal content is S ₁ TH ₁ regarding density, output 1 (black), and if S ₁ <
If TH is ₁ , a binary signal S ₂ ' is sent out which outputs 0 (white). Such signals S ₂ ' are temporarily stored in the memory 42 for the required number of pixels and sent to the next stage.

Note that the threshold value TH ₁ is set here as a value that can remove a certain amount of background noise without damaging character information.

The pattern creation circuit 50 divides the image portion and non-image portion of the input image based on the output signal _S2 of the binarization circuit 40.
That is, in a document image, character line portions and interline portions are identified and patterned. For example, a configuration as shown in FIG. 5 can be used.

This circuit 50 scans the image (corresponding to FIG. 1b) stored in the memory 42 of the binarization circuit 40 in the vertical and horizontal directions, and sets the density value of the pixels in each direction to "0" or "1". The projection pattern obtained from the integrated value is examined to determine the character line direction, and a binary pattern representing the character line part and the interline part of the image signal _S2 is created from one of the projection patterns.

In the figure, elements 51A to 56A on the left form a sequence for processing information in the vertical direction, and elements 51B to 56B on the right form a sequence for processing information in the horizontal direction.

That is, the accumulation circuit 51A integrates all the pixel densities of a specific vertical scanning line of the image information signal _S2 (f ₁ ), and the comparison circuit 52A compares this with a predetermined threshold value β to obtain a binary value. signal _g1 is sent. Threshold B should be set so that it is possible to judge whether the scanning line belongs to a character line or not, and should be selected so that the relative ratio of black pixels to white pixels is 1/50 to 1/10. desirable.

Such a binarized signal _g1 is stored in the pattern storage circuit 53A for a plurality of scanning lines (for example, three columns),
Based on the binary signals g ₁ ' for a plurality of scanning lines, the judgment logic circuit 54A judges whether or not the scanning line belongs to a character line in a binary manner (h ₁ ). By sequentially accumulating the binary signal _h1 indicating this determination result in the pattern storage circuit 55A, two
You can get value patterns.

Similarly, a horizontal binary pattern can be obtained with elements 51B to 55B.

Here, patterns h ₁ ' and h ₂ ' in the vertical and horizontal directions are taken out from the pattern storage circuits 55A and 55B, respectively, and accumulated by the accumulation circuits 56A and 56B, respectively. The integration results i ₁ and i ₂ are compared in a comparison circuit 57, and if i ₁ > i ₂ , it is assumed that there is a character line in the vertical direction, and J=1 is output, and if i ₁ i ₂ , there are characters in the horizontal direction. Assuming that there is a row, output J=0.

Based on this result, a signal _S3 indicating the pattern of the image portion and the non-image portion is formed via the pattern generation circuit 58 and the pattern storage circuit 59.

The binarization circuit 60 has the same configuration as the above-mentioned binarization circuit 40, but differs only in the threshold value. That is, 2
A threshold value is set on the higher density side than the threshold value of the value converting circuit 40, so that background noise can be removed to a considerable extent even if some character information is missing based on the image signal _S1 . A so-called skeleton image _S4 is formed.

The fusion processing circuit 70 converts pixels surrounding a black pixel portion of the output signal _S4 of the binarization processing circuit 60 into black pixels based on a predetermined rule.

The AND processing circuit 80 includes two binarization circuits 4
0, 60 and the output S ₂ of the pattern creation circuit 50,
The AND condition of S ₃ and S ₄ is taken, and the signal S ₆ obtained as a result forms the desired image.

By configuring this invention as described above,
It is possible to provide an image processing device that can remove background noise without missing image information and can reproduce high-quality images.

[Brief explanation of drawings]

FIG. 1 is a process diagram showing the principle of the invention, FIG. 2 is a system diagram of an embodiment of the invention, and FIGS. 3 to 5 are system diagrams of main parts of the embodiment of the invention. 30... preprocessing circuit, 40, 60... binarization circuit, 50... pattern creation circuit, 70... fusion processing circuit, 80... logical product processing circuit.

Claims (1)

[Claims] 1 Multivalued input image information with a predetermined threshold value 2
a first binarization circuit that converts the input image information into a value; a second binarization circuit that binarizes the input image information with a threshold value higher than the threshold value; and the first binarization circuit. a pattern forming circuit that identifies and patterns the image portion and non-image portion of the input image based on the output of the second binarization circuit; An image processing device comprising: a fusion processing circuit that changes an image portion into an image portion; and an AND processing circuit that takes an AND condition for each output of the first binarization circuit, the pattern forming circuit, and the fusion processing circuit. .