JPH025278A - Memory device - Google Patents

Abstract

PURPOSE:To decrease the number of input terminals for external address signals necessary for the random access by selecting the memory blocks according to the level change timing of the external control signal and then selecting the memory cell of the selected memory block based on an external address signal. CONSTITUTION:The selection means 20-22 select the actions of the desired memory blocks MB11-MBii according to the level change timings of external control signals SX and SY. Then the address signals ADRSr and ADRSc received from outside in time division are supplied in common to the blocks MB11-MBii via an internal address bus 15. Then the memory cell of a selected prescribed memory block can be selected 2-dimensionally by both signals ADRSr and ADRSc. Thus it is possible to perform the random access to a wafer scale memory 1 with reduction of the number of input terminals for external address signals compared with the memory capacity.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to addressing technology for a storage device with an extremely large storage capacity in which a plurality of memory blocks are arranged in a matrix, particularly addressing technology for random access. It relates to techniques that are effective when applied to memory.

[Prior art]

Wafer scale memory, which consists of multiple memory blocks formed on one wafer, has a large storage capacity, so
If the large address space is simply a linear address space and each memory block is mapped to a different address space so that a desired memory cell can be addressed, random access is possible, but the number of bits of the address signal is The number becomes extremely large.

Conventionally, as a technique for reducing the number of bits of an address signal required for addressing for a storage device including a plurality of memory blocks such as a wafer scale memory, there is, for example, British Publication No. GB2177825. The technology described in this document connects all memory blocks serially, and a control signal called a token moves serially from the first memory block to the last memory block in synchronization with a clock. . A chip selection signal is supplied in parallel to each memory block, and the chip selection signal is considered valid in the memory block receiving the control signal called the token. Each memory block has an address counter, and data corresponding to the output of this address counter is serially read out from the memory block selected by the chip. Such techniques make it possible to reduce the number of external signals for addressing storage devices with extremely large storage capacities.

[Problems to be Solved by the Invention] However, in the above-mentioned technique, the propagation time of the control signal, which is a token, varies depending on the serially coupled position of the memory block to be accessed, resulting in a large difference in access time.

In other words, a control signal called a token is serially moved from the first memory block to the last memory block in synchronization with the clock, so that the memory blocks connected relatively early in the serial sequence and the memory blocks connected later. Access times will be different for combined memory blocks. Moreover, as the number of memory blocks increases, it takes a proportionate amount of time for a control signal called a token to propagate to a desired memory block, slowing down the average access speed.Furthermore, random access is essentially impossible. It is considered possible.

An object of the present invention is to provide a storage device that has a relatively small number of address signal input terminals compared to its storage capacity, and that can be randomly accessed without any particular access time delay.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a plurality of memory blocks in which memory cells arranged in a matrix can be randomly accessed are arranged in a matrix, and an address signal supply means for commonly supplying an external address signal to each of the memory blocks, and a level of an external control signal are provided. A storage device such as a wafer scale memory is provided with a first selection means for forming a selection signal for selecting an operation of a desired memory block from among the plurality of memory blocks according to the change timing.

At this time, the first selection means includes a counter that resets the counting operation based on the level change of the external control signal, and a counter output immediately before being reset based on the level change of the external control signal. and second selection means for selecting an operation of the memory block according to the count value.

[For production]

According to the above-mentioned means, the first selection means selects the operation of a desired memory block according to the level change timing of the external control signal, and selects the memory cells in the selected memory block based on the external address signal. The operation works to reduce the number of external address signal input terminals required for random access to memory cells compared to the storage capacity, and also works to obtain the same access time for any memory block. do.

[Embodiment] FIG. 1 shows a wafer scale memory which is an embodiment of the present invention. The wafer scale memory 1 shown in the figure is formed on a single semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique.

In the wafer scale memory 1, i memory blocks M811 to MBii are formed horizontally and vertically.

Each of the above memory blocks MB, . . . ~MBii has the same configuration, for example, DRAM (dynamic
random access memory).

FIG. 2 typically shows the configuration of one memory block MB, □. This memory block MB,1 has a memory cell array 2 in which dynamic memory cells (not shown) are arranged in a matrix, and selection terminals of the dynamic memory cells are coupled to word lines 3 for each row. Furthermore, data input/output terminals of the dynamic memory cells are coupled to bit lines 4 for each column, and the bit lines 4 are commonly connected to a common data line 6 via a column selection circuit 5.

The word line 3 is coupled to the output terminal of a row address decoder and word driver 7, and the row address decoder and word driver 7 selects one word line corresponding to the output address signal of the row address buffer and address latch circuit 8. Drive to the level.

The column selection circuit 5 includes selection switch elements in one-to-one correspondence with each bit line pair, and the selection terminals of these selection switch elements are coupled to the output terminal of the column address decoder 9. The column address decoder 9 turns on the selection switch element corresponding to the output address signal of the column address buffer and address latch circuit 10, and makes the bit line coupled to this selection switch element conductive to the common data line 6. do.

A row address signal A D RS r is supplied to the row address buffer and address latch circuit 8 via an address multiplexer 11 .

A column address signal ADR8c is supplied to the column address buffer and address latch circuit 10 via an address multiplexer 11. The address multiplexer 11 supplies a row address signal ADR5r to the row address buffer and address latch circuit 8 in synchronization with the timing when the externally supplied row address strobe signal RAS1 is negated to low level, and also supplies the externally supplied row address signal ADR5r to the row address buffer and address latch circuit 8. Column address strobe signal CAS
Column address signal ADR8c is applied to column address buffer and address latch circuit 10 in synchronization with the timing when 1 is negated to low level.

Control signals such as the row address strobe signal RAS1 and the column address strobe signal CAS are supplied to the timing generator 12, and based on various internal control signals 13 output from the timing generator 12, address signal capture control by the address multiplexer 11, etc. will be held. The above row address strobe signal RAS is regarded as a selection signal for selecting the operation of memory block MB□1, and when it is asserted, various internal circuits of memory block MB are activated and can operate. controlled to a certain state. In particular, the input/output circuit 14 coupled to the common data line 6 is controlled to enable data input/output operations based on assertion of the column address strobe signal CAS1.

Although not shown, the timing generator 12 is also supplied with a control signal for instructing read/write operations.

Memory block MB configured as shown in FIG.
, 1 to MBii, address signals ADR8r and ADR8c given from the outside in a time-division manner are connected to the internal address bus 1.
Commonly supplied via 5.

In addition, the input/output circuits 14 of memory blocks MB to MBii are commonly connected to an internal data bus 16, and can be interfaced with the outside via a data input/output buffer 17.

In Fig. 1, 20 is the RAS generator, 21 is the CA
It is an S generator. The RAS generator 20 forms row address strobe signals RAS1 to RASi common to memory blocks in the same row, and the CAS generator 21 forms column address strobe signals CAS1 to CASi common to memory blocks in the same column.

The above RAS generator 20 and CAS generator 2
1 is supplied with the count output C0UNT of the counter 22 that counts the clock CLK, and the selection control signal S
X, SY are given. The count-up value of the counter 22 is at least i or more. Selection control signal sx, s
y is regarded as a signal for selecting and instructing a desired memory block from memory blocks M811 to MBii.

Although not particularly limited, the counter 22 may be configured to receive a selection control signal s.
In response to both x and sy being changed from low level to high level, the counting operation is reset and starts counting from 1, and when the selection control signal SY is set to high level, the other selection control is performed. The counting operation is also reset when the signal SX is changed from high level to low level and starts counting operation from 1.

The RAS generator 20 latches and decodes the count output C0UNT in response to the timing at which the 1 selection suppression signal Sx changes from high level to low level, thereby generating one row address according to the value of the count output C0UNT. Assert strobe signal. The asserted row address strobe signal is the selection control signal S.
It is negated in response to the timing when x changes from low level to high level.

The CAS generator 21 latches and decodes the count output C0UNT in response to the timing when the 5 selection suppression signal SY changes from high level to low level, thereby generating one column address according to the value of the count output C0UNT. Serve the strobe signal 7 times. The asserted column address strobe signal is negated in response to the timing at which the selection control signal SY changes from low level to high level.

FIG. 3 schematically shows a method of addressing a predetermined memory cell using selection control signals sx, sy and addresses (J No. ADRSr, ADR8c). For example, when selecting memory block MB!3, First, at the timing when the count output C0UNT becomes "2", the selection control signal Sx is negated, and the row address strobe signal R is
Assert AS. As a result, the row address signal ADR is applied to the second row of memory blocks MB, 1 to MB21.
5r is taken in 6 then count output C0UNT
At the timing when becomes "3", the selection control signal SY is negated and the column address strobe signal CAS3 is asserted. As a result, the third column memory block MB
Column address number ADR8c is taken in from 13 to MBi.

In this way, the row address strobe signal RAS and the column address strobe signal CAS are both asserted in the memory block MB.

operation is selected, and a predetermined memory cell in the memory block MB, 3 is accessed according to the row address signal ADR8r and column address signal ADR3c taken into the memory block MB, 3.

The timing chart in Figure 4 shows memory block MB3.
An example of an addressing operation when accessing a memory cell included in s is shown.

When the selection control signals sx and sy are both changed to high level at time t0, the counter 22 is reset and starts counting from "1". When the selection control signal Sx is changed to low level at time t1 when the count output C0UNT is set to "3", the RAS generator 20 takes in the count value "3" in response to this and generates the row address strobe signal in response. Assert RAS3. As a result, the row address signal ADR8r is taken into the memory blocks MB, 1 to MB, i arranged in the third row.

When the selection control signal Sx is changed to low level at time t1, the counter 22 is reset again and the counter 2
2 starts counting operation from "1". Count output C0
Select IIJ control signal S at time t2 when UNT is set to "5"
When Y is changed to low level, the CAS generator 21 takes in the count value "5" in response,
In response to this, a column address strobe signal CAS is asserted. As a result, the fifth column memory block MB3s takes in the column address signal ADR8r.
Therefore, the memory block MB in which both the row address strobe signal RAS and the column address strobe signal CAS are asserted.

5 is selected, and a predetermined memory cell in the memory block MB3s is accessed according to the row address signal ADR8r and column address signal ADRSc taken into the memory block MB3s.

When selection control signals SX and SY are both changed to high level at time t, row address strobe signal RAS and column address strobe signal CAS are negated, and the access operation is completed.

According to the above embodiment, the following effects can be obtained.

(1) Memory blocks MB11 to MBi are controlled by the output of the counter 22 controlled by two selection control signals SX and SY.
i is made two-dimensionally selectable and memory cells in one selected predetermined memory block are made two-dimensionally selectable by address signals ADR5r and ADR8c, thereby allowing random access to the wafer scale memory. This can be achieved by reducing the number of external address signal input terminals compared to the storage capacity. In particular, when comparing the number of external terminals of a DRAM corresponding to one memory block and the number of external terminals of the wafer scale memory 1 of this embodiment, only the number of input terminals for the clock CLK is increased, so the storage capacity is enormous. It is possible to completely suppress a significant increase in the number of external terminals, especially the address signal input terminals, of the wafer scale memory 1 having the above structure.

(2) The selection of memory blocks M81□ to MBii and the selection of memory cells within the selected memory block are both performed two-dimensionally, thereby reducing the difference (variation) in access time between memory blocks. be able to.

(3) One access operation selects a word line in one row of memory blocks, and the memory cells aligned on the same word line are effectively refreshed all at once, so the refresh operation The time required for this can be reduced.

Although the invention made by the present inventor has been specifically described above based on examples, it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof.

Although the above embodiment describes the case where a memory block is selected using a counter, the present invention is not limited thereto, and may be configured by providing shift registers on each of the RAS generator side and the CAS generator side. . That is, each serially coupled latch circuit is used as an address strobe signal generation source, and a bit "1" is sequentially propagated serially to the latch circuit in synchronization with a clock, and the output timing is transmitted through a gate controlled by a selection control signal. The configuration is such that an address strobe signal corresponding to the bit "1" is asserted to a desired memory block.

Further, in the above embodiment, the memory block is a DRAM, but the present invention is not limited thereto, and can also be configured with a static RAM.

In the above explanation, the invention made by the present inventor was mainly applied to wafer scale memory, which is the field of application that formed the background of the invention, but the present invention is not limited thereto, and can also be applied to memory boards, etc. Can be widely applied.

The present invention can be applied to a condition in which a plurality of memory blocks are arranged in a matrix, in which a desired memory cell can be selectively accessed from among the memory cells arranged in a matrix.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, since the first selection means selects the operation of a desired memory block according to the level change timing of the external control signal, and selects the memory cells in the selected memory block based on the external address signal, random access to the memory cells is possible. In addition, the number of input terminals for external address signals required can be reduced compared to the storage capacity.

This has the effect that the same access time can be obtained for any memory block.

By using the counting operation of a counter to select a memory block, the configuration for this purpose can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a wafer scale memory that is an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of the configuration of one memory block. FIG. 3 is a schematic diagram illustrating a method of addressing a predetermined memory cell using a selection control signal and an address signal, and FIG. 4 is an example of an addressing operation when accessing a memory cell included in a predetermined memory block. FIG. 1... Wafer scale memory, MB, 1 to MBii
...Memory block, 2...Memory cell array, 7
... row address decoder and word driver, 6.
...lower trellis buffer and address latch circuit,
5... Column selection circuit, 9... Column address decoder, 10... Column address buffer and address latch circuit, ADR8r... Row address signal, AD
R3c...Column address signal, 20...RAS generator, 21...CAS generator, 22...
・Counter, RAS1 to RASi... Row address strobe signal, CAS1 to CASi... Column address strobe signal, sx, sy... Selection control signal, C
LK...Clock. Figure 1 Figure 2 ME// A01? sc Figure A33 θ

Claims (1)

[Scope of Claims] 1. A memory device in which a plurality of memory blocks are arranged in a matrix in which a desired memory cell can be selectively accessed from memory cells arranged in a matrix, and an external address signal is transmitted to each of the above memory blocks. address signal supplying means for commonly supplying the address signal to the memory blocks; and a first selection for forming a selection signal for selecting the operation of a desired memory block from among the plurality of memory blocks according to the level change timing of the external control signal. 1. A storage device comprising: means. 2. The first selection means includes a counter that resets the counting operation based on the level change of the external control signal, and a counter that captures the counter output immediately before being reset based on the level change of the external control signal, and selects the captured counter. 2. The storage device according to claim 1, further comprising second selection means for selecting an operation of the memory block according to a numerical value.