JPH0251297B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (i) Description of the field to which the invention pertains The present invention relates to a logic array device, and more specifically, the present invention relates to a logic array device, and more specifically, it is possible to prevent defects such as short circuits or disconnections in input lines, product term lines, and output lines within the device. The present invention relates to a logic array device that outputs logical operation results correctly even if there exists a logic operation result.

(ii) Explanation of the prior art and its problems In recent years, logic integrated circuits have been made into regular circuit structures like memory integrated circuits, reducing layout (placement/wiring design) man-hours and streamlining modification/testing. Logical array device (hereinafter abbreviated as PLA) aimed at
is proposed.

The basic configuration of the PLA consists of an input circuit section 1, a front-stage array section 2, a rear-stage array section 3, and an output circuit section 4, as shown in FIG. Front array section 2 is AND
Alternatively, the rear array section 3 is a section that performs operations such as NOR logic, etc., and the rear array section 3 is a section that performs operations such as OR or NOR logic, and any logical function can be realized by this two-stage logic operation. Unless otherwise specified as a logical calculation expression, hereinafter, logic level "H" will be referred to as logic value "1",
An operation when applying positive logic in which the logic level "L" corresponds to the logic value "0" will be shown.

Figure 2 shows an example of a PLA in which the front array section 2 is an AND array and the rear array section 3 is an OR array. This is an example. In these configurations, input lines 10 ₁ to 10 ₆
If a short circuit defect or disconnection defect occurs in the product term lines 11 ₁ to 11 ₄ , or a short circuit defect or disconnection defect occurs in the output lines 12 ₁ to 12 ₃ , the outputs f ₁ to _{f 3} of the PLA will become abnormal. Become.

For example, in FIG. 2, the influence of the above defect on the logic value of the product term line or the output of PLA is shown as follows. When the input lines 10 ₂ and 10 ₃ are short-circuited at 100, depending on the configuration of the input circuit section 1, the logic levels of both 10 ₂ and 10 ₃ are “L” level, “H” level, or “H” level and “L” level. ``Degenerate to a level between levels. Therefore, the product term lines 11 ₂ , 11 ₃ , 11 connected to such input lines
The logic values AB, ABC, of ₄ are affected by this short circuit, and when the shorted input line degenerates to "L" level, they become "0", and when they degenerate to "H" level, they become A, AC, respectively. , "1", and when the level is intermediate, the value is the same as that at the "H" level or is unstable. When the input line ₁₀₂ is disconnected at 101, the input line on the opposite side of the input circuit section 1 across the disconnection point 101 becomes in a floating state. Therefore, the product term line 11 ₄ is always "1" or an unstable value. When the product term lines 11 ₃ and 11 ₄ are short-circuited at 102, the logic value ABC of 11 ₃ becomes erroneously set to ABC="0", and the logic value of 11 ₄ also becomes erroneously set to "0". When the product term line 11 ₂ is disconnected at 103, the product term line in the subsequent array section 3 becomes in a floating state. Output lines 12 ₂ and 12 ₃ are
104, the output f ₂ incorrectly changes +AB to +AB, and the output f ₃ incorrectly changes ABC to +AB.
If the output line 12 ₂ is disconnected at 105, the output f ₂ = AB
+ is "1" only when input A=0, otherwise it is in a floating state (unstable state) and its value is not determined.

In the configuration shown in FIG. 3, the influence of defects on the PLA output is partially different from that in FIG. 2, but if a defect exists, it is not possible to obtain the correct output as in FIG. 2.

In view of these circumstances, conventionally, after inputting a test pattern and testing the presence or absence of defects inside PLA,
Defects were repaired by selecting and using only good PLA, incorporating a test circuit to check for defects and a circuit to repair defects, and providing operating modes for testing and defect repair. Therefore,
As the scale of PLA increases, the manufacturing yield decreases, and in the latter case, it is necessary to provide additional operating modes for testing and defect relief, which has the disadvantage of complicating testing during manufacturing. Also,
There were drawbacks that resulted in lower reliability, such as malfunctions due to the occurrence of defective parts during normal PLA operation.

(iii) Purpose and general explanation of the invention The present invention has a PLA with a duplex configuration, and automatically degenerates defective states in each part to a logically safe side (fail-safe side). By outputting correct calculation results from the side, the aim is to improve the manufacturing yield of PLA and reduce the failure rate during PLA operation.

More specifically, the present invention has an array configuration consisting of a front-stage array section and a rear-stage array section, and an input circuit section.
As well as making one part A-based and the other B-based,
Add an input line level compensation circuit (NBF circuit) and an input line interconnection control circuit (IGC circuit) to the input line (or the IGC circuit can be omitted), and set the product term according to the array configuration type. A line level compensation transistor or a product term line level compensation resistor is added to the product term line in the subsequent array section, and a 1-bit decoder configured to degenerate to "L" level when the decoder output is short-circuited is used as a decoder in the input circuit section. It is used for the logical operation of the output from the A system and B system performed in the output circuit section.
Direct connection (wired) depending on array configuration type
By applying a logical operation (OR/AND logical operation) or an OR logic gate (gate OR logical operation), short-circuit defects in input lines, product term lines, and output lines can be fixed.
This is to relieve disconnection defects.

In the following explanation, unless otherwise specified, the case where positive logic is applied is shown. The array section will be named according to the arithmetic function of the array section in positive logic.

(iv) Description of Embodiment FIG. 4 is an embodiment of PLA according to the present invention.
This PLA includes input circuit sections 1 ₁ , 1 ₂ , front array section 2 ₁ ,
2 ₂ , rear array section 3 ₁ , 3 ₂ , output circuit section 4 , input line level compensation circuit (NBF circuit) 5 ₁ , 5 ₂ , input line interconnection control circuit (IGC circuit) 6; , the front array section, and the rear array section are duplicated. One of the duplexes is called the A system and the other is called the B system. In the following embodiments, the number of inputs of the PLA is limited to 2, the number of product terms is 3, and the number of outputs is 3. However, there is no particular restriction on these numbers. Also, a case where an n-channel MOS transistor is used will be explained. Note that when using a P-channel MOS transistor, the logic level "H" is changed to "L", and the logic level "L"
Replace “H” with NOR, NAND, AND
The ORs may be replaced with each other, and the polarity of the program element diode may be reversed.

The input circuit units 1 ₁ and 1 ₂ each include a plurality of 1-bit decoders (DEC circuits). 1 in Figure 5
An example of a bit decoder is shown. This 1-bit decoder is configured such that when two pairs of outputs 20 _i and 20 _i (referred to as pair outputs) are short-circuited, both outputs degenerate to the "L" level.

FIGS. 6 and 7 show embodiments of the front array sections 2 ₁ and 2 ₂ . The front array section outputs the output 2 of the input circuit section.
Outputs the input lines 10 _i , 10 _i , 10 i ₊₁ , 10 _i+1 connected to 0 _i , 20 _i , 20 _i+1 , 20 _i+1 respectively, and the logic operation results in the previous stage array section. Product term line 11
₁ , 11 ₂ , and 11 ₃ as required for logical operations. Figure 6 shows a NOR array configuration using an n-channel MOS transistor as the program element 21.
FIG. 7 shows an embodiment of an AND array configuration using a diode as the program element 22.

FIGS. 8 to 11 show examples of the rear array sections 3 ₁ and 3 ₂ . FIG. 8 and FIG. 9 show product term lines 11 ₁ , 11 ₂ , 11 ₃ that convey the output from the previous stage array section and output lines 12 ₁ , 12 ₂ , 12 that output the logical operation results.
₁₀ and 11 show an AND array configuration in which a diode is used as the program element 24. FIGS. In order to remedy the disconnection defect of the product term line, in _the configuration shown in FIG. Transistor for line level compensation (Q _LL transistor)
is connected to the far end side of each product term line from the previous array section. In addition, in the configurations shown in FIGS _. 9 and 11, the product term line level compensation resistor (R _G A resistor) is connected to the far end of each product term line from the previous array section. In the configuration shown in Figure 10, Q _LL is applied to the far end of each product term line from the front array section.
Connect a transistor or R _V resistor.

Figure 12 shows the input line level compensation circuit (NBF circuit)
This is an example of 5 ₁ and 5 ₂ . This connects the pair of outputs 20 _i and 20 _i of the 1-bit decoder (DEC circuit) to the inverter circuit 2 through the pair of input lines 10 _i and 10 _i , respectively.
5, 26, and the positive output _20i of the input A _i in the 1-bit decoder is input to the transistor Q ₁
and the input A _i in the 1-bit decoder
β of transistor Q ₂ whose input is supplementary output 20 _i
This is an unbalanced flip-flop circuit in which the outputs of the inverter circuits 25 and 26 are connected to the inputs of the other inverter circuits 26 and 25. When one of the pair of input lines 10 _i and 10 _i is disconnected, if the logic level of the other input line that is not disconnected is “L” level, this input line will
The NBF circuit operates and the disconnected input line is correctly set to the "H" logic level. On the other hand, when the logic level of the input line that is not disconnected is "H" level, the input line interconnection control circuit (IGC circuit) described below determines that the correct logic level of the input line of the other system is disconnected. Set to input line. Further, as will be described later, if another embodiment of the NBF circuit is used, a disconnection defect in one of the input lines of the pair can be completely repaired without using the IGC circuit. If both input wires of the pair are disconnected, transistor _Q1 and
By providing a difference in gain constant β in Q ₂ , the logic level of the input line connected to the output of the inverter circuit 25 including the transistor Q ₁ with a large β is temporarily set to “L” level, and the logic level of the other input lines is set to “L” level. The input line is set to "H" level, and the correct logic level of the input line of another system is set to this broken input line by the IGC circuit described below.

FIG. 13 shows an embodiment of an input line interconnection control circuit (IGC circuit) 6 consisting of a control circuit section 27 and a gate 28. The control circuit 27 performs a NOR logic operation on the logic levels of the pair of input lines of the A system and a NOR logic operation on the logic levels of the pair of input lines of the B system corresponding to this input line, and further calculates the results of these operations. of
A NOR logical operation is performed, and the gate 28 for connecting and disconnecting the input line of the A system and the input line of the B system is controlled based on the result of this operation. In the IGC circuit, the control circuit section 27 detects a short circuit between adjacent input lines and shuts off the gate 28, thereby preventing the short circuit defect in the input line from spreading to other systems. Furthermore, when both input lines of a pair are disconnected, or when one of the input lines of a pair is disconnected, this input line and the corresponding pair of input lines of the other system are connected by the gate 28 to prevent the disconnection. The logic level of the input line is set correctly.

Figure 14 shows product term line level compensation elements (Q _LL transistor, _RG resistor) and suitable for various array configurations.
Logical operation configuration of R _V resistor and output circuit section (direct connection,
This shows the types of OR logic gates and whether various defects can be repaired. The array configuration in the figure is A of the duplex array configuration of the present invention.
Indicates the type of array configuration of the system. As a specific example of the configuration of the front array section, the NOR array configuration is shown in Figure 6.
The AND array configuration is as shown in Figure 7,
In addition, as a specific configuration example of the rear array section, NOR
The array configuration is as shown in FIGS. 8 and 9, and the AND array configuration is as shown in FIGS. 10 and 11. Note that the inverter added between the front array section and the rear array section in the figure is an inverter added to each product term line that transmits the output of the front array section to the rear array section, and the logical value of the product term line (product term line) is means to negate the term value). Similarly, the inverter added to the output of the subsequent array section in the figure means that an inverter is added to each output line that transmits the output of the subsequent array section to the output circuit section, and the logical value of the output line is negated. .

Below, in FIG. 14, the NOR array
In the case of a NOR array configuration (i.e., the NOR array configuration shown in Figure 6 is in the front array section and the 8th array is in the rear array section).
When using the NOR array configuration shown in the figure) and when using an AND array-NOR array configuration (i.e., using the AND array configuration shown in Figure 7 in the front array section and the NOR array configuration shown in Figure 9 in the rear array section) ), we will explain how various defects that occur in each part of PLA can be repaired.

NOR array - NOR array configuration NOR array - In the case of NOR array configuration, A system,
Each output of the B system is subjected to a logical operation by the OR logic gate shown in FIG. 15 to generate the output of the PLA. In such a configuration, short circuit defects and disconnection defects in the input line, "L" level stack defects in the decoder output, product term line disconnection defects, and short circuit defects and disconnection defects in the output line can be repaired. Hereinafter, relief from these defects will be explained based on FIG. 16.

(a) Input line short-circuit defect repair A short-circuit in an input line includes a short-circuit 200 in a pair of input lines to which paired outputs from one decoder are respectively connected;
A short circuit 201 of adjacent input lines to which the outputs of different decoders are each connected is considered. The former is called a short-circuit to the input line, and the latter is called a short-circuit to the non-input line. If there is no defect, the product term values of the product term lines 11 ₁ , 11 ₂ , 11 ₃ are _{1 1} , B ₁ , A _{1 1} . Therefore A ₁ = A ₂ ,
From B ₁ = B ₂ , C ₁ = C ₂ , the input variables of system A are A ₁ , B ₁ ,
When expressed as C ₁ , the outputs f ₁ , f ₂ , f ₃ are _{1 1} +A _{1 1} ,
B ₁ , B ₁ A _{1 1} becomes. For example, when the input line short circuit 200 occurs in the A system, the input A ₁
Regardless of the logical value of , both input lines 10 _i and 10 _i become "L" level by the 1-bit decoder. Therefore, the product term lines 11 ₁ , 11 ₂ ,
The product term value of 11 ₃ is ₁ , B ₁ , ₁ , and the A system and B system
By the OR logic operation of the system, the output of the defective system A is logically included in the output of the non-defective system B,
As a result, the output f ₁ is ₁ + ₁ + _{2 2} + A _{2 2} =
_{2 2} + A _{2 2} , output f ₂ is ₁ + ₂ = ₂ , output f ₃ is
B ₁ + ₁ + ₂ + A _{2 2} = B ₂ + A _{2 2} , and the correct calculation result from the B system becomes the PLA output. Also,
If a non-pair input line short circuit 201 exists in the A system, ₁
= “0”, B ₁ = “1”, the input lines 10 _i and 10 _i+1 are both set to “L” level by the decoder of input A ₁ , and ₁ = “1”, B ₁ = When it is “0”,
By decoder of input B ₁ input lines 10 _i and 10 _i+1
Both become "L" level. Therefore, the product term values of the product term lines 11 ₁ , 11 ₂ , 11 ₃ are ₁ , B ₁ , ₁
, which is logically included in the output of system A, and the output f ₁
is ₁ + ₁ + _{2 2} + A _{2 2} = _{2 2} + A _{2 2} , output f ₂ is ₁ + ₂ = ₂ , output f ₃ is B ₁ + ₁ + ₂ + A ₂
C ₂ =B ₂ +A _{2 2} , and the correct calculation result from the B system becomes the PLA output. Non-pair input line short circuit 201
exists and the input is ₁ = B ₁ = “0”, or ₁ =
When B ₁ = "1", the outputs from the A system and the B system are the same, and the correct calculation result becomes the PLA output.

In this way, an input line short-circuit defect results in the same state as when a program element in the previous stage array section is missing due to "L" level degeneration of the 1-bit decoder output, and therefore, the NOR including the missing product term The output of the system subjected to logical operations and the output of the system without defects
The correct output can be obtained by OR logic operation. On the other hand, in the IGC circuit shown in Fig. 13, which is used to repair a disconnection of a pair of input lines, which will be explained in detail later, the
By setting both the two inputs of the IGC circuit to “L” level, the IGC circuit performs a logical operation,
By prohibiting the connection of the input lines of the A system and B system, such defects are prevented from spreading to other systems.

(b) Remedy for disconnection defects in input lines Disconnection defects in input lines include cases in which one of the input lines of a pair connected to the pair of outputs of a 1-bit decoder is disconnected, and cases in which both are disconnected. In FIG. 16, when one of the input lines in the pair is disconnected, such as input line disconnections 202 and 203, the NBF circuit shown in FIG. 12 operates depending on the logic level of the other input line that is not disconnected. Then, the logic level of the disconnected input line is correctly set from the floating state to the logic level of the complement of the logic level of the input line that is not disconnected. Further, in order to repair a case where both of a pair of input lines are disconnected, such as input line disconnections 204 and 205, the IGC circuit shown in FIG. 13 is used. In other words, when both input lines of a pair are disconnected, the NBF circuit automatically outputs one at "H" level and the other at "L" level, regardless of the logic level of the output of the 1-bit decoder. In response to these outputs, the IGC circuit operates, connects the corresponding input lines of the A system and B system with the gate 28, and correctly sets the logic level of the input line with the disconnection. Further IGC
Even if one of the input wires in a pair is disconnected, the circuit connects the input wires of system A and system B to each other in the same way as above, and connects the input wires of system A and system B.
To correctly set the logic level of an input line by helping to repair a disconnection defect caused by a circuit.

(c) Remedy for product term line breakage defects In order to prevent the product term line from floating due to breakage (for example, 206), the product term line is held at the "H" level by the _QLL transistor, and the output line connected to the product term line in the subsequent array section by the program element is degenerated to the "L" level.
Therefore, by duplication, the output of system A and system B can be reduced.
Correct PLA by performing OR logical operation
You can get the output.

(d) Remedy for output line short-circuit defects When an output line is short-circuited, the logic value of the short-circuited output line is equivalently the negation of the wired OR logic of the respective logic values of the short-circuited output lines. For example, in FIG. 16, when the output line short circuit 207 occurs, the output lines 12 ₁ , 12 ₂
The logical values of are respectively _{1 1} +A _{1 1} to _{1 1} +A _{1 2}
+B ₁ , ₁ becomes _{1 1} +A _{1 1} +B ₁ . However, by calculating the outputs of the A and B systems using the OR logic gate shown in Figure 15, the logical set of the defective outputs of the A system is included in the logical set of the non-defective outputs of the B system. correct PLA
I get the output.

(e) Remedy for output line disconnection defects When the output line is disconnected, the output line becomes a floating state when the logic level of the product term line connected to the output line by the program element is at the "L" level.
In this case, an output line connection ground resistor ( _RO resistor) with a resistance value sufficiently larger than the ON resistance of the output line load transistor (Q _LO transistor) is connected to the OR logic gate input section as shown in Figure 15. By adding this, the output line degenerates to "L" level, and correct PLA is established by OR logical operation with the system without defects.
I get the output.

In addition, instead of the OR logic gate shown in FIG. 15, as shown in FIG. 17, an output line gate (GTO gate) 29 is added to the output lines of the A system and B system,
The above defects a, c, d, and e can also be relieved by an output circuit configured by directly connecting these outputs and adding an R _O resistor to this connection point.

AND array-NOR array configuration In the case of AND array-NOR array configuration, A
The outputs of the system and B system are directly connected (wired OR logical operation) to generate the PLA output. In such a configuration, short circuit defects and disconnection defects in the input line, "L" level stack defects in the decoder output, product term line short circuit defects and disconnection defects, and disconnection defects in the output line can be repaired. Hereinafter, relief from these defects will be explained based on FIG. 18.

(a) Input line short-circuit defect relief When an input line is short-circuited, regardless of whether the input line is short-circuited or the non-input line is short-circuited, the 1-bit decoder shown in Fig. “L”
become the level. This is equivalent to a missing program element on the output line in the subsequent array section, and by directly connecting the output line of system A and the output line of system B (wired OR logical operation), such a defect can be removed from system B. Rescued by correct output.

(b) Input line disconnection defect relief If the input line is disconnected, the NOR array described above
Just as in the case of the NOR array configuration, relief is achieved by the operations of the NBF circuit shown in FIG. 12 and the IGC circuit shown in FIG. 13.

(c) Remedy for short-circuit defects in product term lines When product term lines are short-circuited, the logical value of each short-circuited product term line becomes the product of their respective logical values. In FIG. 18, for example, if the product term lines 11 ₂ and 11 ₃ are short-circuited at 210, the product term value of each product term line will change from B ₁ to A _1
1 B ₁ , A _{1 1} becomes A _{1 1} B ₁ . However, the logical set (A _{1 1} B ₁ ) of the above product term lines 11 ₂ and 11 ₃ is
The corresponding product term line 11' ₂ , 1 of the other defect-free system
Such defects can be repaired by integrating the output lines into logical sets (B ₂ ) and (A _{2 2} ) of 1' ₃ and directly connecting the output lines of the A system and B system in the subsequent array section. Expressing the above as a logical formula, A ₁ = A ₂ , B ₁ =
From B ₂ , C ₁ = C ₂ , the output f ₁ is ( _{1 1} + A _{1 1} B ₁ ) +
( _{2 2} + A _{2 2} ) = _{2 2} + A _{2 2} , the output f ₂ is (A ₁
C ₁ B ₁ ) + B ₂ = B ₂ , the output f ₃ is (A _{1 1} B ₁ + A _{1 1} B ₁ )
+(B ₂ +A _{2 2} )=B ₂ +A _{2 2} .

(d) Remedy for product term line disconnection defects In order to prevent the product term line from floating due to disconnection, the product term line is connected to an R _G resistor as shown in Figure 18. Therefore, it is held at the "L" level, and the state is logically the same as the absence of a program element connected to such a product term line in the subsequent array section. Therefore, A due to duplication
Correct PLA output can be obtained by directly connecting the output lines of the system and B system (wired OR logical operation).

(e) Remedy for output line disconnection defects When the output line is disconnected, the product term line is connected to the output line from the output line load transistor (Q _LO transistor) to the disconnection point via the program element in Figure 18. Even if it is, such program element becomes irrelevant to the output. This is equivalent to the above program element being missing. on the other hand,
For the program element located between the disconnection point and the output point of the subsequent array section, the output line load transistor ( _QLO
transistor) to perform the correct NOR logic operation. Therefore, correct PLA output is obtained.

(v) Explanation of a modification of the embodiment The NBF circuit, as shown in _FIG.
In order to reliably set the output level of the NBF circuit after applying V D, a transistor 31 is provided, and after applying V _D ,
A configuration may be adopted in which another power source _V'D is applied with a slight delay. In addition, as shown in FIG. 20, by setting the clock φ to the "H" level immediately after applying the power supply V _D , the output of the NBF circuit and the input line connected to it are temporarily " It may be configured to be set at L'' level. Furthermore, as shown in FIG. 21, only the output of the NBF circuit may be temporarily set to the "L" level by the clock φ.

In addition, in the NBF circuit of FIG. 20, in addition to the above embodiment in which the clock φ is set to "H" level only once immediately after power is applied, the clock φ is set as an input variable.
Synchronize with the application time of PLA of A _i to "H" level, reset the output and input line of the NBF circuit to "L" level, apply input variable A _i , and set NBF to "H" level.
The clock φ may be set to operate the circuit and perform the calculation operation of the PLA. By this,
Even without using an IGC circuit, a disconnection defect in one of the paired input lines can be completely repaired.

In addition, in the above embodiment, the product term line load resistor (R _V resistor) is made conductive only during PLA operation,
It may be replaced by a product term line load transistor that is non-conductive during standby.

(vi) Explanation of Effects As explained above, the present invention provides PLA input lines,
Even if there is a short-circuit defect or open-circuit defect in the product term line or output line, the logic level of the output from the system containing the defect can be reduced to the fail-safe side without the need for a special test or operation period for defect relief. It can be set equivalently to a state in which the program element in the subsequent array section is missing, and the output of the correct system among the outputs of the duplicated system is automatically output. Therefore, with the PLA of the present invention, it is only necessary to perform input/output logic tests such as whether the program element is operating correctly during manufacturing, and a significant improvement in manufacturing yield is expected, making it possible to realize large-scale PLA. Become.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the basic configuration of a conventional PLA, Figure 2 is a diagram showing a specific PLA configuration example of an AND array-OR array configuration, and Figure 3 is a diagram showing a specific example of a NOR array-NOR array configuration. FIG. 3 is a diagram showing an example of a PLA configuration. FIG. 4 is a block diagram showing one embodiment of the PLA according to the present invention. FIG. 5 is a diagram showing an embodiment of a 1-bit decoder, FIG. 6 is a diagram showing an embodiment of the front-stage array section having a NOR array configuration, and FIG. 7 is a diagram showing an embodiment of the front-stage array section having an AND array configuration. Figures showing examples, Figures 8 and 9 are NOR
FIGS. 10 and 11 are diagrams showing an embodiment of a rear array section having an array configuration. FIGS. 10 and 11 are diagrams showing an embodiment of a rear array section having an AND array configuration. 1st
FIG. 2 is a diagram showing one embodiment of the input line level compensation circuit, and FIG. 13 is a diagram showing one embodiment of the input line interconnection control circuit. FIG. 14 is a diagram showing the types of logic operation configurations of the product term line level compensating element and output circuit section suitable for various array configurations, and whether or not various defects can be repaired. Figure 15 is a diagram showing an OR logic gate as an example of the output circuit section, and Figure 16 is a diagram showing a NOR logic gate.
FIG. 17 is a diagram showing another embodiment of the output circuit section, and FIG. 18 is an explanatory diagram of defect relief in the AND array-NOR array configuration. Figure 19, 2nd
0 and 21 are diagrams showing other embodiments of the input line level compensation circuit. 1, _{1 1} , 1 ₂ ... input circuit section, 2, 2 ₁ , 2 ₂ ...
...Pre-stage array section, 3, _{3 1} , 3 ₂ ... Rear-stage array section, 4 ... Output circuit section, 5, _{5 1} , 5 ₂ ... Input line level compensation circuit, 6 ... Input line interconnection control circuit, 10 ₁ to 10 ₆ , 10 _i , 10 _i , 10 _i+1 , 10 _i+
1 , 10 _i+2 , 10 _i+2 ... input line, 11 ₁ to 11 ₄ ,
11' ₁ to 11' ₃ ...product term line, 12 ₁ to 12 ₃ , 1
2' ₁ ~12' ₃ , 12n, 12'n...Output line, 2
0 _i , 20 _i ...output of 1-bit decoder, 21,
22, 23, 24...program element, 25, 2
6... Inverter circuit, 27... Control circuit section, 2
8...Gate, 29...Gate, 30...Output line grounding resistor, 31...Transistor.

Claims (1)

[Scope of Claims] An input circuit section comprising a plurality of 1-bit decoders that both output a "L" level or "H" level when a pair of outputs are short-circuited, and a plurality of inputs that transmit the output of the input circuit section. a pre-stage array unit that connects a program element to the line and the plurality of product term lines, performs a first logical operation on the logic level on the input line, and outputs the operation result to the next stage through the product term line; , connecting a program element to the product term line and the plurality of output lines;
In the logic array device, the input circuit section comprises a second array section that performs a second logic operation on the operation result of the front array section on the product term line and outputs the operation result to the output line. , each section of the front-stage array section and the rear-stage array section is duplicated, and the output of the 1-bit decoder is connected to one end of the input line across the input line of each front-stage array section, and the input line is connected to the other end. A line level compensation circuit is provided, and a product term line level compensation element is provided on the far end side from the previous array section for the product term line of each subsequent array section, and the output line from each subsequent array section is directly connected. Or a logic array device characterized by inputting to an OR logic gate. 2. An input circuit section consisting of a plurality of 1-bit decoders that both output a "L" level or "H" level when a pair of outputs are short-circuited, a plurality of input lines that convey the output of the input circuit section, and a plurality of product terms. a pre-stage array section that connects a program element to the line, performs a first logical operation on the logic level on the input line, and outputs the operation result to the next stage using the product term line; Connect the program element to multiple output lines,
In the logic array device, the input circuit section comprises a second array section that performs a second logic operation on the operation result of the rear array section on the product term line and outputs the operation result to the output line. , each section of the front-stage array section and the rear-stage array section is duplicated, and the output of the 1-bit decoder is connected to one end of the input line across the input line of each front-stage array section, and the input line is connected to the other end. A line level compensation circuit is provided, and for the pair of input lines connected to the pair of outputs of the 1-bit decoder, each corresponding input line of the duplexed array section is gated (hereinafter referred to as input line connection gate). )
and input the corresponding pair of input lines of each duplicated front array section to the OR logic gate,
It has an input line interconnection control circuit configured to input the output of each of the OR logic gates to an AND logic gate, and control conduction/cutoff of the input line connection gate by the output of the AND logic gate. The product term line of the array section is provided with a product term line level compensation element on the far end side from the preceding array section, and the output lines from each subsequent array section are directly connected or input to an OR logic gate. logical array device.