JPH025099U - - Google Patents

Info

Publication number
JPH025099U
JPH025099U JP8283788U JP8283788U JPH025099U JP H025099 U JPH025099 U JP H025099U JP 8283788 U JP8283788 U JP 8283788U JP 8283788 U JP8283788 U JP 8283788U JP H025099 U JPH025099 U JP H025099U
Authority
JP
Japan
Prior art keywords
memory means
operating time
target devices
adder
timer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8283788U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8283788U priority Critical patent/JPH025099U/ja
Publication of JPH025099U publication Critical patent/JPH025099U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Measurement Of Unknown Time Intervals (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例によるタイマー回
路を示すブロツク図、第2図は従来のタイマー回
路を示すブロツク図である。 図において、1は電気または機械機器の動作信
号、2はカウンタ、3は上記電気または機械機器
の機器番号、4は加算器、5はメモリ手段、6は
表示器。なお、図中同一符号は同一又は相当部分
を示す。
FIG. 1 is a block diagram showing a timer circuit according to an embodiment of this invention, and FIG. 2 is a block diagram showing a conventional timer circuit. In the figure, 1 is an operation signal of the electrical or mechanical equipment, 2 is a counter, 3 is the equipment number of the electrical or mechanical equipment, 4 is an adder, 5 is a memory means, and 6 is a display. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] メモリ手段と加算器とを備え、上記メモリ手段
に複数個の対象機器の各個の動作時間を記憶させ
ることによつて、上記複数個の対象機器の各個の
累積動作時間を表示できるようにしたタイマー装
置。
A timer comprising a memory means and an adder, and capable of displaying the cumulative operating time of each of the plurality of target devices by storing the operating time of each of the plurality of target devices in the memory means. Device.
JP8283788U 1988-06-21 1988-06-21 Pending JPH025099U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8283788U JPH025099U (en) 1988-06-21 1988-06-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8283788U JPH025099U (en) 1988-06-21 1988-06-21

Publications (1)

Publication Number Publication Date
JPH025099U true JPH025099U (en) 1990-01-12

Family

ID=31307578

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8283788U Pending JPH025099U (en) 1988-06-21 1988-06-21

Country Status (1)

Country Link
JP (1) JPH025099U (en)

Similar Documents

Publication Publication Date Title
JPH025099U (en)
JPS61185980U (en)
JPS61118091U (en)
JPS61206944U (en)
JPS62163797U (en)
JPS6257884U (en)
JPS6421529U (en)
JPH01104596U (en)
JPS62115400U (en)
JPS6399296U (en)
JPS6142597U (en) Rhythm pattern display device
JPH01173833U (en)
JPS6425786U (en)
JPS61131255U (en)
JPS5886687U (en) display device
JPH0365199U (en)
JPS6448693U (en)
JPS63143949U (en)
JPS61178498U (en)
JPS6281136U (en)
JPS60189892U (en) alarm clock
JPS5868624U (en) function selection device
JPS6059995U (en) Electronic timer device with display
JPS59134094U (en) alarm clock
JPS59187789U (en) time management device