JPH0250701U - - Google Patents
Info
- Publication number
- JPH0250701U JPH0250701U JP12948088U JP12948088U JPH0250701U JP H0250701 U JPH0250701 U JP H0250701U JP 12948088 U JP12948088 U JP 12948088U JP 12948088 U JP12948088 U JP 12948088U JP H0250701 U JPH0250701 U JP H0250701U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- analog input
- process signal
- switches
- inputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 238000002955 isolation Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Control By Computers (AREA)
- Analogue/Digital Conversion (AREA)
Description
第１図はこの考案の一実施例によるデイジタル
制御装置を示すブロツク図、第２図はそのアナロ
グ入力装置の詳細を示すブロツク図、第３図はそ
のオンライン時の校正処理の流れを示すフローチ
ヤート、第４図、第５図は従来のデイジタル制御
装置の一例を示すブロツク図である。
１はアナログ入力装置、１Ａ，１Ａ′はアナロ
グ入力回路、１Ｂ，１Ｂ′は増幅回路、１Ｃ，１
Ｃ′はＡ／Ｄ変換回路、１Ｄ，１Ｄ′は基準信号
発生回路、２はＣＰＵ、３はＲＯＭ、４はＲＡＭ
、５はデイジタル出力装置、６はデイジタル入力
装置である。なお、図中、同一符号は同一、又は
相当部分を示す。
Fig. 1 is a block diagram showing a digital control device according to an embodiment of this invention, Fig. 2 is a block diagram showing details of its analog input device, and Fig. 3 is a flowchart showing the flow of the online calibration process. , 4 and 5 are block diagrams showing an example of a conventional digital control device. 1 is an analog input device, 1A, 1A' are analog input circuits, 1B, 1B' are amplifier circuits, 1C, 1
C' is an A/D conversion circuit, 1D and 1D' are reference signal generation circuits, 2 is a CPU, 3 is a ROM, and 4 is a RAM
, 5 is a digital output device, and 6 is a digital input device. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
生し、前記プロセス信号毎に少なくとも１つ以上
設けられている基準信号発生回路を設け、前記プ
ロセス信号のアイソレーシヨンおよび信号変換を
行なう複数のアナログ入力装置と、前記アナログ
入力装置の内指定されたアナログ入力装置の入口
にて、そのアナログ入力信号を前記少なくとも１
つ以上の基準信号の１つに切換えるデイジタル出
力装置と、上記指定されたアナログ入力装置から
入力されていたプロセス信号を他のアナログ入力
装置に切換えて入力する中央処理装置とを備えた
デイジタル制御装置。 A plurality of analog inputs that generate a reference signal adjusted for each process signal, provide at least one reference signal generation circuit for each process signal, and perform isolation and signal conversion of the process signal. the analog input signal from the at least one of the analog input devices at the inlet of the device;
A digital control device that includes a digital output device that switches to one of two or more reference signals, and a central processing device that switches and inputs the process signal input from the specified analog input device to another analog input device. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12948088U JPH0250701U (en) | 1988-09-30 | 1988-09-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12948088U JPH0250701U (en) | 1988-09-30 | 1988-09-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0250701U true JPH0250701U (en) | 1990-04-10 |
Family
ID=31383795
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12948088U Pending JPH0250701U (en) | 1988-09-30 | 1988-09-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0250701U (en) |
-
1988
- 1988-09-30 JP JP12948088U patent/JPH0250701U/ja active Pending