JPH0250583A - Camera system - Google Patents

Abstract

PURPOSE:To obtain an excellent signal processing with a simple circuit without using an extra signal line by extracting a waveform based on prescribed timing included in an output signal from a CCD, and obtaining the timing for sample- and-hold, etc., on a camera control unit side. CONSTITUTION:A signal from a CCD image pickup element 32 is fetched, and transmitted to a camera control unit 1. Simultaneously, the camera control unit 1 extracts (peak clamping circuit 15 to waveform shaping circuit 17) the waveform based on the prescribed timing in the transmitted signal, shapes the extracted waveform, and forms the timing signal at least corresponding to the waveform based on the image pickup in the signals from the CCD. Consequently, the waveform based on the prescribed timing included in the output signal from the CCD is extracted, and the timing for the sample-and-hold, etc., is obtained on the camera control unit side. Thus, without using the extra signal line, the excellent signal processing with the simple constitution is attained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a camera control unit and a camera control unit.
The present invention relates to a camera system with a separate head unit.

[Summary of the invention]

The present invention relates to a camera system, and by extracting a waveform based on a predetermined timing from an imaged signal transmitted to a camera head unit and a color camera control unit, the present invention can eliminate the need for using extra signal lines. This allows good signal processing to be performed with a simple configuration.

[Conventional technology]

For example, a camera head unit (CHU) that takes images
There is a camera system in which a camera control unit (CCU), which processes a captured signal, and a camera control unit (CCU) are separated. In such camera stems, conventionally CH
A synchronization signal generation circuit is provided in each of U and CCU,
The synchronization signal from this synchronization signal generation circuit controls internal circuits such as formation and processing of each video signal.

Therefore, when using such a camera system, it is necessary to synchronize the synchronization signal generating circuits. That is, in order to process the video signal formed by the CHU in the CCU, the phase of the video signal transmitted from the CHU to the CCU needs to match the synchronization signal of the CCU.

Therefore, for example, a device as shown in FIG. 4 can be considered. The figure shows the entire camera system.
The control unit (CCL) (1) and the camera head unit (CHU) (2) are shown on the left side, and these are connected via a so-called multi-core cable (3).

This CCU (1) is provided with a first synchronization signal generation circuit (52) driven by a reference oscillator (51),
Vertical synchronization signal (pulse) V from this generation circuit (52)
D is transmitted to the second synchronizing signal generating circuit (54) through the reset signal generating circuit (53). Also, the generation circuit (5
The horizontal synchronizing signal (pulse) HD from 2) is supplied to the variable oscillator (56) through the phase comparison circuit (55).
This oscillation signal is supplied to a generation circuit (54). Then, the generated composite synchronization signal Sync is sent to the drive circuit (5
7) to the multicore cable (3).

On the other hand, in the CHU (2), the composite synchronization signal Sync transmitted through the multi-core cable (3) is sent to the separation circuit (5
B), the vertical pulse VD and the horizontal pulse HD are separated, and the separated vertical pulse VD is sent to the synchronizing signal generating circuit (60) through the reset signal generating circuit (59).
is supplied to In addition, the horizontal pulse HD from the separation circuit (58) passes through the phase comparator circuit (61) to the variable oscillator (62).
), and this oscillation signal is supplied to the generating circuit (60). Furthermore, the horizontal synchronizing pulse HD from the generation circuit (60) is supplied to the phase comparison circuit (61).

In addition, the horizontal pulse HD from the separation circuit (58) is retransmitted to the multicore cable (3) through the drive circuit (63).The horizontal pulse HD retransmitted at the CCU (1) is then used for correction such as waveform shaping. The signal is supplied to the phase comparison circuit (55) through the circuit (64).

Thereby, the generation circuit (60) is synchronized so that the retransmitted horizontal pulse HD matches the phase of the original synchronization signal.

The vertical pulse VD and horizontal pulse HD from this generation circuit (60) are supplied to the timing generation circuit (31),
Vertical shift clock φ7, ~φV and horizontal shift clock φM synchronized with vertical pulse VD and horizontal pulse HD
++φ)12 and a precharge pulse Pp are generated. CCD (32R) (32G> (32B) for these clocks φv1 to φv4 to form a video signal
and the clock φ□, φ)+2, pulse P
, are the CCD output registers (33R) (33G) (
33B) and the generated video signal is extracted. This video signal is processed by the sample and hold circuit (
34R) (34G) (34B). Further, the precharge pulse P from the generation circuit (31) is supplied to the sampling pulse generation circuit (35), and this sampling pulse is supplied to the circuits (34R) to (34B).
The sampled video signal is transmitted to the multicore cable (3) through the drive circuit (31iR> (36G) (36B)).

Note that the CCD output register (33R) ~ (3
3B), a signal is taken out via, for example, a floating diffusion amplifier.
As shown in Japanese Patent No. 6374, a video signal is obtained by correlated double sampling processing.

Furthermore, the video signal transmitted through the multi-core cable (3) is transferred to the floating amplifier (37R) (37G) (3
7B) is supplied to a process circuit (38) that performs processing such as T correction and white clipping, and this processed signal is supplied to an encoder (39) to form a predetermined composite signal. This composite signal is supplied to the mixing circuit (40), and the vertical pulse VD and horizontal pulse HD from the generating circuit (52) are combined by the blanking generating circuit (41) and supplied to the mixing circuit (40), which mixes The resulting composite video signal is taken out to an output terminal (42).

In this way, according to the above-mentioned device, the phase of the video signal transmitted from the CHU to the ccU can be made to match the synchronization signal of the CCU, so that good video signal processing can be performed.

[Problem to be solved by the invention]

By the way, in the above device, in the above example, CHU [2]
a timing signal generation circuit (31) provided on the side;
Sample hold circuit (34R) ~<34B)
It was considered that the CHU (2) could be further miniaturized by providing the same on the CCU (1) side.

However, in that case, as mentioned above, it is necessary to achieve accurate synchronization phase matching between CCU (1) and CHtJ (2), and in order to perform sample and hold, an extremely accurate pixel clock (horizontal shift It is necessary to obtain the phase of the clock).

To do this, for example, a part of the timing signal transmitted from the timing generation circuit (31) provided in the CCU (1) to the CHU (2) may be returned to the CCU (1). As many as seven cables are already used for the core cable (3) just for transmitting timing signals, and it is difficult and undesirable to increase the number of cables by even one.

This application was filed in view of these points.

[Means to solve the problem]

The present invention provides a camera head unit (2) that performs imaging.
In a camera system in which a camera control unit (1) and a camera control unit (1) that process the imaged signals are formed separately, and these are connected by a predetermined cable (3), the camera head, The unit is equipped with a CCD image sensor (32), which extracts a signal from the CCD image sensor and directly transmits it to the camera control unit via the cable.
The control unit extracts a waveform based on a predetermined timing in the transmitted signal (peak clamp circuit (15) to waveform shaping circuit (17)) L, shapes this extracted waveform, and outputs it from at least the CCD. This camera system is characterized in that a timing signal (sample pulse generation circuit (35)) corresponding to a waveform based on imaging in the signal is formed (sample pulse generation circuit (35)).

[Effect]

According to this, the waveform based on the predetermined timing included in the output signal from the CCD is extracted and the timing for sample and hold etc. is obtained on the camera control unit side, so there is no need to use an extra signal line. Therefore, good signal processing can be performed with a simple configuration.

〔Example〕

In Figure 1, the synchronization signal generation circuit (
The vertical pulse VD from 52) and the horizontal frequency signal from the variable oscillator (56) are supplied to the timing signal generation circuit (31) provided on the CCU (1) side, and the vertical shift clocks φ□~ φV4 and horizontal shift clock φ, +1. φH2 and precharge pulse P are generated. A signal from this generation circuit (31) is transmitted to the multicore cable (3).

On the other hand, in the CHU (2), among the signals transmitted through the multicore cable (3), the vertical shift clocks φv1 to φ7. is direct CCD (32R)
~(32B) High frequency horizontal shift clock φM++ φH2 and precharge pulse P,
are the drive circuits (11) (12) (13) respectively.
Output register (33R) ~ (33B) through
It is supplied to Furthermore, output registers (33R) to (3
The signals from 3B) are connected to the drive circuits (14R
) (14u) (14B) is transmitted to the multicore cable (3).

The CCD (3) is transmitted to this multi-core cable (3).
CC for signals from 2R) ~ (32B)
Each sample hold circuit (34
R) to (34B) are provided, and the transmitted signals are supplied to the respective circuits, and these transmitted signals are respectively connected to the peak clamp circuits (15R) (15
G) (15B). Furthermore, the signals from the clamp circuits (15R) to (15B) are each supplied to comparison circuits (16R) (16G) (16B)), where they are compared with a predetermined level somewhat lower than the clamp level, and the comparison outputs are each waveform shaped. Circuit (17R)
(17G) (17B) Through sampling pulse generation circuit (34R) (34G) (34B)
The sampling pulses generated are sent to sample and hold circuits (34R) to (34B).
is supplied to

In other words, in this device, the CCD output register (3
When the signals from 3R) to (33B) are extracted via the above-mentioned floating diffusion amplifier, the output signal waveforms are as shown in Fig. 2, as shown in the above-mentioned literature. Become like to.

Here, the waveform is the precharge pulse P as shown in the figure.
, a P phase that always shows a black level, and a D phase that changes depending on the amount of light and becomes lower than the P phase as the amount of light increases. Therefore, as described above, the signal is peak-clamped, this clamp signal is compared with a predetermined level, and this comparison output is waveform-shaped, so that the coupling pulse of the precharge pulse Pp is A reference signal with predetermined timing can be formed.

Therefore, by forming sampling pulses for sampling the above-mentioned P and D phases from this reference signal as shown in C and D in the same figure, and supplying them to the sample and hold circuit, it is possible to perform good video signal processing. . Note that this reference signal has a predetermined amount of delay due to the operation delay of the circuit, but the above-described sampling pulse can be formed in consideration of this amount of delay.

Furthermore, in the above-mentioned device, the timing signal generation circuit (3
The precharge pulse P generated in 1) has a missing portion, for example, in the period of the horizontal pulse HD. Therefore, for example, the reference signal from the waveform shaping circuit (17R) and the precharge pulse P from the generation circuit (31) are supplied to the detection circuit (18), and by detecting the omission of the reference signal, the transmitted image is Horizontal pulses HD of the signal can be detected.

This detected horizontal pulse is then converted into a phase comparator circuit (55).
), the generation circuit (31>) is controlled so that the horizontal pulse HD of the transmitted video signal matches the phase of the original synchronizing signal.

Furthermore, Fig. 3 shows the specific circuit configuration of the peak clamp circuit (15) to the waveform shaping circuit (17) mentioned above. This is high level clamping by diode clamping performed by capacitor C resistor R2 and transistor Q2.

In this case, the capacitor C1 is 0.01 μF, which is small and somewhat hard. The clamp level depends on the emitter potential of transistor Q3. The reason why a transistor is used instead of a diode for the lamp element Q2 is to balance it with the transistor Q3.

That is, the emitter potential of transistor Q3 moves by 2 mV per 1° C. due to the temperature of Vbe, so by using the same transistor as Q for Q2, fluctuations in the DC value of the output are reduced.

Next, the area between the dotted and dashed lines in the center corresponds to the comparison circuit (16),
Comparison is performed by a high-speed comparator composed of transistors Q6 to Q9, diodes D3 to Dg, and resistors R8 to R1°. That is, a reference potential is input to the base of transistor Q9, and a signal is input to the base of transistor Q6. In addition, the collector of transistor Q6 becomes an output, and a normally high pulse is output as an inverted output. In this case, the reference potential of the base of transistor Q is created by the emitter follower of transistor Qs. Note that the temperature characteristics of the emitter potential of the transistor Q5 are balanced and canceled by the transistor Q.

The circuit after the dashed line on the right side is the waveform shaping circuit (1
7), a pulse from the comparator circuit (16) enters the constant current driven emitter follower and enters the driver stage. That is, capacitors Cs and C+. , diode D, ,D2,
) transistor Q, 2. A 0-5v pulse is created by an inverting driver consisting of Q and 3. Note that diode D
1. By using a Schottky diode for D2, transistors Q, 2. The pulse width is widened by increasing the saturation time of Q.

In this way, according to the above-mentioned device, the waveform based on the predetermined timing included in the output signal from the CCD is extracted to obtain the timing for the sample hold on the camera control unit side. It is possible to perform good signal processing with a simple circuit without using.

In addition, in the above-mentioned specific circuit, the waveform of the output pulse is, for example, amplitude 5.2Vpp, pulse 1m16m 5ecCC
Obtained with a delay amount of 14n sec for the output waveform of D,
Experiments have confirmed that this pulse can be used as a reference pulse.

(31) is a timing signal generation circuit, (32) is a CCD
, (33) is the output register, (34) is the sample hold circuit, (35) ! This is a sample pulse generation circuit.

〔Effect of the invention〕

According to this invention, since the waveform based on the predetermined timing included in the output signal from the CCD is extracted and the timing for sample hold etc. is obtained on the camera control unit side, an extra signal line is used. It has now become possible to perform good signal processing with a simple circuit without any problems.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of the present invention, FIGS. 2 and 3 are diagrams for explaining the same, and FIG. 4 is a diagram for explaining a conventional technique. (1) is the camera control unit, (2) is the camera head unit, (3) is the multi-core cable, (1)
1) to (14) are drive circuits, (15) are peak clamp circuits, (16) are comparison circuits, (17) are waveform shaping circuits, Agents: Itosada Domatsu, Hidemori Kuma

Claims (1)

[Claims] A camera in which a camera head unit that captures images and a camera control unit that processes the captured signals are formed separately, and these are connected by a predetermined cable. In the system, the camera head unit is provided with a CCD image sensor, and the signal from the CCD image sensor is extracted and directly transmitted to the camera control unit via the cable, and the camera head unit is connected to the camera control unit. The unit extracts a waveform based on a predetermined timing in the transmitted signal, and shapes the extracted waveform to form at least a timing signal corresponding to the waveform based on imaging in the signal from the CCD. A camera system characterized by: