JPH0247909B2 - WACHUKAISEN HOJIKAIRO - Google Patents
WACHUKAISEN HOJIKAIROInfo
- Publication number
- JPH0247909B2 JPH0247909B2 JP23680483A JP23680483A JPH0247909B2 JP H0247909 B2 JPH0247909 B2 JP H0247909B2 JP 23680483 A JP23680483 A JP 23680483A JP 23680483 A JP23680483 A JP 23680483A JP H0247909 B2 JPH0247909 B2 JP H0247909B2
- Authority
- JP
- Japan
- Prior art keywords
- bits
- signaling
- output
- circuit
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000011664 signaling Effects 0.000 claims description 27
- 238000011084 recovery Methods 0.000 description 9
- 238000000926 separation method Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/08—Indicating faults in circuits or apparatus
- H04M3/12—Marking faulty circuits "busy"; Enabling equipment to disengage itself from faulty circuits ; Using redundant circuits; Response of a circuit, apparatus or system to an error
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明はPCM端局装置のシグナリング処理方
法に係り、特にPCM信号伝送路の瞬断等に基づ
くアラームが発生した場合の話中回線保持回路に
関する。[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a signaling processing method for a PCM terminal equipment, and in particular to a busy line holding circuit when an alarm occurs due to a momentary interruption of a PCM signal transmission path, etc. Regarding.
(b) 従来技術と問題点
従来、PCM端局装置を用いて通信回線を構成
した場合、信号伝送路に瞬断等が発生すると該信
号伝送路上を伝送中のシグナリングビツトが正常
でなくなるため、話中回線が切断される。第１図
はPCM端局装置を用いた通信回線の構成例を示
す。交換機１からCH1からCHnまでのｎチヤネ
ルの電話回線がPCM端局装置２に接続され、音
声情報とシグナリング情報とが交換機１とPCM
端局装置２の間で伝送される。PCM端局装置２
と３の間は前記音声情報とシグナリング情報とが
コード化されたPCM信号を伝送する回線である。
また交換機４からCH1からCHnまでのｎチヤネ
ルの電話回線がPCM端局装置３に接続され、音
声情報とシグナリング情報とが交換機４とPCM
端局装置３の間で伝送される。ここで例えば回線
の５で示す位置で回線断が発生するとPCM信号
が断となるため、PCM端局装置３の受信ビツト
は正常でなくなり、その時交換機１と４の間で構
成されていた話中回線が切断される。通話が瞬断
する程度では余りサービス低下にはならないが、
通話中の回線が切断されると、再度ダイヤリング
して通話回線を構成し直す必要があり、大幅なサ
ービスの低下となるという欠点がある。(b) Conventional technology and problems Conventionally, when a communication line is configured using PCM terminal equipment, if a momentary interruption occurs in the signal transmission path, the signaling bits being transmitted on the signal transmission path become abnormal. The busy line is disconnected. FIG. 1 shows an example of the configuration of a communication line using PCM terminal equipment. N-channel telephone lines from CH1 to CHn from exchange 1 are connected to PCM terminal equipment 2, and voice information and signaling information are transferred between exchange 1 and PCM.
It is transmitted between the terminal devices 2. PCM terminal equipment 2
and 3 is a line that transmits a PCM signal in which the voice information and signaling information are encoded.
In addition, the n-channel telephone lines from CH1 to CHn from the exchange 4 are connected to the PCM terminal equipment 3, and voice information and signaling information are transferred between the exchange 4 and the PCM.
It is transmitted between the terminal devices 3. For example, if a line disconnection occurs at the position indicated by 5 on the line, the PCM signal will be disconnected, and the received bits of the PCM terminal equipment 3 will no longer be normal. The line is disconnected. Momentary interruptions in calls do not significantly degrade service, but
If the line during a call is disconnected, it is necessary to reconfigure the call line by dialing again, which has the disadvantage of significantly degrading the service.
(c) 発明の目的
本発明の目的は上記欠点を除くため、PCM端
局装置がPCM信号の断を検出してアラームを発
生した時、アラーム発生直前のシグナリングビツ
トをラツチしておくことにより、該ラツチしてお
いたシグナリングビツトを用いて話中回線の接続
を継続させることで、該当話中回線が切断される
ことを防止する話中回線保持回路を提供すること
にある。(c) Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks by latching the signaling bit immediately before the alarm occurs when the PCM terminal equipment detects a disconnection of the PCM signal and generates an alarm. To provide a busy line holding circuit which prevents the busy line from being disconnected by continuing the connection of the busy line using the latched signaling bit.
(d) 発明の構成
本発明の構成はPCM端局装置のシグナリング
ビツト処理回路において、音声情報ビツトとシグ
ナリングビツトとを分離した後、該シグナリング
ビツトをｍビツト分順次連続して記憶する手段
と、該記憶手段から読出したｍビツトの各データ
に対して予め定められた処理を施す手段と、該処
理手段の出力をラツチする手段とを設け、アラー
ム発生と同時に該ラツチ手段にラツチされたシグ
ナリングビツトを用いて、話中回線をアラーム復
旧後前記ｍビツト処理手段の出力が正常となるま
で保持するようにしたものである。(d) Structure of the Invention The structure of the present invention includes means for separating audio information bits and signaling bits in a signaling bit processing circuit of a PCM terminal equipment, and then successively storing m bits of the signaling bits; Means for performing predetermined processing on each of m bits of data read from the storage means and means for latching the output of the processing means are provided, and the signaling bit latched by the latch means at the same time as an alarm is generated. is used to hold the busy line until the output of the m-bit processing means becomes normal after the alarm is restored.
(e) 発明の実施例
第２図は本発明の一実施例を示す回路のブロツ
ク図である。端子Ａより多重化されたｎチヤネル
分のPCM信号が分離回路１０に入る。ここで音
声ビツトとシグナリングビツトが分離され、音声
ビツトは端子CH1′〜CHn′に送出される。シグナ
リングビツトは例えばＤフリツプフロツプ１１，
１２，１３で構成される３ビツトのシフトレジス
タにチヤネル１が、Ｄフリツプフロツプ１４，１
５，１６で構成される３ビツトシフトレジスタに
チヤネルｎが夫々送出される。フリツプフロツプ
１１〜１６のＴ端子には分離回路１０からシグナ
リングビツトの受信周期に同期したシフトクロツ
クが与えられる。従つてフリツプフロツプ１１〜
１３には３ビツト分のシグナリングビツトが記憶
される。フリツプフロツプ１１〜１３からなるシ
フトレジスタの出力は３ビツト処理回路１８に入
り、多数決処理（例えばフリツプフロツプ１１と
１３の出力が“１”でフリツプフロツプ１２の出
力が“０”の時“１”と判定する）又は連続判定
処理（例えばフリツプフロツプ１１〜１３の総て
が“１”の時“１”と判定する）等により処理さ
れ、ラツチ回路１９と切替器２０に送出される。
ラツチ回路１９はチヤネル１のシグナリングビツ
トを遅延復旧回路２５の出力によりラツチする。
そしてラツチ回路１９の出力は切替器２１に送出
される。PCM信号が断となると分離回路１０か
らアラーム信号が遅延復旧回路２５に送出され
る。遅延復旧回路２５はアラーム信号受信と同時
に動作し、アラーム信号が復旧しても一定時間経
由した後復旧する信号を作成し、ラツチ回路１９
と２４及び切替器２０〜２３に供給する。切替器
２０は遅延復旧回路２５の出力がオフの時３ビツ
ト処理回路１８の出力を端子CH1に送出しオン
の時阻止する。又切替器２１は遅延復旧回路２５
の出力がオンの時ラツチ回路１９の出力を端子
CH1に送出しオフの時阻止する。従つて端子
CH1には、それ迄３ビツト処理回路１８が送出
していたシグナリングビツトの代わりに、アラー
ム発生と同時にラツチ回路１９がラツチしていた
チヤネル１のシグナリングビツトが送出される。
そしてアラームが復旧して３ビツト処理回路１８
の出力が正常に回復する迄の一定時間が経過する
間は前記ラツチしていたチヤネル１のシグナリン
グビツトの送出が継続される。従つてチヤネル１
が話中の場合は回線が切断されずに維持される。
フリツプフロツプ１４〜１６で構成されるシフト
レジスタの出力は３ビツト処理回路１７に入り、
多数決処理又は連続判定処理等により処理され、
ラツチ回路２４と切替器２２に送出される。ラツ
チ回路２４はチヤネルｎのシグナリングビツトを
遅延復旧回路２５の出力によりラツチする。そし
てラツチ回路２４の出力は切替器２３に送出され
る。切替器２２は遅延復旧回路２５の出力がオフ
の時３ビツト処理回路１７の出力を端子CHnに
送出しオンの時阻止する。又切替器２３は遅延復
旧回路２５の出力がオンの時ラツチ回路２４の出
力を端子CHnに送出しオフの時阻止する。従つ
て端子CHnには、それ迄３ビツト処理回路１７
が送出していたシグナリングビツトの代わりに、
アラーム発生と同時にラツチ回路２４がラツチし
ていたチヤネルｎのシグナリングビツトが送出さ
れる。そしてアラームが復旧して３ビツト処理回
路１８の出力が正常に回復する迄の一定時間が経
過する間は前記ラツチしていたチヤネルｎのシグ
ナリングビツトの送出が継続される。従つてチヤ
ネルｎが話中の場合は回線が切断されずに維持さ
れる。(e) Embodiment of the invention FIG. 2 is a block diagram of a circuit showing an embodiment of the invention. N-channel multiplexed PCM signals enter the separation circuit 10 from the terminal A. Here, the audio bits and signaling bits are separated, and the audio bits are sent to terminals CH1' to CHn'. The signaling bits are, for example, D flip-flop 11,
Channel 1 is connected to a 3-bit shift register consisting of D flip-flops 12 and 13, and D flip-flops 14 and 1
Channel n is sent to a 3-bit shift register consisting of 5 and 16 bits, respectively. The T terminals of the flip-flops 11 to 16 are supplied with a shift clock synchronized with the reception period of the signaling bits from the separation circuit 10. Therefore, flip-flop 11~
13 stores 3 signaling bits. The output of the shift register consisting of flip-flops 11 to 13 enters a 3-bit processing circuit 18, which performs majority voting processing (for example, when the outputs of flip-flops 11 and 13 are "1" and the output of flip-flop 12 is "0", it is determined to be "1"). ) or continuous determination processing (for example, it is determined as "1" when all of the flip-flops 11 to 13 are "1"), and is sent to the latch circuit 19 and the switch 20.
Latch circuit 19 latches the channel 1 signaling bit with the output of delay recovery circuit 25.
The output of the latch circuit 19 is then sent to the switch 21. When the PCM signal is disconnected, an alarm signal is sent from the separation circuit 10 to the delay recovery circuit 25. The delay recovery circuit 25 operates at the same time as the alarm signal is received, and even if the alarm signal is recovered, it creates a signal that recovers after a certain period of time, and the latch circuit 19
and 24 and the switching devices 20 to 23. The switch 20 sends the output of the 3-bit processing circuit 18 to the terminal CH1 when the output of the delay recovery circuit 25 is off, and blocks it when the output is on. The switch 21 also has a delay recovery circuit 25.
When the output of the latch circuit 19 is on, the output of the latch circuit 19 is connected to the terminal.
Blocks when sending to CH1 is off. Therefore the terminal
Instead of the signaling bits previously sent by the 3-bit processing circuit 18, the channel 1 signaling bits that were latched by the latch circuit 19 at the same time as the alarm generation are sent to CH1.
Then, the alarm is restored and the 3-bit processing circuit 18
The transmission of the latched signaling bit of channel 1 is continued until a certain period of time elapses until the output of channel 1 is restored to normal. Therefore channel 1
If the line is busy, the line will be maintained without being disconnected.
The output of the shift register composed of flip-flops 14 to 16 enters a 3-bit processing circuit 17.
Processed by majority decision processing or continuous judgment processing, etc.
The signal is sent to the latch circuit 24 and the switch 22. Latch circuit 24 latches the signaling bit of channel n with the output of delay recovery circuit 25. The output of the latch circuit 24 is then sent to the switch 23. The switch 22 sends the output of the 3-bit processing circuit 17 to the terminal CHn when the output of the delay recovery circuit 25 is off, and blocks it when the output is on. Further, the switch 23 sends the output of the latch circuit 24 to the terminal CHn when the output of the delay recovery circuit 25 is on, and blocks it when the output is off. Therefore, until then, the 3-bit processing circuit 17 is connected to the terminal CHn.
Instead of the signaling bits that were being sent out,
At the same time as the alarm occurs, the signaling bit of channel n that was latched by the latch circuit 24 is sent out. The transmission of the latched signaling bits of channel n is continued until a certain period of time elapses until the alarm is restored and the output of the 3-bit processing circuit 18 is restored to normal. Therefore, when channel n is busy, the line is maintained without being disconnected.
(f) 発明の効果
以上説明した如く、本発明はPCM回線が瞬断
等によりPCM端局装置がアラームを発生した場
合に話中回線が切断されサービスが低下すること
を防止出来る。(f) Effects of the Invention As explained above, the present invention can prevent the busy line from being disconnected and the service from deteriorating when the PCM terminal equipment generates an alarm due to a momentary interruption of the PCM line.
第１図はPCM端局装置を用いた通信回線構成
例を示す図、第２図は本発明の一実施例を示す回
路のブロツク図である。
１，４は交換機、２，３はPCM端局装置、１
０は分離回路、１１，１２，１３，１４，１５，
１６はフリツプフロツプ、１７，１８は３ビツト
処理回路、１９，２４はラツチ回路、２０，２
１，２２，２３は切替器、２５は遅延復旧回路で
ある。
FIG. 1 is a diagram showing an example of a communication line configuration using a PCM terminal device, and FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention. 1 and 4 are exchanges, 2 and 3 are PCM terminal equipment, 1
0 is a separation circuit, 11, 12, 13, 14, 15,
16 is a flip-flop, 17, 18 are 3-bit processing circuits, 19, 24 are latch circuits, 20, 2
1, 22, and 23 are switchers, and 25 is a delay recovery circuit.
Claims (1)
路において、音声情報ビツトとシグナリングビツ
トとを分離した後、該シグナリングビツトをｍビ
ツト分順次連続して記憶する手段と、該記憶手段
から読出したｍビツトの各データに対して予め定
められた処理を施す手段と、該処理手段の出力を
ラツチする手段とを設け、アラーム発生と同時に
該ラツチ手段にラツチされたシグナリングビツト
を用いて、話中回線をアラーム復旧後前記ｍビツ
ト処理手段の出力が正常となるまで保持すること
を特徴とする話中回線保持回路。1 In the signaling bit processing circuit of the PCM terminal equipment, after separating the audio information bits and the signaling bits, means for successively storing m bits of the signaling bits, and each of the m bits read from the storage means. A means for performing predetermined processing on data and a means for latching the output of the processing means are provided, and a signaling bit latched to the latch means at the same time as an alarm is generated is used to restore the busy line to the alarm. A busy line holding circuit is characterized in that the busy line holding circuit holds the output of the m-bit processing means until it becomes normal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23680483A JPH0247909B2 (en) | 1983-12-15 | 1983-12-15 | WACHUKAISEN HOJIKAIRO |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23680483A JPH0247909B2 (en) | 1983-12-15 | 1983-12-15 | WACHUKAISEN HOJIKAIRO |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60127857A JPS60127857A (en) | 1985-07-08 |
| JPH0247909B2 true JPH0247909B2 (en) | 1990-10-23 |
Family
ID=17006028
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23680483A Expired - Lifetime JPH0247909B2 (en) | 1983-12-15 | 1983-12-15 | WACHUKAISEN HOJIKAIRO |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0247909B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3886315A1 (en) | 2020-03-24 | 2021-09-29 | Kabushiki Kaisha Yaskawa Denki | Motor control apparatus, elevator drive system, and motor control method |
-
1983
- 1983-12-15 JP JP23680483A patent/JPH0247909B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3886315A1 (en) | 2020-03-24 | 2021-09-29 | Kabushiki Kaisha Yaskawa Denki | Motor control apparatus, elevator drive system, and motor control method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60127857A (en) | 1985-07-08 |
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