JPH0246590A - Memory device - Google Patents

Abstract

PURPOSE:To minimize a device size and to shorten serial access time by providing plural transistors to transfer data between the input edge of respective flip flops and respective digit lines. CONSTITUTION:A serial port is connected through respective transistors Q31-Q34 of a data transfer gate 3 between the input edge or output edge of respective flip flops FFf1-FF5, the data between these are transferred, the data are directly mounted and communicated to the shift register 2. Consequently, a data input output circuit including a data register and a data bus is not made necessary. Thus, the device size can be minimized and the serial access time can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory device, and more particularly to a dual-baud 1-type memory device equipped with a serial port and a parallel port, which is used as a frame buffer for image data.

[Conventional technology]

A conventional memory device of this type will be described with reference to the drawings.

FIG. 4 is a circuit diagram showing an example of a conventional memory device.

Memory cell array] includes a plurality of memory cells 11 arranged in a matrix, a plurality of digit lines connected to these memory cells 11, ~D5, and a word line (WK).
It is equipped with

The data transfer gate 3 connects the first terminal to each digit line ~D5 in correspondence with each other, inputs the data transfer control signal TO to the gates, turns on/off, and connects the first and second terminals. A plurality of transistors Q31 to Q35 are provided to transfer data between the two transistors.

The data register 4 includes a plurality of registers R1 to R6 whose input/output terminals are respectively connected to the second terminals of the respective transistors Q31 to Q35 of the data transfer gate 3 and hold data transmitted to the input/output terminals. We are prepared.

The data input/output circuit 5 has one end connected to each register R1.
~ Connect correspondingly to the input/output end of R5 and connect the other end to data bus 5.
A plurality of transistors Q are commonly connected to 1 and are turned on and off by inputting scanning signals SS1 to SS to their gates to transfer data between each register R1 to R5 and the data bus 51.
51 to Q55. Note that the data bus 5] is connected to an input/output terminal TTo for serial data input/output.

The shift register 2B includes a plurality of cascade-connected flip-flops FF, ~FF5, and receives a scanning signal from the output terminals of these flip-flops 'F1~FF5 to sequentially turn on the transistors Q+it~Q55 of the data input/output circuit. Output S81 to S85.

F-described data transfer gate 3. A serial port is formed by the data register 4, data input/output circuit 5, and shift register 2B.

Next, the operation of this memory device will be explained using an example of reading data.

In the memory cell array 1, the word line W+< at the row address is activated and the memory cell 11 on the word line WK is activated.
When refreshed, the data of each memory cell 11 appears on the corresponding digit line D1-D.

Immediately after this, when the data transfer gate 3 is opened by the data transfer control signal TG, the data on each digit line D1 to D5 is transferred and latched to each register R1 to R5 of the data register 4 (the word line at the row address (The data of all memory cells 11 connected to WK are transferred).

The data latched in each register R1 to R5 of the data register 4 is transmitted by the scanning signal SS1 from the shift register 2B.
The transistors Q51 to Q55 of the data input/output circuit 5, which are turned on sequentially by SS5, sequentially transfer one bit at a time to the input/output terminal TIO via the data bus 51, and output as serial data.

[Problem to be solved by the invention]

” A conventional memory device in series consists of data transfer gates 3.
Data register 4. Since the serial port is formed by the data input/output circuit 5 and the shift register 2R, there is a drawback that the data register 4 and the shift register 2B occupy a large area and the device size becomes large. This has the drawback that the bus 51 is subject to a large load, which increases the data transfer time and the serial access time.

An object of the present invention is to provide a memory device that can reduce device size and shorten serial access time.

[Means to solve the problem]

The memory device of the present invention includes a memory cell array including a plurality of memory cells arranged in a matrix, a plurality of tigit lines and word lines connected to these memory cells, and a plurality of cascade-connected flip-flops. , at least one of an input terminal for inputting serial data and an output terminal for outputting serial data is connected to at least one of the first stage and the last stage of these flip-flops, and the input terminal of each flip-flop is connected to the input terminal of each flip-flop by a clock signal. A shift register that sequentially transmits the transmitted data backward; and a shift register that is connected correspondingly between the input terminal (or output terminal) of each of the flip-flops and each of the Diff 1 to lines, and transfers data between them. The data transfer gate includes a plurality of transistors that perform the following steps.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In this embodiment, the present invention is applied to the output side of a serial port.

The memory cell array 1 of this embodiment is similar to a conventional memory device.

The shift register 2 includes transistors Q21 to Q, respectively.
A plurality of flip-flops F cascaded via 24
F, ~FF5, and the last stage flip-flop F
Connect the output terminal '. to F5, and connect the transistors Q21 to
When Q24 is off, the clock signal CLK causes the flip-flops FFl to FF5 to hold the data at their respective input terminals, and when the transistors Q21 to Q24 are on, the clock signal CLK causes the flip-flops FF, to FF, to hold the data. The held data is sequentially transmitted to the rear.

The data transfer gate 3 connects the input terminals of the flip-flops FF2 to FF5 of the shift register 2 to the digit lines D1 to D.
The data transfer control signal TG is input to the gates to turn them on and off, and the data on the digit lines D1 to D4 are transferred to the flip-flops FF2 to FF.
, to each input terminal.

The inverter 11 inverts the data transfer control signal TG and transmits it to the gates of the transistors Q21 to Q24. Flip-flops FF, ~FF5 are separated from each other, and these flip-flops FF, ~FF5 are separated during data shift.
Connect between FF5.

” Dual shift register 2. A serial port is formed by the data transfer gate 3 and the inverter 1.

Next, the operation of this embodiment will be explained.

In the memory cell array 1, when the word line WK at the row address is activated and the memory cell 11 on the word line W8 is refreshed, the data of the memory cell]1 appears on the corresponding digit lines ■)1 to I)4. .

Immediately after this, when the data transfer gate 3 is opened by the data transfer control signal TG, the data on each digit line ~D4 is transferred to the flip-flops FF2~FF of the shift register 2.
, and is latched into flip-flops FF2 to FF5 by clock signals CL and K (at this time, transistors Q21 to Q24 are in the off state,
Furthermore, the data of all memory cells 11 connected to the word line WK at the row address are transferred).

When the data transfer control signal TG becomes inactive, the transistors Q21 to Q24 become conductive, so the data latched in the flip-flops FF2 to FF5 is transferred to the clock signal C.
The bits are sequentially transmitted to the rear via LK, and are sequentially output one bit at a time from the output terminal To.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, the present invention is applied to the input side of a serial port.

This embodiment differs from the first embodiment in that the inverter 1, the last stage flip-flop FF5, and the output terminal T
o and remove the connection with transistor Q 2 t~
Q24 is shortened, the input terminal T1 is connected to the first flip-flop FF1, and the data flow is routed from the input terminal T+ to the digit line through the shift register 2A, ~D5/\
The point is that it is reversed to reach the point.

Next, the operation of this embodiment will be explained.

Serial data SDI input to input terminal TI is sequentially shifted and latched by flip-flops FF, -FF of shift register 2A in accordance with clock signal CLK.

When the data is stored in the shift register 2A, the data transfer control signal TG is activated to transfer the data to the shift register 2A.
Data in digit 1 is transferred to memory cell 11 connected to activated word line WK via lines D1 to D5.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

This embodiment is an integration of the first and second embodiments so that input and output of serial data can be performed by the same circuit.

In this embodiment, the input terminal of the inverter 1 of the first embodiment is separated from the input terminal of the data transfer control signal TG so that it can be controlled independently. ” 5, each input terminal TI
, output terminal T. When inputting serial data, the transistor Q21 is connected by the control signal C8.
~When shorting Q24 and outputting serial data,
Control signal CS has the same waveform as data transfer control signal TG to control on/off of transistors Q21 to Q24.

The operation of this embodiment is such that the first
This is similar to the second embodiment, and the input is similar to the second embodiment.

〔Effect of the invention〕

As explained above, the present invention connects a serial port between the input end or output end of each flip-flop of a shift register and each digit line through each transistor of a data transfer gate, and transfers data between them. By implementing a configuration in which the data is transferred and transferred directly to the shift register, the data register and data input/output circuit including the data bus that were required in the past can be removed, allowing the device size to be reduced. can,
Moreover, there is an effect that the serial access time can be shortened.

[Brief explanation of the drawing]

1 to 3 are circuit diagrams showing first to third embodiments of the present invention, respectively, and FIG. 4 is a circuit diagram showing an example of a conventional memory device.

Claims (1)

[Claims] A memory cell array including a plurality of memory cells arranged in a matrix, a plurality of digit lines and word lines connected to these memory cells, and a plurality of cascade-connected flip-flops, the first stage of these flip-flops. and at least one of an input terminal for inputting serial data and an output terminal for outputting serial data are connected to at least one of the last stage, and the data transmitted to the input terminal of each flip-flop by a clock signal is sequentially transmitted to the input terminal of each flip-flop. and a plurality of transistors connected in correspondence between the input end (or output end) of each of the flip-flops and each of the digit lines to transfer data therebetween. A memory device comprising a transfer gate.