JPH0244937A - Circuit for adjusting identified phase - Google Patents

Circuit for adjusting identified phase

Info

Publication number
JPH0244937A
JPH0244937A JP63195621A JP19562188A JPH0244937A JP H0244937 A JPH0244937 A JP H0244937A JP 63195621 A JP63195621 A JP 63195621A JP 19562188 A JP19562188 A JP 19562188A JP H0244937 A JPH0244937 A JP H0244937A
Authority
JP
Japan
Prior art keywords
section
phase
error rate
code error
phase adjustment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63195621A
Other languages
Japanese (ja)
Inventor
Masahiro Suzuki
正博 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63195621A priority Critical patent/JPH0244937A/en
Publication of JPH0244937A publication Critical patent/JPH0244937A/en
Pending legal-status Critical Current

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  • Synchronisation In Digital Transmission Systems (AREA)
  • Optical Communication System (AREA)

Abstract

PURPOSE:To prevent the increase in a code error rate by providing a phase control section varying the phase adjustment state of a timing signal in the optimum direction according to the detection output of the code error rate so as to keep the phase adjustment state in the optimum state at all times in response to the phase characteristic change of each section. CONSTITUTION:The phase control section 7 is provided between a code error rate count section 6 and a phase adjustment section 4. Then the count output of the count section 6 is used as a detection output of the code error rate, the control section 7 varies the phase shift of the adjustment section 4 accordingly so as to control the phase adjustment state of the timing signal by the section 4 in the optimum direction. Thus, even if the phase characteristic of each section is fluctuated due to the change with the lapse of time or the like, the phase adjustment state of the timing signal is always maintained as the optimum state automatically. Thus, the code error rate is kept lowest.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、光信号受信回路において、光受信信号の識別
位相を自動的に調整する回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit that automatically adjusts the identification phase of an optical reception signal in an optical signal reception circuit.

〔従来の技術〕[Conventional technology]

第2図に従来例のブロック図を示すとおシ、入力INへ
与えられた光受信信号を等化増幅部1によ9等化および
増幅を行なってから、識別再生部2においてサンプリン
グ等によシ論理値の識別を行ない、受信出力OUTへ送
出する一方、等化増幅部1を介する光受信信号からタイ
ミング抽出部3においてタイミング信号を抽出し、位相
調整部4によシ固定的な位相調整を行ない、この位相調
整後のタイミング信号に基づき、識別再生部2における
識別時点を定めるものとなっている。
FIG. 2 shows a block diagram of a conventional example. After the optical reception signal applied to the input IN is equalized and amplified by the equalization amplification section 1, the identification and regeneration section 2 performs sampling etc. At the same time, the timing extractor 3 extracts a timing signal from the optical reception signal via the equalization amplifier 1, and the phase adjuster 4 performs fixed phase adjustment. Based on this phase-adjusted timing signal, the identification time point in the identification reproducing section 2 is determined.

また、識別再生部2の出力は、符号誤シ検出部5におい
てコードの誤シが検出され、この検出出力を符号誤シ率
計数部6によシ計数し、コードの誤)率が一定値以上と
なれば、警報表示等を行なうものとなっている。
Further, the code error detection unit 5 detects a code error in the output of the identification/reproduction unit 2, and this detection output is counted by the code error rate counting unit 6, so that the code error rate is a constant value. If the situation exceeds the above, an alarm will be displayed.

なお、位相調整部4の位相偏移量は、製造時において、
符号誤シ率が最小となる値に調整のうえ固定される。
Note that the phase shift amount of the phase adjustment section 4 is determined at the time of manufacturing.
The value is adjusted and fixed to the value that minimizes the code error rate.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、タイミング信号の位相調整状況は、当初最適な
状態であっても、各部の経時変化に応じて最適な状態か
ら不適尚た状態へと推移し、特に伝送速度がIGb/m
を超える高速光受信回路の場合、位相調整状況の不適化
が顕著となυ、受信出力の符号誤シ率が増大する欠点を
生じている。
However, even if the phase adjustment status of the timing signal is initially optimal, it changes from optimal to unsuitable as each part changes over time, especially when the transmission speed is IGb/m.
In the case of high-speed optical receiving circuits exceeding υ, the phase adjustment situation becomes significantly inappropriate, resulting in the drawback that the code error rate of the received output increases.

〔課題を解決するための手段〕[Means to solve the problem]

前述の課題を解決するため、本発明はつぎの手段によ多
構成するものとなっている。
In order to solve the above-mentioned problems, the present invention is constructed by the following means.

すなわち、上述の回路において、光受信信号の識別出力
から符号誤シ率を検出する回路と、この回路の検出出力
にしたがいタイミング信号の位相調整状況を最適な方向
へ可変する位相制御部とを設けたものである。
That is, in the above-mentioned circuit, a circuit for detecting the code error rate from the identification output of the optical reception signal and a phase control section for varying the phase adjustment status of the timing signal in the optimum direction according to the detection output of this circuit are provided. It is something that

〔作用〕[Effect]

したがって、タイミング信号の位相調整状況が常に最適
となシ、各部の経時変化にかかわらず符号誤シ率を最低
に維持できる。
Therefore, the phase adjustment status of the timing signal is always optimal, and the code error rate can be maintained at the lowest level regardless of changes in each part over time.

〔実施例〕〔Example〕

以下、実施例を示す第1図のブロック図によって本発明
の詳細な説明する。
Hereinafter, the present invention will be explained in detail with reference to the block diagram of FIG. 1 showing an embodiment.

同図は、第2図とほぼ同様な構成となっているが、符号
誤シ率計数部6と位相調整部4との間に位相制御部Tが
設けてあシ、計数部6の計数出力を符号誤シ率の検出出
力として用い、これにしたがって制御部7が!ili!
整部4の整相4移量を可変し、間部4によるタイミング
信号の位相調整状況を常に最適な方向へ制御するものと
なっている。
This figure has almost the same configuration as that in FIG. is used as the code error rate detection output, and the control unit 7 uses ! ili!
The amount of phasing shift of the adjustment section 4 is varied, and the phase adjustment status of the timing signal by the adjustment section 4 is always controlled in the optimum direction.

すなわち、位相調整部4においては、例えばバリキャッ
プによシ移相回路の位相偏移量を可変しており、バリキ
ャップのバイアス電圧を位相制御部7が制御し、これに
よシタイミング信号の位相偏移量を定めると共に、制御
部7は、符号誤り率計数部6の計数出力を直流のバイア
ス電圧へ変換し、符号誤シ率が最小となるときバイアス
電圧が平衡する方向へ調整部4を制御している。
That is, in the phase adjustment section 4, the amount of phase shift of the phase shift circuit is varied using, for example, a varicap, and the phase control section 7 controls the bias voltage of the varicap, thereby controlling the timing signal. In addition to determining the amount of phase shift, the control unit 7 converts the count output of the code error rate counting unit 6 into a DC bias voltage, and adjusts the adjustment unit 4 in a direction in which the bias voltage is balanced when the code error rate is minimized. is controlled.

したがって、制御部7を介するフィードバックルーズが
形成されておシ、各部の位相特性が経時変化等によシ変
動しても、タイミング信号の位相調整状況が常に最適な
状態として自動的に維持される。
Therefore, even if a feedback loop is formed through the control section 7 and the phase characteristics of each section change due to changes over time, etc., the phase adjustment status of the timing signal is always automatically maintained in an optimal state. .

〔発明の効果〕〔Effect of the invention〕

以上の説明によシ明らかなとおシ本発明によれば、符号
誤シ率の検出出力にしたがい、タイミング信号の位相調
整状況を最適な方向へ可変する位相制御部を設けたこと
によシ、各部の位相特性変化に応じて位相調整状況が常
に最適として維持され、符号誤り率の増大が阻止される
ため、特に高速光通信の受信回路において顕著な効果が
得られる0
As is clear from the above description, according to the present invention, by providing a phase control section that varies the phase adjustment status of the timing signal in the optimum direction according to the detection output of the code error rate, The phase adjustment status is always maintained as optimal according to changes in the phase characteristics of each part, and an increase in the bit error rate is prevented, which is particularly effective in receiving circuits for high-speed optical communications.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例を示すブロック図、第2図は従
来例のブロック図である。 2・・・φ識別再生部、3・争・・タイミング抽出部、
4・・・・位相調整部、5・・・・符号vAシ検出部、
6・・・・符号誤シ率計数部、7・・・・位相制御部。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional example. 2... φ identification reproduction section, 3. Conflict... timing extraction section,
4... Phase adjustment section, 5... Code vA detection section,
6... code error rate counting section, 7... phase control section.

Claims (1)

【特許請求の範囲】[Claims] 光受信信号から抽出したタイミング信号の位相を調整し
、該調整後のタイミング信号に基づき前記光受信信号の
識別を行なう回路において、前記光受信信号の識別出力
から符号誤り率を検出する回路と、該回路の検出出力に
したがい前記位相の調整状況を最適な方向へ可変する位
相制御部とを設けたことを特徴とする識別位相調整回路
A circuit that adjusts the phase of a timing signal extracted from an optically received signal and identifies the optically received signal based on the adjusted timing signal, a circuit that detects a code error rate from the identification output of the optically received signal; An identification phase adjustment circuit comprising: a phase control section that varies the phase adjustment state in an optimal direction according to a detection output of the circuit.
JP63195621A 1988-08-05 1988-08-05 Circuit for adjusting identified phase Pending JPH0244937A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63195621A JPH0244937A (en) 1988-08-05 1988-08-05 Circuit for adjusting identified phase

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63195621A JPH0244937A (en) 1988-08-05 1988-08-05 Circuit for adjusting identified phase

Publications (1)

Publication Number Publication Date
JPH0244937A true JPH0244937A (en) 1990-02-14

Family

ID=16344216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63195621A Pending JPH0244937A (en) 1988-08-05 1988-08-05 Circuit for adjusting identified phase

Country Status (1)

Country Link
JP (1) JPH0244937A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000018077A1 (en) * 1998-09-18 2000-03-30 Kabushiki Kaisha Kenwood Radio digital signal receiver
WO2003103244A1 (en) * 2002-05-31 2003-12-11 松下電器産業株式会社 Data transmission system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000018077A1 (en) * 1998-09-18 2000-03-30 Kabushiki Kaisha Kenwood Radio digital signal receiver
US7529321B1 (en) 1998-09-18 2009-05-05 Kabushiki Kaisha Kenwood Radio digital signal receiver
WO2003103244A1 (en) * 2002-05-31 2003-12-11 松下電器産業株式会社 Data transmission system
US7286616B2 (en) 2002-05-31 2007-10-23 Matsushita Electric Industrial Co., Ltd. Data transmission system

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