JPH0244880A - Hold circuit - Google Patents

Hold circuit

Info

Publication number
JPH0244880A
JPH0244880A JP63195536A JP19553688A JPH0244880A JP H0244880 A JPH0244880 A JP H0244880A JP 63195536 A JP63195536 A JP 63195536A JP 19553688 A JP19553688 A JP 19553688A JP H0244880 A JPH0244880 A JP H0244880A
Authority
JP
Japan
Prior art keywords
circuit
amplifier
output
input
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63195536A
Other languages
Japanese (ja)
Inventor
Masanobu Shinoda
篠田 匡暢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP63195536A priority Critical patent/JPH0244880A/en
Publication of JPH0244880A publication Critical patent/JPH0244880A/en
Pending legal-status Critical Current

Links

Landscapes

  • Television Signal Processing For Recording (AREA)
  • Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To lower the distortion rate of a reproduced sound signal by providing a second amplifier and a second SW circuit to make the reproduced sound signal take a roundabout route without passing through an integration circuit constituted of a first SW circuit and a capacitor at ordinary time, and using a signal stored in the integration circuit during a period in which a noise is to be removed. CONSTITUTION:When the reproduced sound signal is inputted to an input terminal 1, the reproduced sound signal through an amplifier 6 is outputted to an output terminal 2 by the SW circuit 9. Besides, at the time of the switching to two sound heads fitted to a cylinder head, the reproduced sound signal have been inputted to the amplifier 4 is cut off by turning the SW circuit 8 off by inputting a switching signal from a switching control input terminal 10, and the amplifier 5 is driven by potential charged in a capacitor 7, and the output of the output level of the potential same as the potential charged in the capacitor 7 is outputted to the output terminal 2. Thus, the distortion rate of the reproduced sound signal can be lowered.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ホールド回路に関し、特に、VTRのHi−
Fi音声を復調とする時シリンダーヘッドに付いている
2つの音声ヘット切換え時に発生するノイズ期間をホー
ルドするホールド回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hold circuit, and in particular, to a hold circuit for a VTR.
This invention relates to a hold circuit that holds the noise period that occurs when switching between two audio heads attached to a cylinder head when demodulating Fi audio.

〔従来の技術〕[Conventional technology]

従来のホールド回路を第2図を用いて説明する。 A conventional hold circuit will be explained using FIG. 2.

第2図に示すホールド回路は、増幅器4の入力を入力端
1とし出力からSW回路8を介して、増幅器5とコンデ
ンサ7の一端に接続し、コンデンサ7の他端を低電位端
3に接続し、増幅器5の出力を出力端2としSW回路8
に切換制御入力をもつ構成となっていた。
In the hold circuit shown in FIG. 2, the input of the amplifier 4 is input terminal 1, the output is connected to the amplifier 5 and one end of the capacitor 7 via the SW circuit 8, and the other end of the capacitor 7 is connected to the low potential terminal 3. The output of the amplifier 5 is set as the output terminal 2, and the SW circuit 8
The configuration was such that it had a switching control input.

VTRcr)Hl−Fi音声を復調とする時、シリンダ
ヘットに磁気テープを回き付はアジマス録音されている
H i −F iのFM変調信号を2つの音声ヘッドを
切換える事にて連続信号として取り出しているが、2つ
の音声ヘッドが切換わった瞬間にHi−Fi音声のFM
変調信号がとぎれ再生音声信号に大きなノイズが発生す
る為、このノイズ期間たけ前記ホールド回路のSW回路
8を切換制御人力10より切換信号を入力してOFFさ
せボールド回路の入力端1に入力されていた再生音声信
号を遮断し、コンドンサ7にチャージされた電位にて後
段の第2の増幅器5を駆動し、出方端2にコンデンサ7
にチャージされた電位と同電位の出力レベルを出力して
いた。
VTR cr) When demodulating Hl-Fi audio, a magnetic tape is wound around the cylinder head, and the FM modulated signal of H i -Fi, which is azimuthally recorded, is extracted as a continuous signal by switching between two audio heads. However, the moment the two audio heads are switched, the Hi-Fi audio FM
Since the modulation signal is interrupted and a large noise is generated in the reproduced audio signal, the SW circuit 8 of the hold circuit is turned off by inputting a switching signal from the switching control human power 10 for the period of this noise, and the signal is input to the input terminal 1 of the bold circuit. The second amplifier 5 at the rear stage is driven by the potential charged in the capacitor 7, and the capacitor 7 is connected to the output end 2.
It was outputting an output level that was the same potential as the potential charged in it.

又、2つの音声ヘッドの内どちらが一方(磁気テープに
接触している側の音声ヘッド)が動作している時は、S
W回路8はONして、ホールド回路の入力に入った再生
音声信号を増幅器4と増幅器5を介して出力される。
Also, when one of the two audio heads (the one that is in contact with the magnetic tape) is operating, the S
The W circuit 8 is turned on, and the reproduced audio signal that has entered the input of the hold circuit is outputted via the amplifiers 4 and 5.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のホールド回路は、Sw回Fl@ 8がO
Nしている通常時、ONN抵抗上コンデンサ7によって
形成される積分回路のために、ホールド回路に入力再生
音声信号の周波数(f’N≧8KHz)によって歪率が
悪化するという欠点があった。
In the conventional hold circuit described above, Sw times Fl @ 8 is O
During normal operation, the hold circuit has a disadvantage in that the distortion rate worsens depending on the frequency of the input reproduced audio signal (f'N≧8KHz) due to the integration circuit formed by the ONN resistor and the capacitor 7.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のホールド回路は、第]、第2の増幅器の入力端
とし、該第1の出力を第1の8w回路を介して第3の増
幅器とコンデンサの一端に接続し、前期コンデンサの他
端を低電位端に接続し、前記第3の増幅器の出力を第2
のSW回路の第1−の入力に前記第2のSW回路の第2
の入力に接続し、該第2のSW回路の出力を出力端とし
、前記第1.第2のSW回路の切換制御入力を切換制御
端とすることを含で構成される。
The hold circuit of the present invention connects the first output to the third amplifier and one end of the capacitor via the first 8W circuit, and the other end of the first capacitor. is connected to the low potential terminal, and the output of the third amplifier is connected to the second
The second input of the second SW circuit is connected to the first input of the second SW circuit.
, the output of the second SW circuit is connected to the input of the first SW circuit, and the output of the second SW circuit is connected to the input of the first SW circuit. The switching control input of the second SW circuit is configured as a switching control terminal.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を示す回路図である。FIG. 1 is a circuit diagram showing an embodiment of the present invention.

入力端1から入力された再生音声信号は、第18.第2
の増幅器4,6の入力に入り、増幅器4の出力から第1
のSW回路8と第3の増幅器5を介して、第2のSW回
l¥89の第1の入力に入いる。
The reproduced audio signal input from the input terminal 1 is transmitted to the 18th. Second
from the output of amplifier 4 to the inputs of amplifiers 4 and 6.
It enters the first input of the second SW circuit 89 via the SW circuit 8 and the third amplifier 5.

又、増幅器6の入力に入った再生音声信号は、増幅器6
の出力より8w回路9の第2の入力に入り、SW回路9
の出力より8w回路9の第1又は第2の入力より入力さ
れた一方の信号を出力端子へ出力する。
Also, the reproduced audio signal input to the amplifier 6 is input to the amplifier 6.
It enters the second input of the 8W circuit 9 from the output of the SW circuit 9.
One of the signals inputted from the first or second input of the 8W circuit 9 is outputted to the output terminal.

又SW回1i48と増幅器5との接続点から、低電位端
子にコンデサ7を挿入する。
Also, a capacitor 7 is inserted into the low potential terminal from the connection point between the SW circuit 1i48 and the amplifier 5.

SW回路8とSW回路9の切換えのタイミングは、第1
.第2のSW回路8,9の切換制御入力へ接続している
切換制御入力端の切換信号に同期していてSW回路8が
OFFしている時は、SW回路9の出力にSW回路9の
第1の入力より入力された信号が出力され、SW回路8
がONしている時は、SW回路9の出力に回路9の第2
の入力より入力された信号が出力される。
The switching timing between the SW circuit 8 and the SW circuit 9 is the first
.. When the SW circuit 8 is OFF in synchronization with the switching signal of the switching control input terminal connected to the switching control input of the second SW circuit 8, 9, the output of the SW circuit 9 is The signal input from the first input is output, and the SW circuit 8
is ON, the second output of the circuit 9 is connected to the output of the SW circuit 9.
The signal input from the input is output.

上記構成で、入力端1に再生音声信号か入力された時、
出力端2にはSW回路9により増幅器6を介した再生音
声信号か出力される。
With the above configuration, when a playback audio signal is input to input terminal 1,
A reproduced audio signal via the amplifier 6 is outputted from the SW circuit 9 to the output terminal 2 .

又、シリンタヘッドに付いている2つの音声ヘードの切
換え時、出力端2にはSW回路8を切換制御入力端10
より切換信号を入力してOFFさせ、増幅器4に入力さ
れていた再生音声信号を遮断し、コンデンサ7にチャー
ジされていた電位にて、増幅器5を駆動し、出力端2に
コンデンサ7にチャージされた電位と同電位の出力レベ
ルが出力される。
Also, when switching between the two audio heads attached to the cylinder head, the SW circuit 8 is connected to the output terminal 2 and the switching control input terminal 10 is connected to the output terminal 2.
A switching signal is input to turn it off, cutting off the reproduced audio signal input to the amplifier 4, driving the amplifier 5 with the potential charged in the capacitor 7, and transmitting the signal charged to the capacitor 7 to the output terminal 2. The output level is the same as the potential that was applied.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に本発明は、ノイズを取り除く期間以外
では、すなわち、通常時第]、のSW回路とコンデンサ
で形成される積分回路に再生音声信号を通さず迂回させ
る第2の増幅器と第2のSW回路を設はノイズを取り除
く期間では積分回路に蓄積された信号を利用することで
、再生音声信号の歪率を大幅に改善できるという効果が
ある。
As explained above, the present invention provides a second amplifier and a second amplifier that bypass the reproduced audio signal without passing it through the integrating circuit formed by the SW circuit and the capacitor except during the noise removal period, that is, during normal times. By using the signal accumulated in the integrating circuit during the noise removal period, the SW circuit has the effect of greatly improving the distortion rate of the reproduced audio signal.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の一実施例を示す回路図、第2図は、
従来の一例を示す回路図である。 1・・・・・・入力端、2・・・・出力端、3・・・・
・・低電位端、10・・・・・切換制御端、4,5.6
・・・・・増幅器、7・・・・・コンデンサ、8,9・
・・・・・SW回路。 第 ? 厳
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a conventional example. 1...Input end, 2...Output end, 3...
...Low potential end, 10...Switching control end, 4,5.6
...Amplifier, 7...Capacitor, 8,9.
...SW circuit. No.? Strict

Claims (1)

【特許請求の範囲】[Claims] 第1、第2の増幅器の入力端とし、該第1の出力を第1
のSW回路を介して第3の増幅器とコンデンサの一端に
接続し、前期コンデンサの他端を低電位端に接続し、前
記第3の増幅器の出力を第2のSW回路の第1の入力に
前記第2のSW回路の第2の入力に接続し、該第2のS
W回路の出力を出力端とし、前記第1、第2のSW回路
の切換制御入力を切換制御端とすることを特徴とするホ
ールド回路。
The input terminals of the first and second amplifiers are the input terminals of the first and second amplifiers, and the first output is the input terminal of the first amplifier.
The third amplifier is connected to one end of the capacitor through the SW circuit, the other end of the capacitor is connected to the low potential end, and the output of the third amplifier is connected to the first input of the second SW circuit. connected to a second input of the second SW circuit;
A hold circuit characterized in that the output of the W circuit is an output terminal, and the switching control inputs of the first and second SW circuits are switching control terminals.
JP63195536A 1988-08-04 1988-08-04 Hold circuit Pending JPH0244880A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63195536A JPH0244880A (en) 1988-08-04 1988-08-04 Hold circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63195536A JPH0244880A (en) 1988-08-04 1988-08-04 Hold circuit

Publications (1)

Publication Number Publication Date
JPH0244880A true JPH0244880A (en) 1990-02-14

Family

ID=16342724

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63195536A Pending JPH0244880A (en) 1988-08-04 1988-08-04 Hold circuit

Country Status (1)

Country Link
JP (1) JPH0244880A (en)

Similar Documents

Publication Publication Date Title
KR900011329A (en) 4-channel surround sound generator
JPH0244880A (en) Hold circuit
JPS6057152B2 (en) magnetic tape playback device
JPH0320934Y2 (en)
JP2947416B2 (en) Hold circuit
KR100231448B1 (en) Switching noise removing method of hifi audio signal
JPH021685Y2 (en)
JPH0447798Y2 (en)
JP2813099B2 (en) Audio recording and playback circuit
JP2790049B2 (en) Recording device
JPH0253262A (en) Video signal recording circuit for video tape recorder
JPS6211086Y2 (en)
JP2726270B2 (en) Magnetic recording / reproducing device
JPH11163641A (en) Low power output device
JPS6018802A (en) Tape recorder
JPH0253260A (en) Sound signal recording circuit for video tape recorder
JPH0244572A (en) Demodulating circuit
JPS60197909A (en) Pcm magnetic reproducing circuit constituted of cmos invertor
JPS63106959A (en) Rotary head signal reproducing device
JPH03132969A (en) Video tape recorder
JPS62232206A (en) Limiter circuit
JPS58205903A (en) Magnetic recorder and reproducer
JPS5924406A (en) Magnetic recording and reproducing device
JPS60140501A (en) Signal reproducing device using rotary head
JPS6199903A (en) Magnetic sound recording and reproducing device