JPH0244572A - Demodulating circuit - Google Patents

Demodulating circuit

Info

Publication number
JPH0244572A
JPH0244572A JP19556588A JP19556588A JPH0244572A JP H0244572 A JPH0244572 A JP H0244572A JP 19556588 A JP19556588 A JP 19556588A JP 19556588 A JP19556588 A JP 19556588A JP H0244572 A JPH0244572 A JP H0244572A
Authority
JP
Japan
Prior art keywords
signals
signal
circuit
series
pll
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19556588A
Other languages
Japanese (ja)
Other versions
JP2710348B2 (en
Inventor
Masanobu Shinoda
篠田 匡暢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP19556588A priority Critical patent/JP2710348B2/en
Publication of JPH0244572A publication Critical patent/JPH0244572A/en
Application granted granted Critical
Publication of JP2710348B2 publication Critical patent/JP2710348B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To remove a rasping tone at the time of switching by supplying a series of FM signals through a PLL, which traces the change of a modulating wave and does not trace the raid change, to a demodulating circuit. CONSTITUTION:A series of the FM signals, which pass through a switch circuit 1, a buffer amplifier 2, a BPF3 and a limiter amplifier 4, to be successively switched and outputted are processed by a PLL5, which traces the frequency change by the modulating wave and does not trace the rapid change, of loop gain and damping factor. A signal to be locked by the FM signal, which is outputted from the PLL, is inputted to an FM modulator 6. Thus, an output signal, which is smoothly changed even during a switching period between the respective FM signals, is obtained and the rasping tone can be removed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は復調回路に関し、特にVTRのHiFi音声を
復調する時、シリンダーヘッドに付いている2つの音声
ヘッドからのFM信号を切換える時に発生する雑音を除
去する回路を含む復調回路に関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a demodulation circuit, and in particular, the present invention relates to a demodulation circuit, and in particular, when demodulating Hi-Fi audio of a VTR, the FM signal generated when switching between FM signals from two audio heads attached to a cylinder head. The present invention relates to a demodulation circuit including a circuit for removing noise.

〔従来の技術〕[Conventional technology]

従来、この種の復調回路は、第3図に示すように、シリ
ンダーヘッドの第1の音声ヘッドからの第1のFM信号
IN、と第2の音声ヘッドがらの第2のFM信号IN2
とを、切換制御信号Vsの制御のもとにスイッチ回路1
により切換えて一連のFM信号とし、バッファ増幅器2
、帯域フィルタ3及びリミッタ増幅器4を経てFM復調
器6へ入力し、FM復調器6で一連のFM信号を復調後
、バッファ増幅器7を介してホールド回路8へ入力し、
ホールド回路8はホールドパルス発生回路10からのホ
ールドパルスVHによりコンデンサC2と共に、スイッ
チ回路による第1及び第2のFM信号IN、、IN2の
切換え時にこれらFM信号IN、、IN2間の切換え直
前のレベルをホールドし、バッファ回路9を介して出力
する構成となっていた。
Conventionally, this type of demodulation circuit, as shown in FIG.
and the switch circuit 1 under the control of the switching control signal Vs.
to create a series of FM signals, and buffer amplifier 2
, input to the FM demodulator 6 via the bandpass filter 3 and limiter amplifier 4, and after demodulating a series of FM signals in the FM demodulator 6, input to the hold circuit 8 via the buffer amplifier 7,
The hold circuit 8, together with the capacitor C2, uses the hold pulse VH from the hold pulse generation circuit 10 to maintain the level immediately before switching between the first and second FM signals IN, IN2 when the switch circuit switches between the first and second FM signals IN, IN2. was held and outputted via a buffer circuit 9.

第4図はこの復調回路の各部信号の波形図である。FIG. 4 is a waveform diagram of signals of various parts of this demodulation circuit.

第1及び第2のFM信号IN、、IN2は、スイッチ回
路1により切換えられ一連のFM信号V、となったとき
、切換期間T1において不連続であり、かつレベルが急
激に低下するので、FM復調器6の出力信号、即ち復調
信号V。は切換期間T1で雑音(C)が発生する。
When the first and second FM signals IN, IN2 are switched by the switch circuit 1 to become a series of FM signals V, they are discontinuous in the switching period T1 and the level rapidly decreases. The output signal of the demodulator 6, ie, the demodulated signal V. Noise (C) occurs during the switching period T1.

この雑音を除去するために、ホールド回路8及びコンデ
ンサC1により、第1及び第2のFM信号IN1.IN
2間の切換え直前のレベルを切換期間T1だけホールド
する(D)ようになっている。
In order to remove this noise, the hold circuit 8 and the capacitor C1 control the first and second FM signals IN1. IN
The level immediately before switching between 2 and 2 is held for a switching period T1 (D).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の復調回路は、第1及び第2のFM信号I
N、、IN2切換え時に発生する雑音を除去するために
、切換期間T1だけ切換え直前のレベルをホールドする
構成となっているので、出力波形(OUT’ )に段差
を生じ、この出力信号を聴いたとき非常に耳ぎわすな音
になるという欠点がある。
The above-described conventional demodulation circuit is configured to convert the first and second FM signals I
In order to remove the noise that occurs when switching IN2, the level immediately before switching is held for the switching period T1, so there is a step in the output waveform (OUT'), which makes it difficult to listen to this output signal. The drawback is that the sound can be very harsh at times.

本発明の目的は、切換え時の耳ぎわすな音を除去するこ
とができる復調回路を提供することにある。
An object of the present invention is to provide a demodulation circuit that can eliminate harsh sounds during switching.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の復調回路は、複数の入力端からそれぞれ入力さ
れる複数のFM信号を順次切換えて一連のFM信号とし
て出力するスイッチ回路と、少なくとも前記各FM信号
の変調波による周波数変化には追従するが急峻な変化に
は追従しない所定のループ利得、ダンピング係数をもち
、前記スイッチ回路からの一連のFM信号を入力してこ
のFM信号にロックした信号を出力するP L I−回
路と、このPLL回路の出力信号を復調するFM復調器
とを有している。
The demodulation circuit of the present invention includes a switch circuit that sequentially switches a plurality of FM signals respectively inputted from a plurality of input terminals and outputs them as a series of FM signals, and a switch circuit that at least follows frequency changes due to modulated waves of each of the FM signals. A PLL circuit that has a predetermined loop gain and damping coefficient that does not follow sudden changes in the circuit, inputs a series of FM signals from the switch circuit, and outputs a signal locked to this FM signal, and this PLL circuit. and an FM demodulator that demodulates the output signal of the circuit.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.

この実施例は、第1及び第2の入力端から、シリンダヘ
ッドの第1の音声ヘッドからの第1のFM信号IN、及
び第2の音声ヘッドからの第2のFM信号IN2を入力
し、切換制御信号Vsの制御のもとにこれらFM信号I
NI、IN2を切換えて一連のFM信号とするスイッチ
回路1と、この一連のFM信号を帯域増幅し振幅制限す
るバッファ、増幅器2.帯域フィルタ3及びリミッタ増
幅器4と、位相比較器51.ループフィルタ52及び電
圧制御発振器53を備え、少なくとも第1及び第2のF
M信号IN、、IN2の変調波による周波数変化では追
従するが急峻な変化には追俊しないループ利得、ダンピ
ング係数をもち、リミッタ増幅器4からの一連のFM信
号Vlを入力してこのFM信号にロックした信号(V2
)を出力するPLL回路5と、このP L L回路5の
出力信号■2を復調するFM復調器6と、この復調器6
の出力信号を増幅するバッファ増幅器7とを有する構成
となっている。
This embodiment inputs a first FM signal IN from a first audio head of the cylinder head and a second FM signal IN2 from a second audio head from the first and second input ends, These FM signals I under the control of the switching control signal Vs
A switch circuit 1 that switches NI and IN2 to produce a series of FM signals, and a buffer and amplifier 2 that band-amplifies and limits the amplitude of this series of FM signals. A bandpass filter 3, a limiter amplifier 4, and a phase comparator 51. It includes a loop filter 52 and a voltage controlled oscillator 53, and includes at least a first and a second F
It has a loop gain and damping coefficient that follows the frequency changes caused by the modulated waves of the M signals IN, IN2, but does not follow steep changes. Locked signal (V2
), an FM demodulator 6 that demodulates the output signal 2 of this PLL circuit 5, and this demodulator 6.
The configuration includes a buffer amplifier 7 that amplifies the output signal of.

次に、この実施例の動作について説明する。Next, the operation of this embodiment will be explained.

第2図はこの実施例の動作を説明するための各部信号の
波形図である。
FIG. 2 is a waveform diagram of various signals for explaining the operation of this embodiment.

スイッチ回路1からリミッタ増幅器4までは従来と同様
に動作し、リミッタ増幅器4から、切換え時(TI)、
不連続でレベルが急激に低下した一連のFM信号■1が
出力される。
The switch circuit 1 to the limiter amplifier 4 operate in the same manner as before, and from the limiter amplifier 4, at the time of switching (TI),
A series of discontinuous FM signals (1) whose level rapidly drops is output.

PLL回路5は、電圧制御発振器53の出力信号V2 
(PLL回路5の出力信号でもある。)がリミッタ増幅
器4からの一連のFM信号V、に対して位相が90°ず
れた状態でロックし、ループ利得は比較的低く、ダンピ
ング係数は1.0以上として収束する時間をやや長くし
、各FM信号IN、、IN2の変調波による周波数変化
には追従するか急峻な変化には追従しないようになって
いる。
The PLL circuit 5 receives the output signal V2 of the voltage controlled oscillator 53.
(also the output signal of the PLL circuit 5) is locked with a phase shift of 90° to the series of FM signals V from the limiter amplifier 4, the loop gain is relatively low, and the damping coefficient is 1.0. As described above, the convergence time is made a little longer, and the frequency changes caused by the modulated waves of each FM signal IN, . . . IN2 are followed, but steep changes are not followed.

従って、FM信号IN、、IN2の切換期間T、におい
て、レベルが急激に低下したり信号が無くなって自走周
波数に戻る動作に入っても収束するのに時間がかかるの
で、すぐに次のFM信号(IN2)が入力されて不連続
とならずに次のFM信号(IN2)に追従するように動
作する((A)の部分)。
Therefore, during the switching period T of the FM signals IN, IN2, even if the level suddenly drops or the signal disappears and the operation returns to the free-running frequency, it takes time to converge, so the next FM signal is immediately switched on. When the signal (IN2) is input, it operates so as to follow the next FM signal (IN2) without becoming discontinuous (part (A)).

このようにして得られたPLL回路5の出力信号V2は
、FM復調器6により復調され、第2図最下段に示すよ
うに滑らかに変化する出力信号OUTとなる。
The output signal V2 of the PLL circuit 5 obtained in this way is demodulated by the FM demodulator 6, and becomes an output signal OUT that changes smoothly as shown in the bottom row of FIG.

なお、PLL回N5の過渡応答特性を急峻な変化に追従
可能な特性とすると、第2図最下段の(B)に示すよう
な段差を含む波形となり、従来例と同様に耳ぎわすな音
になってしまう。
If the transient response characteristic of PLL circuit N5 is made to be a characteristic that can follow sudden changes, the waveform will include a step as shown in (B) at the bottom of Figure 2, and as with the conventional example, it will produce a noise that does not disturb the ears. Become.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、一連のFM信号を、少な
くともFM信号の変調波による周波数変化には追従する
が急激な変化には追従しないPLL回路を通してF M
 IN調器へ伝達する構成とすることにより、各FM信
号間の切換期間においても滑らかに変化する出力信号を
得ることができ、この出力信号を聴いたとき、従来のよ
うな耳ぎわすな音を除去することができるという効果が
ある。
As explained above, the present invention transmits a series of FM signals through a PLL circuit that follows at least frequency changes caused by modulated waves of the FM signal, but does not follow sudden changes.
By adopting a configuration in which the signal is transmitted to the IN modulator, it is possible to obtain an output signal that changes smoothly even during the switching period between each FM signal, and when listening to this output signal, it does not produce a harsh sound like the conventional one. It has the effect of being able to remove.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すブロック図、第2図は
第1図に示された実施例の動作を説明するための各部信
号の波形図、第3図及び第4図は従来の復調回路の一例
を示すブロック図及び各部信号の波形図である。 1・・・スイッチ回路、2・・・バッファ増幅器、3・
・・帯域フィルタ、4・・・リミッタ増幅器、5・・・
PLL回路、6・・・FM復調器、7・・・バッファ増
幅器、8・・ホールド回路、9・・・バッファ増幅器、
10・・・ホールドパルス発生回路、51・・・位相比
較器、52・・ループフィルタ、53・・・電圧制御発
振器。
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram of various signals for explaining the operation of the embodiment shown in FIG. 1, and FIGS. 3 and 4 are conventional diagrams. FIG. 2 is a block diagram showing an example of a demodulation circuit and waveform diagrams of signals of various parts. 1... Switch circuit, 2... Buffer amplifier, 3.
... Bandpass filter, 4... Limiter amplifier, 5...
PLL circuit, 6...FM demodulator, 7...buffer amplifier, 8...hold circuit, 9...buffer amplifier,
DESCRIPTION OF SYMBOLS 10... Hold pulse generation circuit, 51... Phase comparator, 52... Loop filter, 53... Voltage controlled oscillator.

Claims (1)

【特許請求の範囲】[Claims] 複数の入力端からそれぞれ入力される複数のFM信号を
順次切換えて一連のFM信号として出力するスイッチ回
路と、少なくとも前記各FM信号の変調波による周波数
変化には追従するが急峻な変化には追従しない所定のル
ープ利得、ダンピング係数をもち、前記スイッチ回路か
らの一連のFM信号を入力してこのFM信号にロックし
た信号を出力するPLL回路と、このPLL回路の出力
信号を復調するFM復調器とを有することを特徴とする
復調回路。
A switch circuit that sequentially switches a plurality of FM signals respectively input from a plurality of input terminals and outputs them as a series of FM signals, and a switch circuit that at least follows frequency changes due to modulated waves of each FM signal, but does not follow sudden changes. a PLL circuit that has a predetermined loop gain and damping coefficient, and that inputs a series of FM signals from the switch circuit and outputs a signal locked to this FM signal; and an FM demodulator that demodulates the output signal of this PLL circuit. A demodulation circuit comprising:
JP19556588A 1988-08-04 1988-08-04 Demodulation circuit Expired - Fee Related JP2710348B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19556588A JP2710348B2 (en) 1988-08-04 1988-08-04 Demodulation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19556588A JP2710348B2 (en) 1988-08-04 1988-08-04 Demodulation circuit

Publications (2)

Publication Number Publication Date
JPH0244572A true JPH0244572A (en) 1990-02-14
JP2710348B2 JP2710348B2 (en) 1998-02-10

Family

ID=16343237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19556588A Expired - Fee Related JP2710348B2 (en) 1988-08-04 1988-08-04 Demodulation circuit

Country Status (1)

Country Link
JP (1) JP2710348B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5237495A (en) * 1990-05-23 1993-08-17 Fujitsu Limited Production/purchase management processing system and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5237495A (en) * 1990-05-23 1993-08-17 Fujitsu Limited Production/purchase management processing system and method

Also Published As

Publication number Publication date
JP2710348B2 (en) 1998-02-10

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