JPH0244815A - Output circuit - Google Patents

Abstract

PURPOSE:To give an output current without waste by automatically selecting an output driving capacity by means of a circuit which detects the change of an output signal due to an external load and a circuit which fluctuates the output driving capacity in accordance with the state of the external load and fixing the output driving capacity by means of an external signal. CONSTITUTION:When latch circuits 10 and 11 latch a high level, namely, when the delay of the output signal due to the external load is delayed later than the fall of AND 12 and 13, three state buffers 2 and 3 maintain an enable state, the output driving capacity is raised and the large current is given to outside through an output terminal 4. Since the three state buffers 2 and 3 come to a disable state when a low level is latched in the latch circuits 10 and 11, the output driving capacity is lowered and a small current is given to outside. When an objective output driving capacity can be obtained at that time, the enable signal of an external part is set to the low level and the output driving capacity is fixed. Thus, the output current without waste can be given.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit, particularly to an output circuit of a logic integrated circuit.

[Conventional technology]

The output circuit of a logic integrated circuit is required to drive an output signal to another logic integrated circuit. Logic integrated circuits that receive output signals require different current values to drive depending on their characteristics, so if the output circuit provides a small current and the receiving logic integrated circuit requires a large current, the receiving logic integrated circuit will not be driven. Conversely, when the output circuit applies a large current and the receiving logic integrated circuit requires a small current, the current flows excessively and wastes power consumption. Therefore, the output circuit is
The logic integrated circuits were often individually designed.

Regarding this issue, the application was filed on October 23, 1986 (62
-152560) output circuit can automatically select the output drive capacity according to the external load circuit and provides an efficient output current.

An example of the output circuit is shown in FIG.

In FIG. 3, a buffer 16 receives a signal from inside the logic integrated circuit and outputs a corresponding output current to an output terminal 19.
Supplied to the external load circuit via.

This buffer 16 has a three-state buffer 17゜18
are connected in parallel.

First, let's calculate the time delay between the input and output of the buffer 16 by [
'Detected by exclusive OR circuit C (hereinafter referred to as EXOR) 20. When this EXOR20 operates, EXOR20
Toshii state buffer control circuit 2
7.28 generates a control signal for a certain period of time depending on the delay amount of the delay circuit 21.23, and the three-state buffer 17
．． 18 to set the output drive capability and provide an efficient output current to the external load circuit.

[Problem to be solved by the invention]

In the conventional output circuit described above, the three-state buffer control circuits 27 and 28 enter a new operating state each time the output signal changes, so the output current may vary depending on influences other than external loads, such as voltage and temperature during operation. There is a risk that the external load circuit may not be driven stably.

An object of the present invention is to provide an output circuit for a logic integrated circuit that can automatically select the output drive capacity according to the state of an external load, further fix the output drive capacity by an external signal, and provide an efficient output current. It is about providing.

[Failure to solve the problem]

The output circuit of the present invention includes: a buffer that receives an input signal and supplies an output current corresponding to the input signal to an external load circuit; a detection circuit that detects a time delay between the input and output of the buffer; and a detection circuit that is connected in parallel with the buffer. at least one three-state buffer that is connected and whose operation and stop of its buffer function is controlled by an enable signal, and generates the enable signal according to the amount of delay in the detection circuit;
and at least one three-state buffer control circuit that stops or restarts its control operation upon receiving an external enable signal.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the output circuit of the present invention, which includes a buffer 1, two three-state buffers 2, 3, an output terminal 4, an EXOR 5, and two thinutate buffers 7 control circuits 14 and 15. It is composed of. The three-state buffer control circuit 14 and 15 include delay circuits 6 and 8,
EXOR7, 9 and logic integrated circuit (hereinafter referred to as AND)
It consists of 12.13.

In FIG. 1, a buffer l inputs a signal from inside the logic integrated circuit and supplies it to an external load circuit (not shown) via an output terminal 4.

The input side and output side of the buffer 1 are connected to the input of EXOR5, respectively, and the input side of buffer 1 and the outputs of delay circuits 6 and 8 for that input side are connected to the inputs of EXOR7 and 9, respectively.

EXOR7゜9 is applied to the AND12 and 13 inputs, respectively.
and an external enable signal. Also, the latch control signals of the latch circuits 10 and 11 are AND12.
The output side of EXOR5 is connected to the data signal, and the output side of latch circuits io and ii are connected to the enable signals of three-state buffers 2 and 3, respectively. are connected in parallel.

Next, the operation of this embodiment will be explained with reference to the timing chart shown in FIG.

As mentioned above, signals from within the logic integrated circuit are sent to buffers 1. An external load circuit is driven via the output terminal 4.

The delay time of the buffer 1 occurring at this time is detected by the EXOR 5 and is used as a signal on the output side of the EXOR 5 (shown in the second stage of FIG. 2). Here, the longer the delay time of the buffer 1, the wider the high level width of the signal on the output side of the EXOR 5 becomes.

Furthermore, when the signal level on the input side of the buffer 1 changes, signals on the output side of the EXORs 7 and 9 are generated using delay circuits 6 and 8. Here, since we will now set the output drive capability, the external enable signal is set to high level. Therefore, the signals on the output side of EXOR7 and EXOR9 are ANDI2. A
It is equal to the signal on the output side of NDI3 (shown in the third and fourth stages of FIG. 2).

The latch circuit 10.11 enters the through state due to the rise of the signal on the output side of AND12.13. 1llEXO
Outputs the signal on the output side of R5. Next, AND12
．． The latch circuits 10 and 11 latch the signal on the output side of EXOR5 according to the fall timing of the signal on the output side of EXOR5.

When the /% level is latched in the latch circuit 10.11, that is, the delay of the output signal due to the external load is A
When the falling edge of ND12 and ND13 is also delayed, the three-state buffers 2 and 3 maintain the enabled state and apply a large current to the outside through the output terminal 4 since the output driving ability is high.

On the other hand, when the low level is latched in the latch circuit 10.11, that is, when the delay of the output signal due to the external load causes the AND 12.13 to fall too quickly, the three-state buffers 2 and 3 are in the disabled state. Therefore, the output drive capability is low, so a small current is applied to the outside.

This sets the output drive capability until the next change in signal level on the input side of the buffer 1. At this time, when the desired output drive capability is obtained, the external enable signal is set to low level and the output drive capability is fixed. If it does not meet your expectations, set the output drive capacity again while leaving the NO level unchanged.

In the above description, as an example, two sets of three-state buffers and their three-state buffer control circuits are used, but the present invention is not limited to this.

In other words, at least one three-state buffer and its three-state buffer control circuit are used, and the setting range of the output drive capability can be changed depending on the number of three-state buffers, and the output drive capability can be adjusted according to the state of the external load. It is possible to obtain an output circuit of a logic integrated circuit that can automatically select and furthermore fix the output drive capability using an external signal to provide an efficient output current.

〔Effect of the invention〕

As is clear from the above description, the present invention automatically selects the output drive capability according to the state of the external load using a circuit that detects changes in the output signal due to the external load and a circuit that changes the output drive capability. Further, it is possible to obtain an output circuit of a logic integrated circuit whose output drive capability is fixed by an external signal and which can provide an output current with no waste.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of this embodiment, and FIG. 3 is a conventional circuit diagram. 1.16... Buffer, 2, 3, 17. 18... Three-state buffer, 4.19... Output terminal, 5,
7,9゜20.22.24...Exclusive OR circuit (E
XOR), 6.8, 21.23...delay circuit, 10,
11,25°26...Latch circuit, 12.13...
Logical product circuit (AND), 14.15, 27.28...
Three-state buffer control circuit. Agent Patent Attorney Otozuzu Uchihara

Claims (1)

[Scope of Claims] A buffer that receives an input signal and supplies an output current corresponding to the input signal to an external load circuit; a detection circuit that detects a time delay between the input and output of the buffer; connected in parallel with the buffer. at least one three-state buffer whose buffer function is operated and stopped by an enable symbol, and generates the enable signal according to an amount of delay in the detection circuit, and
and at least one three-state buffer control circuit that stops or resumes its control operation in response to an external enable signal.