JPH0244599A - Writing method for non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To largely reduce the stress of a semi-selective condition and to improve the reliability of E<2>PROM by simultaneously writing data in entire memory cells along a selected word line when the data are written in the E<2> PROM of an NAND cell system. CONSTITUTION:Plural pieces of memory cells M11, M12...M1024 able to rewrite are serially connected to constitute the NAND cell, matrix-arranged, the drains of one end part of respective NAND cells are connected to bit lines BL1, BL2...BL1024 and the control gates of respective memory cells M11, M12...M1024 are connected to word lines WL1, WL2...WL8. A writing circuit 6 is connected to the respective bit lines BL1, BL2...BL1024 through bit line boosters 41 and 42... and data latch circuits 31 and 32...etc. When the data are written by a circuit 5 and a raw decoder circuit 2, the data are simultaneously written into the memory cells M11, M12,...M1024 being connected to the selected word lines WLL, WL....

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention provides an FEE-free semiconductor memory device using an electrically rewritable memory cell having a charge retention portion in a gate insulating film. (E2 FROM), especially E2 which configures a NAND cell by directly connecting multiple memory cells in series.
This relates to a method of writing data in PROM.

(Prior Art) An E2 PROM in which a plurality of nonvolatile semiconductor memory cells are connected in series to form a NAND cell has been proposed (for example, Japanese Patent Application No. 1982-233944).

FIG. 6 is an equivalent circuit showing a part of the memory array of such a NAND cell type E2PROM. Bit line B
L21 is connected to one end drain of a NAND cell configured by series connection of four memory cells M211 to M214 in this example through a selection gate Sl. The memory cell is a MOS with a floating gate and a control gate.
It has a transistor structure. Bit line BL22. B
The same applies to L23°... one NAND
The control gates of memory cells M211-M214 constituting the cell are connected to different word lines WLI-WL4, respectively.

In this E2 FROM, first, batch erasing is performed by injecting electrons into the floating gates of all memory cells, and then data is sequentially written from the bottom of the NAND cells (away from the bit line). If I explain it specifically.

The erase operation is performed on all bit lines B L21. B L22.
... is OV (“L” level) and the 2 selection gate line SD
I.

and “H” boosted to all word lines WLI-WL4.
Apply a high level potential of, for example, 20 V. As a result, electrons are tunnel-injected from the substrate to the floating gate in all memory cells, and the threshold voltage is set to a high positive level of, for example, 20 V.
V, 1 select gate line SDI, '7-do line WLI-WL
Same as 3! , : 20 V and OV is applied to one selected word line WL4 as "L" level. As a result, the potential of the bit line BL21 is changed to that of the selection gate S1 and the memory cell M.
Memory cell M21 through channels 211 to M213
The signal is transmitted to the memory cell M214, where a high voltage is applied between the drain and the floating gate, and electrons are emitted from the floating gate, resulting in a "1" state with a low threshold.

Next, to write "1'" into the memory cell M213, bit line BL21. Select gate line SDI.

20V is applied to the word lines WLI and WL2, and the first selected word line WL3 and the word line WL4 at the position below which writing has already been performed are set to Ov. Due to this.

In the memory cell M213, a high voltage is applied between the floating gate and the drain as in the previous case, and "
1" writing is performed. In the memory cell M214 where writing has already been performed, the potential of the bit line is not transmitted to the drain and the control gate is also at the "L" level, so no writing or erasing occurs. Thereafter, in the same manner, writing is performed sequentially from the bottom of the NAND cells.

By the way, in the above write operation, there must be no erroneous write in other NAND cells driven by the same word line. For example, when writing to memory cell M213, word line WL3 becomes OV, so other memory cells M2Z3, M233 along this same word line WL3
, the control gate of M243 is also Ov. Therefore, in order not to rewrite the data in these memory cells, unselected bit lines BL22 to BL24 may be set to Ov. However, with such a potential relationship, other word lines W
L.I.

Since WL2 is 20V, unselected memory cells M221, M22 . ... enters the erase mode and over-erases, causing malfunction.

To avoid this, unselected bit lines B L 22.
B L 23. It is conceivable to apply an intermediate potential, for example 10V, to .... This allows unselected NAN
The memory cells in the D cell are either in a state where the electric field is small in the erase mode (FIG. 7(a)) or a state where the electric field is small in the write mode (FIG. 7(b)). These are, so to speak, semi-selected states.

Erroneous writing and over-erasing are prevented for the time being.

However, if stress in such a half-selected state is applied many times, the threshold value will gradually change and there is a great risk of malfunction. For example, consider a memory array in which the INAND cell is +1 formed by 8 memory cells, and 1024 memory cells are connected to one word line. As mentioned above, if all bits are sequentially written from the bit line farthest from the NAND cell bit line, when the memory cells connected to one word line are written 1024 times, one bit at a time, the memory cells are undergoes 1023 stresses. However, for the selected word line, “1°
This is the stress in the half-selected state in the write mode, and the stress along the unselected word line on the lipit line side is the stress in the half-selected state in the erase mode.

In the worst case, it is the last memory cell to be written to, 1023X 1 + 1024X 7-81
Stressed by 91 half-select erase conditions. This is E
2 It causes damage to the reliability of FROM.

(Problem to be solved by the invention) As described above, the conventional NAND cell type E2 FROM
However, there is a problem in that the writing operation is subject to the stress of a half-selected state, which tends to cause malfunctions.

The present invention has solved these problems. The present invention aims to provide a method for writing data into a NAND cell type E2 FROM.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a method for simultaneously writing data to all memory cells along one selected word line when writing data to a NAND cell type E2FROM. Features. Specifically, for example, the write cycle is divided into a data latch mode and a subsequent write mode, and the data latch mode
in mode.

All the data for one word line is held in advance in the data latch circuit connected to the 6-bit line, and then in the write mode, the data for one word line of these data latch circuits is transferred all at once to the memory cells along the selected word line. write to.

(Function) According to the present invention, during a write operation, all memory cells connected to one word line are written at the same time, so that only the memory cells along the unwritten word line become half-selected. Among these, only the memory cells along the bit line to which the data "Om" is applied (that is, maintain the erased state) are selected only once per word line selection.The memory cells that are in the half-selected state many times are On average, it is among those along the word line that is selected last, but still, for example, if an INAND cell is configured with 8 memory cells,
The maximum number of times the item is in a half-selected state is 8 times. Therefore, according to the present invention, highly reliable E2 FROM operation is possible.

(Example) Hereinafter, nine aspects of the present invention will be described in detail.

FIG. 1 is an equivalent circuit showing the main structure of an E2FROM according to an embodiment of the present invention. Here, memory array 1 is 8
8 x 1024 x 2-10 consisting of a sector in which 1024 NAND cells each consisting of memory cells are arranged in the word line direction, and a sector that is folded back.
, 384 bits are shown. In this embodiment, the memory cell is a nonvolatile memory cell constructed of a MOS transistor t14 having a floating gate and a control gate. Each NAND
The cell is.

The drain at the end is connected to the bit line BLI through the selection gate,
BL2. ..., and the source at the other end is connected to the ground potential via a selection gate.

The control gates of the 1024 memory cells arranged in the horizontal direction are as follows.

Word line WL (WLI, WL2,...) in common
It is connected to the. Word line WL is row decoder 2
Selected by Each bit line BL (BLI.

BL2. ...) has a data launch circuit 3 (3, .).

32,...) are provided, and these data latch circuits 3
The outputs of the bit line boosters 4 (41, 42, . . . ) are applied to the bit lines.

5 is an input/output (I10) circuit, and 6 is a write control circuit. In the figure, the sense amplifier provided for each bit line BL is omitted.

FIG. 2 shows more specifically the data latch circuit 3 and bit line booster 4 shown in FIG. Also the third
Figures (a) and (b) are timing diagrams showing each signal and node potential during a data write operation. The write operation in this embodiment will now be described with reference to these figures. Note that prior to the data write operation, all memory cells of one block are erased at once, as in the prior art.

The write cycle is performed by data latch and
It is divided into two stages: mode and write mode. In the data latch mode, 1024 pieces of data are latched into the data latch circuit 3 by toggling the write enable signal WE. In FIG. 3, when these 1024 pieces of data are "1", "0", "1", "0", etc. (in the figure, this is inverted as the signal I10, "0", "1",
'"0"1",...). That is, as shown in FIG. 3(a), first the WE is "
When WE goes low, data "0" enters the data latch circuit 31, and its output node N1 becomes 5V.Next, when WE goes low, data "1" enters the next data latch circuit 32. and its output node N2 is O
It becomes v.

Thereafter, data is sequentially latched into each data latch circuit 3 in the same manner. Then, after 1024 pieces of data are latched, the write signal WR goes to "L" level and enters the write mode. When entering the write mode, a program potential Vial) from an internal booster circuit (not shown) is output, and a ring oscillator (not shown) operates to obtain an oscillation output RING, which drives the bit line booster 4. . That is, the node N 1 r N3 with “H” level output
Bit line booster 41 + 43 + connected to...
works, bit lines BLI, BL3 . ... to Vpp-
Outputs 20V.

"L" level output node N2. N4. Bit line boosters 42, 44 . . . ...does not work.

Bit lines BL2 . BL4. . . ., only the intermediate potential generation circuit (MOSFET-Q+ in FIG. 2) operates to output an intermediate potential of 10 V to the bit line. -Rikitsutsu 3
As shown in Figure (b), in the write mode, the necessary selection gate line SDI is set to 20V, the other selection gate line SD2 is set to OV, the first selected word line WL8 is set to OV, and the remaining word lines WLI to WL7 are set to 20V. .

As a result, in the 1024 memory cells along the 1-selected word line WL8, the data potential 20V or 10V from the bit line is applied to the drain, and OV is applied to the control gate, and the data ``1'' or ``02'' is applied all at once. written. In other words, in the current case.

In memory cell M81, electron emission occurs from the floating gate,
Data "1°" is written. Since an intermediate potential is applied to the drain of the memory cell M12, there is almost no electron emission from the il floating gate during one write time of about 2 m5ec, and the erased state "0" is maintained. .

Similarly, word lines WL7, WL8, . . .
1024-bit data is written to each word line.

In this way, according to this embodiment, by writing data of 1024 bits for one word line at the same time, the number of times the state becomes half-selected can be greatly reduced compared to the conventional writing method. Malfunctions caused by state stress can be prevented.

In the above embodiment, data is latched by toggling the write enable signal WE, which is an external signal.
This may be done by an internal circuit.

FIG. 4 is an equivalent circuit illustrating an embodiment in which the data latch circuit 3 is controlled by the address control circuit 7. FIG. 5 is a timing diagram showing a write cycle when using this method.

In this embodiment, there is a data latch mode in which the write enable signal WE becomes "L" level at the beginning of the write cycle, and a write mode in which the write enable signal WE subsequently becomes "H" level and data is written.

First, when WE goes to the "L" level, data "0" is latched only in the data latch circuit to which the address is given. For example, the address is sensed at 20m5ec.

To write the data "0"1"0"1"..., give the column address of memory cell M81, the column address of M2S,..., the column address of M1023, and write the data latch circuit corresponding to these. to “0”
" is latched. All data latch circuits to which no address is given are held at "1".Then, the write enable signal WE becomes "H" level and enters the write mode.
As in the previous embodiment, one word line worth of data is simultaneously written into the memory cells.

It is clear that this practical example also provides the same effects as the previous embodiment.

[Effects of the Invention] As described above, according to the present invention, by writing data in a NAND cell type E2 FROM on one word line at the same time, stress in a half-selected state is greatly reduced, and reliability of the E2 FROM is improved. You can improve your performance.

[Brief explanation of the drawing]

FIG. 1 shows an E2 FR for explaining one embodiment of the present invention.
A diagram showing the configuration of the main part of OM, FIG. 2 is a diagram showing the specific configuration of a part of it, FIGS. 5 is a diagram showing the main part configuration of E2 FROM for explaining another embodiment, FIG. 5 is a timing diagram for explaining the write operation,
FIG. 6 is a diagram showing a NAND cell type E2 PROM cell array, and FIGS. 7(a) and 7(b) are diagrams showing the potential relationship of a memory cell in a half-selected state during writing. 1...Memory cell array, 2...Row decoder. 3...Data latch circuit, 4...Bit line booster. 6...Write control circuit, 7...Address control circuit M
ll, MI2. ...M1024...memory cell,
BLIBL2... B L 1024... Bit line, WLIWL2..., WL8... Word line. Applicant's representative Patent attorney Takehiko Suzue No. 2 Figure WE-SH1 1"-1↑゛-Cod-7+ Mode--Key-8L M7-
p(b) Figure (a) Figure (b)

Claims (3)

[Claims] (1) A control gate is formed on a semiconductor substrate via a gate insulating film, and a plurality of electrically rewritable memory cells each having a charge storage part in the gate insulating film are connected in series to achieve a NA
When writing data to a non-volatile semiconductor memory device configured as ND cells arranged in a matrix, with the drain at one end of each NAND cell connected to a bit line, and the control gate of each memory cell connected to a word line. A method for writing in a non-volatile semiconductor memory device, characterized in that data is written into all memory cells connected to a selected word line at the same time. (2) A control gate is formed on a semiconductor substrate via a gate insulating film, and a plurality of electrically rewritable memory cells having a charge storage part in the gate insulating film are connected in series to achieve a NA
ND cells are arranged in a matrix, the drain at one end of each NAND cell is connected to a plurality of bit lines arranged in one direction, and each bit line is provided with a data latch circuit to control each memory cell. When writing data to a non-volatile semiconductor memory device configured with gates connected to multiple word lines arranged in a direction that intersects bit lines, data for one word line is latched by toggling the write enable signal. A method for writing in a nonvolatile semiconductor memory device, characterized in that data is written simultaneously into all memory cells held in a circuit and connected to a selected word line. (3) A control gate is formed on a semiconductor substrate via a gate insulating film, and a plurality of electrically rewritable memory cells having a charge storage part in the gate insulating film are connected in series to achieve a NA
ND cells are arranged in a matrix, the drain at one end of each NAND cell is connected to a plurality of bit lines arranged in one direction, and each bit line is provided with a data latch circuit to control each memory cell. When writing data to a non-volatile semiconductor memory device in which a plurality of gates are arranged in a direction that intersects a word line and are connected to the word line, the address control circuit controls the data latch circuit to create a plurality of data latch circuits. A nonvolatile semiconductor memory device characterized in that data is inverted only in a data latch circuit to which an address is given, and then data is simultaneously written from these data latch circuits to all memory cells connected to a selected word line. How to write.