JPH0244447U - - Google Patents
Info
- Publication number
- JPH0244447U JPH0244447U JP1988123524U JP12352488U JPH0244447U JP H0244447 U JPH0244447 U JP H0244447U JP 1988123524 U JP1988123524 U JP 1988123524U JP 12352488 U JP12352488 U JP 12352488U JP H0244447 U JPH0244447 U JP H0244447U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- dedicated line
- transmission delay
- counter circuit
- detecting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims description 7
- 238000001514 detection method Methods 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Maintenance And Management Of Digital Transmission (AREA)
- Monitoring And Testing Of Transmission In General (AREA)
Description
第１図は本考案のデジタル伝送における専用回
線の伝送遅延時間増加の検出回路を付加したデジ
タル伝送系の回路図、第２図は第１図に示すデジ
タル伝送系の信号のやり取りを示した図、第３図
はマスター側の処理フロー図、第４図はスレーブ
側の処理フロー図である。第５図は従来のデジタ
ル伝送系の回路図である。
１……マスター側制御部、２……変調回路部、
３……復調回路部、４……スレーブ側制御部、５
……復調回路部、６……変調回路部、７……専用
回線、８……設定回路、９……アラーム表示回路
、１０……カウンタ回路。
Figure 1 is a circuit diagram of a digital transmission system to which a circuit for detecting the increase in transmission delay time of a dedicated line in digital transmission of the present invention is added, and Figure 2 is a diagram showing the exchange of signals in the digital transmission system shown in Figure 1. , FIG. 3 is a processing flow diagram on the master side, and FIG. 4 is a processing flow diagram on the slave side. FIG. 5 is a circuit diagram of a conventional digital transmission system. 1... Master side control section, 2... Modulation circuit section,
3... Demodulation circuit section, 4... Slave side control section, 5
... Demodulation circuit section, 6 ... Modulation circuit section, 7 ... Dedicated line, 8 ... Setting circuit, 9 ... Alarm display circuit, 10 ... Counter circuit.
Claims (1)
出方法において、受信側にカウンタ回路を用意し
、送信側には前記カウンタ回路を設定する回路を
設けることにより遅延の検出を行うことを特徴と
するデジタル伝送における専用回線の伝送遅延検
出回路。 A method for detecting an increase in transmission delay due to switching of a dedicated line, characterized in that a counter circuit is provided on the receiving side, and a circuit for setting the counter circuit is provided on the transmitting side to detect the delay. A dedicated line transmission delay detection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988123524U JPH0244447U (en) | 1988-09-22 | 1988-09-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988123524U JPH0244447U (en) | 1988-09-22 | 1988-09-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0244447U true JPH0244447U (en) | 1990-03-27 |
Family
ID=31372456
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988123524U Pending JPH0244447U (en) | 1988-09-22 | 1988-09-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0244447U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0486029A (en) * | 1990-07-30 | 1992-03-18 | Nippon Motoroola Kk | System for detecting change of line delay amount |
-
1988
- 1988-09-22 JP JP1988123524U patent/JPH0244447U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0486029A (en) * | 1990-07-30 | 1992-03-18 | Nippon Motoroola Kk | System for detecting change of line delay amount |