JPH0243771A - Manufacture of insulated gate type semiconductor element - Google Patents

Abstract

PURPOSE:Not only to alleviate the ruggedness of a polycrystalline silicon surface, which is made to serve as an active region, so as to eliminate a gate failure due to a short circuit but also to improve a semiconductor element in electrical properties such as a carrier mobility and the like by a method wherein a polycrystalline silicon film is formed in film as thick as a specified value or more, which is covered with a cap layer and subjected to a heat treatment at a high temperature and whose surface is flattened. CONSTITUTION:In the manufacture of an insulated gate type semiconductor element provided with a polycrystalline silicon layer 3, serving as an active region deposited on an insulating layer 2, deposited on an insulating layer 2, the polycrystalline silicon layer 3 is formed in film as thick as more than 0.5mum. Then, after the surface of the polycrystalline silicon layer 3 is flattened, the vicinity of the flattened surface of the silicon layer 3, which is thicker than 0.5mum, is made to serve as a channel region 3b-2, and a gate electrode 5 is formed on the region 3b-2 through the intermediary of a gate insulating film 4 and concurrently a drain region 3b-1 and a source region 3b-2 are formed inside the polycrystalline silicon layer 3 so as to be connected to the channel region 3b-2.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention is directed to so-called 5ol (Silicon
The present invention relates to a method for manufacturing an insulated gate type semiconductor device having an nOn Insulator structure.

[Conventional technology]

From the perspective of improving the functionality of semiconductor devices, multiple functions on a single chip are being considered. As a means for achieving this, an SOI structure using polycrystalline silicon as an active region of a device is considered to be promising because it is easy to apply conventional processes. However, since this polycrystalline silicon is usually formed in a thin film state by CVD, vapor deposition, etc., it is difficult to reduce the unevenness of its surface by mechanical polishing as with single-crystal bulk silicon.

[Problem to be solved by the invention]

For this reason, if polycrystalline silicon is applied as it is to the active region of, for example, an MO5 structure, the asperity of the gate oxide film will be degraded, causing a gate short circuit failure. Also,
Although this does not result in device destruction, there is a risk that device characteristics may deteriorate due to scattering of carriers due to unevenness on the surface of the oxide film and polycrystalline silicon.

An object of the present invention is to alleviate gate short circuit defects and carrier movement by alleviating irregularities on the surface of polycrystalline silicon in a method for manufacturing an insulated gate type semiconductor device using a polycrystalline silicon layer deposited on an insulator as an active region. The objective is to improve electrical characteristics such as power.

[Means to solve the problem]

In order to achieve the above object, the method of manufacturing an insulated gate semiconductor device of the present invention is a method of manufacturing an insulated gate semiconductor device using a polycrystalline silicon layer deposited on an insulator as an active region, comprising: a step of forming the polycrystalline silicon layer with a thickness of more than 0.5 μm; a step of forming a camp layer to cover the surface of the polycrystalline silicon layer, and then performing a high-temperature heat treatment in an inert atmosphere; A step of planarizing the surface of the polycrystalline silicon layer, the film thickness of which is thicker than 0.5 μm, the vicinity of the surface of the polycrystalline silicon layer with the planarized surface is used as a channel region, and gate insulation is formed on the channel region. The method is characterized by comprising a step of forming a gate electrode through a film, and forming a drain region and a source region connected to the channel region in the polycrystalline silicon layer.

[Action/Effect]

Therefore, according to the present invention, since the thickness of the polycrystalline silicon layer to be deposited is thicker than 0.5 μm, it is not energetically stable and the 110> crystal axis is highly oriented perpendicular to the film surface. Furthermore, since the high-temperature heat treatment is performed in an inert atmosphere, the crystal grains of the polycrystalline silicon layer can be increased in size.

Therefore, when a semiconductor element is formed using this polycrystalline silicon layer, the electrical characteristics of the element itself are improved.

By flattening the surface of the polycrystalline silicon layer, electrical properties such as carrier mobility are further improved, and the gate insulating film formed on top of it is of high quality, resulting in gate dielectric breakdown voltage. will improve.

〔Example〕

Hereinafter, the present invention will be explained using embodiments shown in the drawings.

FIG. 1 shows a first embodiment in which the present invention is applied to an N-channel MO3I transistor, and FIG. 2 shows the process of forming a polycrystalline silicon layer. In FIG. 1, ■ is a substrate made of single crystal silicon, and 2 is an oxide film 5i having an insulating property.
nt. 3 is a polycrystalline silicon layer formed on the oxide film 2. As shown in the figure, this polycrystalline silicon layer 3 is composed of two layers 3a and 3b depending on the deposition process.

3a is a fine and randomly oriented polycrystalline silicon layer at the initial stage of deposition, while 3b has a film thickness of 0.5 μm.
This is a polycrystalline silicon layer having a columnar structure with a <110> axis oriented substantially perpendicular to the film surface, which is formed when a deposition amount of m or more is generated. 3b- in polycrystalline silicon 13b
1 and 3b-3 are N″ which become the drain and source, respectively.
3b-2 is a P-type channel region. Furthermore, in FIG. 1, 4 is a gate insulating film, 5 is a gate, 6 is an interlayer insulating film, 7 is a gate electrode, 8 is a source electrode, and 9 is a drain electrode.

The channel region 3b-2 is a portion that connects the source region 3b-3 and the drain region 3b-1 by forming an inversion layer and becomes a path for carriers to pass through when the transistor is turned on. This is the active region.

Therefore, this active region (channel region 3b-2) has good crystallinity, that is, there are few grain boundaries,
Furthermore, it is required that there be fewer internal defects within one crystal.

The process of forming polycrystalline silicon layer 3 will be explained in detail with reference to FIG. First, an oxide film 2 is formed on a single crystal silicon substrate 1 by a thermal oxidation method (FIG. 2(a)), and then a 1.5 μm thick film is formed on the oxide film 2 by a low pressure CVD method at a temperature of 610"C. A polycrystalline silicon layer 3 is formed (FIG. 2(b)).
). At this time, in the initial state when the deposition of the polycrystalline silicon layer 3 is started, fine crystal nuclei are formed in a randomly oriented state. In this case, the thickness of polycrystalline silicon layer 3 is less than 0.5 μm. As the deposition continues, among the randomly oriented crystals, crystals oriented along the 110> axis without energetic stability perpendicular to the film surface preferentially grow. Therefore, crystal grains with other axis orientations are prevented from growing. When the deposition continues and the thickness of the polycrystalline silicon layer 3 reaches a predetermined thickness (0.5 μm) or more, the portion near the surface of the polycrystalline silicon layer 3 becomes <110>.
Only axially oriented crystals are present. In this case, since each crystal near the film surface grows almost perpendicularly to the film surface, each crystal is formed into a columnar shape when viewed in a longitudinal section. Furthermore, the surface 3c of the polycrystalline silicon layer 3 becomes more irregular as its thickness increases.

Next, polycrystalline silicon film 3 during high-temperature heat treatment to be described later.
1050 in an oxygen atmosphere to prevent loss of
The surface 3 of the polycrystalline silicon film 3 is heat treated at a temperature below °C.
A camp oxide layer 10 is formed on the polycrystalline silicon layer 3 (FIG. 2(C)), and then heat treatment is performed at a high temperature of 1200°C in an inert atmosphere to enlarge the crystal grains of the polycrystalline silicon layer 3 (second
Figure (d)). At this time, the grain size of the polycrystalline silicon N3 grows to about 2 μm through this high-temperature heat treatment process. Note that the minimum thickness of the cap oxide layer IO is preferably 500 Å or more.

Subsequently, thermal oxidation was performed in an oxygen atmosphere to obtain a film thickness of 500 mm.
A thermal oxide film 11 of 100% is formed (FIG. 2(e)). At this time, the unevenness of the surface 3c of the polycrystalline silicon 3 before oxidation is inherited by the surface of the thermal oxide film 11 after oxidation, but the surface 3d of the polycrystalline silicon film 3 after oxidation is almost uniformly oxidized. In order to advance horizontally, the uneven shape is flattened and the uneven height (pe
ak to peak) will be approximately 210 people.

Thereafter, the thermal oxide film 11 is removed using a hydrochloric acid-based etching solution to expose the polycrystalline silicon film 3 (FIG. 2(f)).
). After that, a gate insulating film 4, as shown in FIG.
Gate 5, interlayer insulating film 6, source 3b-3, drain 3
b-1, a gate electrode 7, a source electrode 8, and a drain electrode 9 are sequentially formed.

Therefore, the effects of this embodiment manufactured as described above will be explained below.

FIG. 3 shows the relationship between the electron spin density, which indicates the film quality of the polycrystalline silicon layer, and its film thickness. Since electron spins are localized at grain boundaries and crystal defect areas, a large number of electron spins, that is, a high electron spin density, means that there are many defects and the film quality is poor.

According to Figure 3, in a polycrystalline silicon layer, when the film thickness is less than 0.5 μm, the electron spin density increases and the film quality deteriorates, but when the film thickness becomes 0.5 μm or more, the electron spin density decreases. It has the characteristic that it becomes saturated at a certain lower limit value and improves reforming. According to this characteristic, the thickness of the polycrystalline silicon layer is generally 0.5
If the thickness is .mu.m or more, a region with good crystallinity can be formed in the vicinity of the film surface.

Therefore, as described above, the polycrystalline silicon N3 is deposited to have a film thickness of 0.5 μm or more, and as a result, a gate insulating film using a deposited portion having a thickness of 0.5 μm or more is formed. The region near the interface with 4, that is, the active region, has good crystallinity.It should be noted that the polycrystalline silicon layer 3 with good crystallinity is used as the active region, and a channel region is formed in that region. Therefore, the thickness of the polycrystalline silicon layer 3 is naturally determined by considering the channel region.The depth of the channel region in the thickness direction of the polycrystalline silicon layer 3 is determined mainly by the gate voltage applied to the gate 5 Voltage VG
The value depends on the impurity concentration and is approximately several hundred. Therefore, in the MOS transistor manufactured in the above embodiment, the thickness of the polycrystalline silicon layer 3 must be 0.5 μm or more than 1000 Å.

In the above embodiment, by heat-treating the polycrystalline silicon, internal defects such as twins existing in the polycrystalline silicon layer 3b near the surface can be eliminated and crystal grains can be further enlarged.

This is because the interfacial energy density of the grain boundaries is reduced because the degree of randomness in three dimensions is reduced to the degree of two-dimensional randomness only in the plane, and the activation energy during fusion is also reduced accordingly. it is conceivable that.

On the other hand, in the polycrystalline silicon 3a in the lower part of the film, the grain size before heat treatment is small and has three-dimensional randomness, so although internal defects are eliminated, crystal growth is slower than in the upper part 3b of the film.

FIG. 4 shows the relationship between spin density and heat treatment conditions for polycrystalline silicon having a film thickness of 1.5 μm. Heat treatment temperature 1100°C
If this is the case, the spin density will drop rapidly within a short period of time. The heat treatment time reaches saturation in about 30 minutes. Therefore, the heat treatment conditions are preferably at a temperature of 1000° C. or higher for 15 minutes or longer, preferably at 1000° C. or higher for 30 minutes or longer. In this example, the polycrystalline silicon layer was heat-treated in a nitrogen atmosphere, but the heat treatment is not limited to a nitrogen atmosphere, and any inert atmosphere may be used. In addition, although the heat treatment temperature was only up to 1200°C in this example,
It is easily expected that the spin density decreases as the temperature increases. However, if the temperature exceeds the melting point of silicon, stress is expected to increase due to melting and recrystallization, so the maximum heat treatment temperature is preferably 1400°C.

5 and 6 show the surface 3d of the polycrystalline silicon layer 3.
3 is a diagram obtained by simulation of the relationship between the thickness of the thermal oxide film 11 formed in the oxidized film and the unevenness height (asperity) of the surface of the polycrystalline silicon layer 3 after oxidation. FIG. Assuming that thermal oxidation proceeds isotropically and considering that the envelope connecting concentric circles from each point corresponds to the surface shape of polycrystalline silicon N3, the height of the unevenness before oxidation is Ho, and the unevenness before oxidation is When the pitch and the thickness of the thermal oxide film 11 are r, the height of the unevenness after oxidation (asperity) H is given by the following formula.

...... (1) (Hereinafter, blank) Here, in the above example, the film thickness of the polycrystalline silicon layer 3 formed as described using FIG. 2(b) was 1.
5 μm, and as a result of cross-sectional TEM observation of this 1.5 μm thick polycrystalline silicon layer 3, L'.

3000 people, Ho#1000 people, so as the initial conditions L = 3000 people, H, = 1000 people above (2
), the relationship shown in (a) in FIG. 5 is obtained. As can be seen from this graph, the thicker the thermally oxidized Mill film is, the smaller the height of the unevenness is.

Further, in this example, when the film thickness is approximately 3000 or more, the value of the unevenness height tends to be saturated.

In Figure 5, graph (b) has an initial condition of L=3000.
people, Ho-500 people, graph (C) is L = 3000 people,
The relationship is obtained by substituting H,=2000 people, and the graph shown in FIG. 6 is the relationship for the polycrystalline silicon layer 3 with a film thickness of 4.5 μm, and the initial condition L determined by cross-sectional TEM observation.
= 6000 people and Ho = 2500 people are substituted into the above formula. As can be seen from these relationships, the thicker the polycrystalline silicon layer 3 to be formed, the larger the height of the unevenness becomes. It also needs to be thicker.

After the process explained using FIG. 2(f), a gate oxide film of 1,000 layers is formed by a thermal oxidation method, a phosphorus-doped polycrystalline silicon gate is formed on this to form a MOS capacitor, and a gate oxide film is formed. The relationship between the dielectric breakdown voltage and the etching amount of the polycrystalline silicon layer 3 is shown in FIG. The amount of etching of the polycrystalline silicon layer 3 corresponds to approximately half the thickness of the thermal oxide film 11 in this embodiment. When etching is not performed (etching amount = 0 μm), that is, when the thermal oxide film 11 is not formed, the unevenness is severe, and
Due to pinholes caused by flakes and the like during polycrystalline silicon deposition, the gate dielectric breakdown voltage becomes approximately 0, and no device can be formed. On the other hand, according to this characteristic, 0.25
When etching is performed by more than μm (the thermal oxide film 11 is etched by about 50 μm or more)
Since the surface of the polycrystalline silicon layer 3 is planarized, a high-quality gate insulating film can be formed, and the gate dielectric breakdown voltage is improved.

Next, a second embodiment of the present invention will be described using FIG. 8.

In this example, the steps not shown in FIGS. 8(a) to 8(d) are shown in FIGS. 2(a) to (d) explained in the first example.
This corresponds to the step shown in d), and similar steps can be applied, so the same components are given the same reference numerals and their explanations will be omitted.

This example is an example in which etch hacking is used as a method for flattening the surface. First, after the step shown in FIG. to expose the surface 3C (Fig. 8(e)
). Next, a resist 12 is applied onto the polycrystalline silicon 3 using a spinner to flatten the resist surface. At this time, the film thickness of the resist 12 needs to be greater than the height of the unevenness of the surface 3C of the polycrystalline silicon layer 3 so that it can be sufficiently flattened (see FIG. 8). Next, resist 1 is etched by dry etching.
Etching is performed so that the etching rates of resist 12 and polycrystalline silicon 3 are the same (Figure 8 (chain). If the surface of polycrystalline silicon 3 is removed using this etch bank, the surface shape of resist 12 will be the same as that of polycrystalline silicon 3 after dry etching. Since the surface 3e of the crystalline silicon layer 3 is inherited, it can be made flat.

In this embodiment, a resist is used for etch hacking, but the material is not limited to resist as long as it has the same etching rate as polycrystalline silicon and can be coated with a spinner to produce a flat surface.

Furthermore, although the first and second embodiments use individual planarization means, they may be used in combination.

Although the present invention has been described above using the first and second embodiments, the present invention is not limited thereto, and can be modified in various ways, for example as shown below, without departing from the spirit thereof. be.

■In the above first embodiment, the film thickness of the polycrystalline silicon layer 3 (the state shown in FIG. 2(f)) to be finally formed should be thicker than 0.5 μm considering the depth of the channel region. Although this is a good product, the thicker the film, the larger the step difference between the polycrystalline silicon layer 3 and the oxide film 2, which causes problems such as the interconnections formed later being more likely to break. Therefore, it is desirable to make the thickness of the polycrystalline silicon layer as thin as possible within the above range, but according to this first embodiment, the film is formed to a thickness of 1.5 μm in the process shown in FIG. 2(b). The final film thickness of the polycrystalline silicon layer 3 is 0.5 μm.
In order to achieve this level, a thermal oxide film 11 of about 2 μm must be formed in the step shown in FIG. 2(e). However, it takes a long time to form a thermal oxide film of about 2 μm using the thermal oxidation method, which is disadvantageous in terms of process.

Therefore, in such a case, after the step shown in FIG. 2(d), the polycrystalline silicon layer 3 is first etched to about 1 μm by dry etching, and then a thermal oxide film of about 0.5 μm is etched by thermal oxidation. , and then remove the thermal oxide film. This process uses dry etching which can perform etching at a relatively high speed, and since the thermal oxide film only needs to be formed to a thickness of about 0.5 .mu.m, the overall time is shortened and the process is advantageous.

(2) In the above embodiment, the cap oxide layer 10 obtained by oxidizing the polycrystalline silicon layer 3 is used as the cap layer, but other layers such as a nitride layer (Si, N4) may be used.

■In the above embodiment, the polycrystalline silicon layer according to the present invention is
Although we have explained an example in which it is applied to a type channel MO3h transistor, it can also be applied to a P type channel MOS transistor or an IG
The present invention can be similarly applied to other insulated gate type semiconductor devices such as BT.

■In the above example, thermally oxidized SiO□, which is obtained by thermally oxidizing silicon, was used as the underlying insulator, but it has insulating properties,
Any material (such as a glass substrate) that can withstand high-temperature heat treatment can be used.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention using polycrystalline silicon MO3I.
- A sectional view of a main part of a transistor; FIGS. 2(a) to 2(f) are sectional views for explaining the manufacturing method of the first embodiment of the present invention;
Figure 3 is a characteristic diagram showing the relationship between polycrystalline silicon layer thickness and electron spin density, Figure 4 is a characteristic diagram showing the relationship between heat treatment time and spin density, and Figures 5 and 6 are Figure 7 is a diagram showing the relationship between the thickness of the oxide film and the height of unevenness on the surface of the polycrystalline silicon layer obtained by simulation. 8(a) to (□□□ are cross-sectional views for explaining the manufacturing method of the second embodiment of the present invention. ■... Single crystal silicon substrate, 2... Oxide film, 3...
・Polycrystalline silicon layer, 3b-1...Drain, 3b-
2...Channel jlJ, 4. 3b 3... Source, 4... Gate insulating film, 5... Gate 1-, 10.
...Cap oxide layer.

Claims (1)

[Claims] A method for manufacturing an insulated gate semiconductor device using a polycrystalline silicon layer deposited on an insulator as an active region, the method comprising: forming the polycrystalline silicon layer with a thickness thicker than 0.5 μm. forming a cap layer to cover the surface of the polycrystalline silicon layer, and then performing high temperature heat treatment in an inert atmosphere; planarizing the surface of the polycrystalline silicon layer; and determining the thickness of the polycrystalline silicon layer. A channel region is formed near the surface of the polycrystalline silicon layer having a thickness of 0.5 μm or more and a flat surface, and a gate electrode is formed on the channel region via a gate insulating film, and 1. A method of manufacturing an insulated gate semiconductor device, comprising the step of: forming a drain region and a source region connected to the channel region within the channel region.