JPH0243608A - Method for pealing with disconnection of system clock - Google Patents

Abstract

PURPOSE:To control a card by an internal clock held by the card even when a system clock signal is interrupted by sending a clock turning-off detecting signal to a bus enable and mask-controlling a bus interface. CONSTITUTION:When a system is monitored by a clock turning-off detecting part 9 and a system clock is contained, a system clock is inserted through a clock switching part 8 to a control block 4 as it is. When a system clock generates the clock turning-off, an internal clock 5 is put through the clock switching part 8 to the control block 4. Simultaneously, a bus enable 7 is controlled by the clock turning-off detecting signal, the enable of the bus is masked and a terminal interface card 1 itself is separated from a system. Namely, a bus interface 6 is made into the non-operation and the transmission/reception of the data from a data bus are not executed. Thus, when the system clock is turned off, a card is electrically separated from the system automatically and self-travelling can be executed by the clock in the internal part of the card.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for dealing with system clock interruption in a terminal interface, the purpose of this terminal interface card is to automatically switch to the internal clock of the device when the external system clock is interrupted. A bus interface that relays data between the terminal device and the data bus, a control block that controls the terminal interface card using signals from the device control card for system control, and a clock disconnection detection circuit that monitors disconnection of the system clock from the outside. The clock interruption detection circuit includes a clock switching section and a clock interruption detection section, and controls the clock switching section by a clock interruption detection signal from the clock interruption detection section when the external system clock is interrupted. The system clock is switched to an internal clock and supplied to the control block, and the clock disconnection detection signal is sent to the bus enable to perform mask control on the bus interface.

be controlled. A system clock signal is also commonly connected to each terminal interface card, and controls the timing signal for each card. Therefore, conventionally, if this system clock is interrupted due to a failure or the like, each card cannot be controlled.

[Industrial application field]

The present invention relates to a method for dealing with system clock interruption in a terminal interface.

Communication devices usually operate based on a basic clock. This clock is called the system clock (SCLK).
It is used to set the timing for data communication and control of the terminal interface cards that make up the device.

An example of a system configuration diagram of the communication device is shown in FIG. In the figure, there is a terminal interface card as a card that constitutes the communication device, each terminal interface card is individually connected to the terminal device and digitally connected to the communication line by a data bus, and each card is commonly connected to the system by the device control card. [Prior Art] A circuit diagram of a conventional terminal interface is shown in FIG. In the figure, 1 is a terminal interface card, 2 is a terminal device, 3 is a device control card, 4 is a control block, 5 is an internal clock, and 6 is a bus interface.

The system clock signal 5CLK is supplied to the control block 4 of each terminal interface card 1 as a clock signal for system control, and is a timing signal for data communication and control of each card under the control of the device control card 3 common to each card. is created. The internal clock 5 is a clock signal of the number Mllz class of the device common power supply, and supplies clocks to the flip-flop circuit, memory circuit, etc. of the control block 4. The control block 4 is a control device including a memory, a counter, etc., and controls the bus interface 6 to control the direction of data transmission and reception between each terminal device 2 and the data bus.

In the above circuit, the system clock signal 5CLK and the internal clock signal 5 are separate clock signals, and if the system clock signal 5CLK stops, even if the internal clock signal 5 is present, system control of each card cannot be performed.

[Problem to be solved by the invention]

As described above, in a conventional card, if the system clock signal 5CLK is interrupted, the system of the card cannot be controlled at all.

Therefore, it is an object of the present invention to enable the card to be controlled using the internal clock of the card even if the system clock signal 5CLK is interrupted.

[Means to solve the problem]

FIG. 1 shows the principle configuration diagram of the present invention. In the figure, 1 is a terminal interface card, 2 is a terminal device, 3 is a device control card, 4 is a control block, 5 is an internal clock, 6 is a bus interface, 5 is a bus enable, 8 is a clock switching unit, and 9 is a A clock disconnection detection circuit 10 shown by a dotted line is a circuit added according to the present invention, which detects disconnection of the system clock signal 5CLK, switches to the internal clock 5, and supplies it to the control block 4. A clock disconnection detection signal is sent to the bus enable 7.

[Effect]

The system clock 5CIJ is monitored by the clock disconnection detection section 9, and if the system clock 5CLK is present, the system clock 5CLK is directly inserted into the control block 4 through the clock switching section 8. system clock 5
When a clock interruption occurs in CLK, the internal clock 5 is input to the control block 4 through the clock switching section 8, and at the same time, the bus enable 7 is controlled by the clock interruption detection signal from the clock interruption detection section 9. Enable is masked and the terminal interface card 1 itself is disconnected from the system. That is, the bus interface 6 is made inactive so that data cannot be sent or received from the data bus. The above state continues to be maintained while the system clock 5CLK is stopped.

The clock loss detection signal is held as a level signal in the register of the clock loss detection section 9, and the level signal held by -degrees is released by inputting a clock loss clear pulse. This happens when controlling with device control card 3.
This is to prevent the card from malfunctioning due to the system clock signal.

〔Example〕

A block diagram of a clock disconnection detection circuit according to an embodiment of the present invention is shown in FIG. In the figure, reference numeral 8 indicates a clock switching section, and reference numeral 9 indicates a clock disconnection detection section.

The clock disconnection detection unit 9 includes flip-flops 11 to 16.1.
8 and a NAND circuit 17, it inputs the system clock 5CIJ and the internal card clock CCLK, and when the system clock is disconnected, sends a clock disconnection detection signal to the bus enable 7, and also controls the clock switching unit 8. Input the card internal clock signal CCLK to the control block 4. Further, a reset signal HR5T is inserted into the flip-flop 12 to release the level signal held in the register as a clock interruption detection signal.

A time chart of the embodiment is shown in FIG. Figures 2 and 3
The operation of the embodiment will be explained with reference to the drawings.

Normally, communication is performed in frame units, so synchronization is achieved using a long-cycle frame pulse FRPA. The output (2) of the flip-flop 12 is a value obtained by dividing the system clock 5CLK by two, and the output (2) of the flip-flop 12 is an inverted signal. Therefore the system clock 5
If CLK stops, flip-flop 11 will inevitably
The output of the flip-flop 12 stops, and the outputs ■ and ■ of the flip-flop 12 also stop. When the output signal stops at “11”, the output signal ■ is always “L” and the flip-flop 1
3 and 14 are activated, and when the frame pulse FRPA falls twice, the output ■ signal of the flip-flop 14 becomes "Signal", and clock interruption detection is performed.Flip-flops 15 and 16 are always cleared and set to "H". Therefore, the clock disconnection detection signal ■ from the NAND circuit 17 is “
If the output of flip-flop 12 stops at <11L11, the output of flip-flop 1
5 and 16 are operating, and flip-flops 13 and 14 are cleared. Therefore, contrary to the above operation, the signal (2) becomes "L" and the signal (2) is in the "H" state, so that the clock interruption detection signal (2) is sent out from the NAND circuit 17 at "H". That is, when the system clock 5CLK is disconnected, the clock disconnection detection signal ■ is always sent out by the output ■ or ■ of the flip-flop 14 or 16, regardless of whether the clock state is H or L. This clock disconnection detection signal controls the switching of the clock switching unit 8 consisting of a 2-1 selector, inserts the card internal clock signal CCLK into the control block 4, and sends a control signal to the switch enable unit 7 to The interface 6 is masked to prevent data from the terminal 2 from being sent out to the terminal 2. Next, when the system clock comes in, a disconnection detection clear pulse is input to the flip-flop 18, thereby canceling the disconnection detection signal. be able to.

The present invention can also be used to test terminal interface cards individually, and by cutting off the system clock and disconnecting from the bus, each card can be tested independently using only the internal clock.

〔Effect of the invention〕

When the system clock is disconnected, the card is automatically electrically disconnected from the system and starts running on its own internal clock. Therefore, it is possible to control the inside of the card at the timing that the card has.

[Brief explanation of the drawing]

FIG. 1 is a diagram of the principle configuration of the present invention, FIG. 2 is a diagram of a clock disconnection detection circuit according to an embodiment of the present invention, FIG. 3 is a time chart of the embodiment, and FIG. 4 is a side view of the system configuration of a communication device. Fifth
The figure shows a circuit configuration diagram of a conventional example. In the figure, 1 is a terminal interface card, 2 is a terminal device, 3 is a device control card, 4 is a control block, 5 is an internal clock, 6 is a bus interface, 7 is a bus enable, 8 is a clock switching unit, and 9 is a clock disconnection unit. Detection part, 1
0 indicates a clock interruption detection circuit, 11 to 16.18 indicate flip-flops, and 17 indicates a NAND circuit.

Claims (1)

[Claims] In a method for dealing with a system clock interruption in a terminal interface, the terminal interface card (1) is a bus interface (6) that relays data between a terminal device and a data bus.
) and a control block (
4) and a clock disconnection detection circuit (10) that monitors disconnection of the system clock from the outside, and the clock disconnection detection circuit (10) is connected to a clock switching section (8).
and a clock disconnection detection section (9), and when the system clock is disconnected from the outside, the clock switching section (8) is controlled by the clock disconnection detection signal from the clock disconnection detection section (9) to switch the system clock. A system clock disconnection system characterized in that the clock disconnection detection signal is switched to an internal clock (5) and supplied to the control block (4), and the clock disconnection detection signal is sent to a bus enable (7) to mask-control the bus interface (6). How to respond.