JPH0241717Y2 - - Google Patents

Description

[Detailed description of the invention] [Industrial application field] This invention determines the authenticity of inserted coins by the interaction between the inserted coins and the electromagnetic field produced by a sorting coil placed close to the coin path. This invention relates to a coin sorting device.

[Conventional technology]

This type of coin sorting device determines the authenticity of the inserted coin by the interaction between the inserted coin and the electromagnetic field generated by the sorting coil.The coin sorting device uses the sorting coil to inspect the coins rolling in the coin passage. The output of this authenticity determination controls a gate provided at the end of the coin passage, and the gate distributes genuine coins to the genuine coin passage and counterfeit coins to the return passage. As such a conventional device, the invention described in Japanese Patent Publication No. 47-30877 is well known.

In the invention described in Japanese Patent Publication No. 47-30877, when an inserted coin is inspected by a sorting coil and determined to be a genuine coin, a flip-flop corresponding to the denomination of the inserted coin is set, and at the same time, another coin is detected. Reset the seed flipflop. The output of the set flip-flop opens the gate and guides the inserted coin into the genuine coin passage.

At this time, there is a coin detector in the genuine coin passage, and the gate is closed by the detection signal of this coin detector, and a coin counting signal is generated by the AND signal with the output of the set flip-flop, and by the detection signal, the gate is closed. This resets the flip-flop. According to this conventional device, when it is detected that a coin has been accepted into the genuine coin passage, the gate is closed and a signal for counting coins is issued, so that it is possible to prevent tampering with coins caught on a line.

[Problem that the invention attempts to solve]

However, in this conventional device, when genuine coins are continuously inserted, the following erroneous counting occurs. That is, for example, when coins of different denominations are successively inserted, the flip-flop corresponding to the denomination of the preceding coin is reset by the authenticity determination signal of the subsequent coin, and the flip-flop corresponding to the denomination of the subsequent coin is set. As a result, when the preceding coin is guided to the genuine coin passage and detected by the coin detector,
The logical product (coin counting signal) of this detection signal is taken by a flip-flop corresponding to the denomination of the subsequent coin. Therefore, the coin counting signal for the preceding coin is not emitted, resulting in erroneous counting in which the counted value of the total amount inserted is different from the actual amount inserted.

In view of the above-mentioned points, the present invention is designed to continuously generate an output within a predetermined period from a comparator circuit that generates an output when detecting that the detection signal of the sorting coil is within a predetermined genuine coin discrimination reference range. An object of the present invention is to provide a coin sorting device that can return the continuously inserted coins when such continuous insertion occurs.

[Means for solving problems]

In order to achieve the above-mentioned objects, the present invention provides a coin passage through which coins inserted from a coin slot roll, a sorting coil that detects the properties of the coins rolled in the coin passage, and a sorting coil. First and second coin detectors are placed in front and behind the coin in the rolling direction of the coin, respectively, and detect that the detection signal of the sorting coil is within a predetermined genuine coin discrimination reference range and output it. a first flip-flop that is set by the output of the first flip-flop; and a first flip-flop that is set by detecting that the output of the first flip-flop is generated when the first flip-flop is set. a second flip-flop;
a third flip-flop that is set by the coin detection signal of the first coin detector, is set by the coin detection signal of the second coin detector, and resets the first and second flip-flops by a reset output; , detecting that the first flip-flop is set and the second flip-flop is reset when a coin detection signal of the second coin detector is generated, and confirming that the coin is a genuine coin. a timer that generates an output for a predetermined period of time based on the generation of the genuine currency signal; the timer is in a first state when the output disappears, and is in a second state when the output is generated; a gate for distributing the inserted coins according to a first state of the gate, a return path to which the inserted coins are guided according to a first state of the gate, and a second gate of the gate.
It is characterized by comprising a genuine coin passageway through which the inserted coin is guided depending on the state.

[Effect]

In the present invention, when the inserted genuine coin passes the position of the sorting coil, an output is generated from the comparator circuit and the first flip-flop is set. If only the first flip-flop is set at the time when the second coin detector detects the coin, a genuine coin signal is generated, the gate is set to the second state by the output of the timer, and the inserted coin is a genuine coin. led to a passage. However, the third flip-flop, which resets the first and second flip-flops by the reset output, is set and reset by the coin detection signals of the first and second coin detectors, respectively.
Since it is reset, the preceding coin is the first coin.
If continuous input occurs in which a succeeding coin causes an output to be generated from the comparator circuit after being detected by one coin detector and before being detected by a second coin detector,
Since the first and second flip-flops are set together, no specie signal is generated and no output is generated from the timer. Therefore, when such continuous input occurs, the gate remains in the first state, and the continuously input coins are guided to the return path and returned.

〔Example〕

Next, one embodiment of the present invention will be described in detail based on the drawings. FIGS. 1 and 2 each show an embodiment of the present invention, with FIG. 1 being a schematic diagram showing the main parts of a coin sorting machine, and FIG. 2 being a circuit diagram.

In FIG. 1, reference numeral 1 denotes a sorting machine body having a coin input port 11 and a protrusion 12 forming a coin passage;
L ₀ is a sorting coil fixedly arranged on the surface facing the coin rolling on the protrusion 12 of the coin passage, SW ₁ , SW ₂
are detectors that sandwich the sorting coil _L0 and are placed in front and behind the coin rolling direction of the sorting coil _L0 ,
Reference numeral 2 denotes a gate which can appear in and out of the coin passage and distributes coins into a genuine coin passage indicated by arrow A or a return passage indicated by arrow B. The detectors SW ₁ and SW ₂ consist of, for example, a light emitting diode and a phototransistor. Coins inserted from the coin input port 11 move along a path shown by a dotted line. That is, the coins inserted from the input port 11 roll on the protrusion 12 of the coin passage and pass through the detector SW ₁ and the sorting coil.
L ₀ and the coin detector SW ₂ position are sequentially passed through to reach the gate 2 position. At this time, if the coin is a genuine coin, the gate 2 exits the coin passage (it is set to the second state) and allows the coin to fall into the genuine coin passage indicated by arrow A without preventing the coin from falling. If the coin is a coin, it protrudes above the coin passage (into the first state) and prevents the coin from falling into the coin passage.
This will lead you to the return passage indicated by .

Figure 2 shows a circuit diagram for sorting coins. In Figure 2, AB is the sorting coil L ₀ and the variable coil
Bridge circuit consisting of L ₁ , variable resistor R ₀ , fixed resistors r ₁ and r ₀ , RS is operational amplifier OP, feedback resistor
R ₁ , diodes D ₁ and D ₂ , and a rectifying and smoothing circuit consisting of a smoothing capacitor C ₁ CP is a comparison circuit consisting of a differential amplifier DA and a feedback resistor R ₂ SW is an R-S flip-flop FF ₃ , a resistor R ₃ , and a capacitor C ₂ , AND circuit
Detection output circuit consisting of _AD1 , OUT is J-K flip-flop _FF1 , R-S flip-flop _FF2 ,
This is an output circuit consisting of AND circuits AD ₂ and AD ₃ and a timer T. In the circuit shown in FIG. 2, the output _V1 of the bridge circuit AB is rectified and smoothed by a rectification and smoothing circuit RS. Next, the DC output of this rectifier smoothing circuit RS
V ₂ is compared with the genuine currency discrimination reference voltage CV by the differential amplifier DA of the comparator circuit CP, and this comparator circuit CP outputs
When V ₂ is lower than the reference voltage CV, that is, when the bridge circuit AB is balanced, a single pulse selection signal is output as the output V ₃ to the first output circuit OUT.
Sends it to the clock pulse input terminal CL of flip-flop _FF1 . On the other hand, the detection output circuit SW is
Detector at the set input of flip-flop FF ₃
When there is no input of the detection signal SW ₁₁ of SW ₁ , the logic signal "1" (hereinafter referred to simply as "1") is output from its Q terminal, so the AND condition of the AND circuit AD ₁ is satisfied. , the first of the output circuit OUT,
"1" is output to the clear input C and reset input R of the second flip-flops FF _{1 and} FF 2 to reset each flip-flop FF ₁ and FF ₂ . When the detection signal SW ₁₁ from the detector SW ₁ is input to the set input of the flip-flop FF ₃ , a logic signal "0" (hereinafter simply referred to as "0") appears at the terminal, so that each flip-flop is connected via the AND circuit AD ₁ .
The reset signal supplied to FF ₁ and FF ₂ is released, and the coin sorting period starts from this time.
The end of this coin sorting period is Flip Flop FF ₃ .
This is done by inputting the detection signal SW ₂₁ from the coin detector SW ₃ to the reset input R of the coin detector SW 3. When flip-flop FF ₃ is reset, a "1" appears on its terminal again, which causes the AND circuit to
A reset signal is applied to the clear input C and reset input R of flip-flops _FF1 and _FF2 via _AD1 . The capacitor _C2 connected to one input terminal of the AND circuit _AD1 does not reset the flip-flops _FF1 and _FF2 at the same time when the Q terminal " ₁ " of the flip-flop FF3 appears.
It delays by a short predetermined time so that the AND condition of AND circuit AD ₁ is satisfied, and just before a coin is detected by coin detector SW ₂ , which determines the coin sorting period, a single pulse is sent from comparator circuit CP for sorting. Signal V ₃
When the output is output, the flip-flop
This is to ensure that it is stored in FF ₁ or FF ₂ . The output circuit OUT outputs the flip-flop FF when the selection signal _V3 representing the equilibrium state of the bridge circuit appears from the comparator circuit CP only once during the coin selection period determined by the detection output circuit SW, that is, when there is no continuous input. When ₁ is set and a detection signal is given from coin detector SW ₂ , input ``1'' to timer T via AND circuit AD ₃ .
is given. At this time, a genuine coin signal M for coin counting is sent via an AND circuit _AD3 as a genuine coin signal generating means.
is sent. Furthermore, if the sorting signal V ₃ representing the balanced state of the bridge circuit appears twice or more during the coin sorting period, that is, if genuine coins are continuously inserted, flip-flops FF ₁ and FF ₂ are both set, so the AND The AND condition of AD ₃ is not satisfied, and in this case, input "1" is not given to timer T and timer T does not operate. Timer T is and
When an input "1" is received via AD ₃ , a time-limited operation is started and an output "1" of a predetermined time width is sent out, and this output "1" is used as a gate control signal G.

Next, the coin sorting operation of the present invention will be explained.
Before a coin is inserted from the coin input port 11 shown in Fig. 1, when there is no change in the impedance of the sorting coil _L0 , the bridge circuit AB is in an unbalanced state, and the output _V1 of the bridge circuit AB is a large unbalanced voltage. The waveform of this unbalanced voltage is shown in Figure 3, _V1 . FIG. 3 shows waveform diagrams when only one genuine coin is inserted, and when two genuine coins are consecutively inserted. Before a coin is inserted, flip-flop _FF3 is in a reset state, as will become clear later, and thereby flip-flops _FF1 and _FF2 are also in a reset state via AND circuit _AD1 .
When flip-flops FF ₁ to _{FF 3} are in such a state, if a genuine coin is inserted from the coin slot 11, the coin is first detected by the detector SW ₁ , and then transferred from the detector SW 1 to the third detector SW ₁ . A detection signal as shown by SW ₁₁ in the figure is transmitted. This detection signal
Flip-flop FF ₃ with SW ₁₁ as set input
is given the detection signal and at the same time as shown in Fig. 3.
Set as shown in FF ₃ . As a result, the terminal "0" of the flip-flop _FF3 appears, and since the AND condition of the AND circuit _AD1 no longer holds true, the output of the AND circuit _AD1 becomes "0". When the output of the AND circuit AD ₁ becomes "0", the reset input of each flip-flop FF ₁ and FF ₂ is canceled and the coin sorting period starts. flip flop
"1" is applied from the terminal of FF ₂ to one input terminal of AND circuit AD ₃ .

The coin detected by the detector SW ₁ then passes through the position of the sorting coil L ₀ . At this time, the bridge circuit AB becomes balanced due to the change in impedance of the selection coil _L0 . Output of bridge circuit AB
As mentioned above, V ₁ is rectified and further smoothed by the rectifying and smoothing circuit RS, and becomes "positive" as shown by V ₂ in Figure 3.
The DC output will be V ₂ . This output V ₂ is the comparator circuit CP
It is compared with the genuine currency discrimination reference voltage CV. This reference voltage CV is shown at _V2 in FIG. The magnitude of the output V ₁ of the bridge circuit AB approaches zero as the bridge changes from an unbalanced state to an balanced state, so when the bridge circuit AB is balanced, the rectifying and smoothing circuit
The output V ₂ of RS is lower than the reference voltage CV. The comparator circuit CP emits a signal when the output V ₂ is lower than the reference voltage CV, and while the output V ₂ is lower than the reference voltage CV, it outputs a single-pulse selection signal V ₃ as shown by V 3 in Figure ₃ . Output. Comparison circuit CP selection signal
_V3 is applied to the clock pulse input terminal CL of flip-flop _FF1 of the output circuit OUT. At this time, since the reset input of flip-flop _FF1 has been released, it is set by inputting selection signal _V3 , and this state is shown by _FF1 in FIG. When flip-flop _FF1 is set, "1" is applied to one input terminal of AND circuit _AD3 connected to its Q terminal.

The coins that have passed through the position of the sorting coil _L0 then reach the position of the coin detector _SW2 . The detection signal SW ₂₁ of the coin detector SW ₂ is shown as SW ₂₁ in FIG. 3, and this detection signal resets the flip-flop FF ₃ and satisfies the AND condition of the AND circuit AD ₃ . When the AND condition of the AND circuit AD ₃ is satisfied, the coin counting genuine coin signal M is transmitted, and the timer T starts operating and transmits the gate signal G for a predetermined time limit. In response to the gate signal G, the gate member 2 shown in FIG. The detection signal
When flip-flop FF ₃ is reset by SW ₂₁ , "1" appears at its terminal. As a result, the AND circuit _AD1 satisfies the AND condition after a short delay time has elapsed due to the capacitor _C2 , and sends out "1" from its output terminal, resetting the flip-flops _FF1 and _FF2 . By placing the flip-flops FF ₁ and FF ₂ in the reset state, the coin sorting period ends and the coins are placed in a standby state in preparation for the next input coin.

Next, a case where two genuine coins are inserted consecutively will be explained. The waveform diagram of the circuit is shown in FIG. When coins are successively thrown in from the slot 11 shown in FIG. 1, the preceding coin is first detected by the detector _SW1 . Detection signal of this detector SW ₁
Flip-flop FF ₃ is set by SW ₁₁ ,
At this time, since "0" appears at the terminal, the flip-flops FF ₁ and FF ₂ are reset via the AND circuit AD ₁ . A subsequent coin is detected by the detector SW ₁ following the preceding coin, but since flip-flop FF ₃ has already been set, the set state of flip-flop FF ₃ does not change. detector
The coin that has passed SW ₁ then reaches the position of the sorting coil L ₀ , and when the preceding coin and the following coin pass the position of the sorting coil L ₀ , the bridge circuit AB has a signal as shown in V ₁ in Figure 3. The equilibrium state of the bridge appears. The output _V1 of the bridge circuit AB is converted into a single-pulse selection signal _V3 representing the balanced state of the bridge via a rectifying and smoothing circuit RS and a comparator circuit CP. The single pulse caused by the preceding coin as the selection signal _V3 of the comparator circuit CP is a flip-flop.
When applied to FF ₁ , "1" appears at its Q terminal and "1" is given to one input of AND circuits AD ₂ and AD ₃ . After the flip-flop FF ₁ is set by a single pulse from the preceding coin, when a single pulse from the subsequent coin is output from the comparator circuit CP, "1" is given to the other input of the AND circuit AD ₂ , so the AND circuit AD The AND condition of ₂ is satisfied and a set input "1" is given to flip-flop _FF2 .
As a result, "0" appears at the terminal of flip-flop _FF2 , and therefore "0" is given to one input of AND circuit _AD3 .

When the preceding coin that has passed the position of the sorting coil _L0 next rolls to the position of the coin detector _SW2 , a detection signal _SW21 is transmitted from the coin detector _SW2 .
The flip-flop _FF3 is reset by the detection signal _SW21 of the coin detector _SW2 . At this time, the detection signal _SW21 is applied to the AND circuit _AD3 , but since one input of the AND circuit _AD3 is connected to the terminal of the flip-flop _FF2 which is in the set state, the AND condition does not hold. Therefore, the coin counting specie signal M and the gate signal G are not transmitted, and the gate member 2 shown in FIG. It is blocked and distributed to the return route indicated by arrow B. When the flip-flop _FF3 is reset by the detection signal _SW21 , "1" appears at its terminal, so a reset signal is applied to the flip-flops _FF1 and _FF2 via the AND circuit _AD1 . When flip-flops FF ₁ and FF ₂ enter the reset state, the coin sorting period ends and they enter a standby state for the next input coin.

Although the case where genuine coins are continuously inserted has been explained above, since the sorting signal _V3 is not generated when counterfeit coins are continuously inserted, the flip-flop _FF1
is never set and therefore the gate signal G
is not issued and the gate 2 is maintained in a state protruding into the coin path, and the continuously inserted counterfeit coins are returned.
If genuine coins and counterfeit coins are continuously inserted, the counterfeit coins will be accepted into the genuine coin passage along with the genuine coins, but since the genuine coin signal for coin counting is transmitted in correspondence with the genuine coins, an erroneous count will occur. This is not the case, and if it is inconvenient to accept such counterfeit currency, separate measures should be taken.

In the above embodiments, a sorting device using a bridge circuit with a sorting coil on one side was described, but a sorting device that configures an oscillator using a sorting coil and detects a change in oscillation frequency when coins pass, or a sorting device The present invention can also be used in a sorting device that includes an oscillating coil and a receiving coil as coils and detects a change in voltage induced in the receiving coil when a coin passes.

[Effect of idea]

According to the present invention as described above, an output is continuously generated within a predetermined period from a comparison circuit that generates an output when detecting that the detection signal of the sorting coil is within a predetermined genuine currency determination reference range. When continuous insertion of coins like this occurs, the gate remains in the first state and the continuously input coins are returned without generating a specie signal, thereby preventing errors when specie coins are continuously input. Counting can be prevented and sorting accuracy can be improved.

[Brief explanation of drawings]

1 and 2 are schematic and circuit diagrams showing one embodiment of the present invention, and FIG. 3 is a waveform diagram showing its operation. 2...Gate, 11...Coin slot, 12...
Coin passage, A...Specie coin passage, B...Return passage,
L ₀ ... Sorting coil, SW ₁ ... First coin detector,
SW ₂ ...Second coin detector, CP...Comparison circuit,
FF ₁ ...first flip-flop, FF ₂ ...second flip-flop
flip-flop, _FF3 ...third flip-flop, _AD3 ...AND circuit as means for generating a genuine signal, T...timer.

Claims (1)

[Scope of utility model registration request] A coin passageway through which coins inserted from the coin slot roll, a sorting coil that detects the properties of the coins rolling in the coin passageway, and a sorting coil that sandwiches the sorting coil and moves back and forth with respect to the rolling direction of the coins. a comparison circuit that detects that the detection signal of the sorting coil is within a predetermined genuine coin determination reference range and generates an output; a first flip-flop that is set when the first flip-flop is set, and a second flip-flop that is set by detecting that the output of the comparator circuit is generated;
a third flip-flop that is set by the coin detection signal of the first coin detector, is set by the coin detection signal of the second coin detector, and resets the first and second flip-flops by a reset output; , detecting that the first flip-flop is set and the second flip-flop is reset when a coin detection signal of the second coin detector is generated, and confirming that the coin is a genuine coin. a timer that generates an output for a predetermined period of time based on the generation of the genuine currency signal; the timer is in a first state when the output disappears, and is in a second state when the output is generated; a gate for distributing the inserted coins according to a first state of the gate, a return path to which the inserted coins are guided according to a first state of the gate, and a second gate of the gate.
A coin sorting device comprising: a genuine coin passage through which the inserted coin is guided depending on the state.