JPH0156435B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a coin sorting device in which a plurality of coin detectors are provided in a coin passage to determine the authenticity of inserted coins and whether the coins are continuously inserted. It is suitable for use in vending machines, etc.

[Conventional technology]

In conventional coin sorting devices, for example, as in the device described in Japanese Patent Application Laid-open No. 123298/1983, in order to accurately determine the authenticity of the inserted coins or sort them by denomination, it is necessary to determine whether the inserted coins are continuously inserted. There is something that does this.

This is because, before the first coin that has been inserted has passed through the last stage of coin detectors among the multiple coin detectors arranged along the coin path, the subsequent coins are detected by the first stage coin detector. If continuous coin insertion occurs that can be detected by the coin detector, the operation for determining authenticity is prohibited and the input coins are rejected, and the first stage coin detector This is performed by a timer that starts operating when a coin passes and has an operating time until at least the coin passes through the final stage coin detector.

[Problem that the invention seeks to solve]

However, since the rolling speed of the coin is not necessarily constant, if the timer is used to release the rejection as described above, the rolling speed of the coin is It is necessary to set the timer operation time with enough time.

For this reason, after a coin is rejected due to continuous insertion, it takes a long time until the next coin is allowed to be accepted. Even if you try to put it in again, it will be returned again, which is an inconvenience.

In view of the above-mentioned points, the present invention makes it possible to detect when an inserted coin has passed through the final stage coin detector, so that even if continuous insertion occurs, the next inserted coin can be promptly accepted. The purpose is to provide a coin sorting device.

[Means for solving problems]

In order to achieve the above-mentioned object, the present invention includes a rolling path on which a coin inserted from a coin input slot rolls, and a system that is sequentially provided along the rolling path to detect the properties or passage of the inserted coin. multiple coin detectors,
an acceptability determining circuit that integrates the outputs of the plurality of coin detectors and determines acceptability based on the successive inputs of the input coins and authenticity; a flip-flop that is set based on the acceptability determination output of the circuit; a timer for resetting the flip-flop a predetermined time after the flip-flop is set;
The reset output of the flip-flop causes the first
a sorting member for distributing the inserted coins that have passed through the plurality of coin detectors and have been set to a second state by a set output, and a return path through which the inserted coins are guided according to the first state of the sorting member;
In the coin sorting device, the coin sorting device includes a receiving path through which the inserted coins are guided according to the second state of the sorting member. a counting means for subtracting and counting the passage detection signal from that of the stage; a count content detecting means for detecting and outputting the count content of the counting means as a predetermined value; The present invention is characterized in that the acceptability determination circuit includes a gate circuit that sends out an acceptability determination output.

[Effect]

According to the present invention, the counting means counts the number of coins between the first stage coin detector and the last stage coin detector, and the count value of the counting means becomes 1. If it becomes 0, then continuous injection did not occur, and if it becomes 2 or more, continuous injection occurred, and,
When the continuously input coins finish passing through the final stage coin detector, the value becomes 0 again. In the present invention, the acceptability judgment output is sent out on the condition that the count content of the counting means that changes in this way is a predetermined value, so that it is possible to detect whether continuous coins are being inserted and whether continuous coins are being inserted. When all the coins have passed through the final stage coin detector, it is possible to detect that the continuous insertion is resolved, and as soon as the continuous insertion is resolved, it becomes possible to immediately send out an output for determining whether the next inserted coin can be accepted.

〔Example〕

Next, one embodiment of the present invention will be described in detail based on the drawings.

Figure 1 is a schematic configuration diagram of a coin sorter, Figure 2 is a circuit diagram showing a bridge type sorting circuit using a sorting coil, and Figure 3 is a circuit diagram showing a coin detection unit that specifically detects specific coins with different diameters. Figure 4 is a circuit diagram for determining the authenticity of coins using the bridge method, Figure 5 is a circuit diagram for determining specific coins and continuous insertion, and Figure 6 is a circuit diagram for determining whether coins are genuine or counterfeit. 7 and 8 each show a waveform diagram of a specific circuit voltage.

In FIG. 1, 1 is a coin sorting machine main body, 11 is a coin input port, 12 is a rolling path that protrudes from the coin sorting machine main body 1 and forms a coin passage in which the inserted coins roll;
2 is connected to the iron core of an electromagnetic device (not shown) so as to be able to appear and retract from the main body 1 of the coin sorting machine.
3 is a sorting coil disposed along the rolling path 12 for input coins; SW 1 is a sorting member disposed in a manner that it can freely appear and retract from above, and distributes the input coins into a storage direction (acceptance path) A or a return direction (return path) _B ; indicates a coin detector having a receiving coil, and SW ₂ and SW ₃ indicate coin detectors composed of a light emitting diode and a phototransistor. Then, the selection coil 3 is connected to the impedance of one side of the bridge circuit as shown in Fig. 2.
It is configured as L ₀ . Also, coin detector
As shown in FIG. 3, SW ₁ consists of a transmitting coil 42 connected to an oscillating circuit 41 and a receiving coil (hereinafter simply referred to as receiving coil SW ₁ ) facing the transmitting coil 42. When there is no coin between the transmitting coil 42 and A predetermined induced voltage is generated in the receiving coil _SW1 , and when a coin is present between the receiving coil SW1 and the transmitting coil 42, the induced voltage is configured to change depending on the properties, diameter, and shape of the coin. A coin inserted from the coin input slot 11 shown in FIG. 1 passes through the receiving coil SW ₁ , the sorting coil 3 , and the coin detector SW 2 in order along the path shown by the dotted line on the rolling path 12 until it reaches the coin detector SW ₂ . After it is determined whether the coins are fake or continuous, if the input coins are genuine coins and are not inserted continuously, the sorting member 2 collapses from above the main body 1, and the coins are guided in the storing direction of arrow A and sent to the coin detector. The coins fall through the SW ₃ position, and if the input coins are counterfeit coins or continuous coins, the sorting member 2 protrudes above the main body 1 and is guided in the return direction of arrow B.

The bridge circuit with the selection coil 3 as one side is the second
It is configured as shown in the figure. In Fig. 2, L ₀ is the impedance of the sorting coil 3, L ₁ ,
R ₁ is a standard inductance and a standard resistance determined according to the properties of the coins to be sorted, and these are used as standard impedance. Connection point of resistors r ₁ and r ₀ and impedance L ₀ and impedance L ₁
An oscillator ω ₀ is connected to the connection point of . The output end of the bridge circuit is connected to the operational amplifier through the resistor _R3 .
It is connected to one input of OP ₁ , and the other input of this operational amplifier is grounded. Operational amplifier OP ₁
A diode D ₂ is connected between the output of the operational amplifier OP ₁ and one input of its amplifier OP 1, and the cathode of the diode D ₁ connected to the output of the operational amplifier OP ₁ and one input of its amplifier OP ₁ . A resistor _r4 is connected between them, and a smoothing capacitor _C1 whose one end is grounded is connected. This operational amplifier OP ₁ ,
A rectifying and smoothing circuit 31 is constituted by resistors r ₃ and r ₄ , diodes D ₁ and D ₂ , and smoothing capacitor C ₁ . The output of the rectifying and smoothing circuit 31 is connected via a resistor _r5 to one input terminal of an operational amplifier _OP2 , and the other input terminal of this operational amplifier _OP2 is connected to a predetermined reference voltage via a resistor _r6 . COM is given and
It is connected with its output end via resistor _r7 . A comparator circuit 32 is constituted by the operational amplifier _OP2 . In the circuit shown in Figure 2, the bridge circuit outputs a large unbalanced voltage when there is no coin at the position of the sorting coil 3, and when a genuine coin passes the position of the sorting coil 3, the impedance of the sorting coil L ₀ changes and balances, and the output of the bridge circuit becomes zero. The output of the bridge circuit is a rectifier and smoothing circuit 31
The voltage is rectified and smoothed by the comparator circuit 32, and compared with a predetermined reference voltage COM close to zero potential.
When the output of the bridge circuit approaches zero potential and becomes lower than a predetermined reference voltage COM, the comparison circuit 32 outputs a selection signal S.

FIG. 3 shows a circuit diagram of a coin detector equipped with the receiving coil SW ₁ shown in FIG. 1. In FIG. 3, the receiving coil SW ₁ is arranged opposite to the oscillating coil 42 connected to the oscillator 41, and the inserted coin CN can pass between the receiving coil SW ₁ and the transmitting coil 42. One end of the receiving coil SW ₁ is grounded, and the other end includes an operational amplifier OP ₆ , resistors r ₁₁ , r ₁₂ , and a diode.
A rectifying and smoothing circuit 13 consisting of D ₃ , D ₄ and a smoothing capacitor C ₃ is connected, and the induced voltage generated in the receiving coil SW ₁ is rectified and smoothed. Rectifier smoothing circuit 43
The output of is connected to a window comparator 44 and a comparison circuit 45. The window comparator 44 receives the output of the rectifying and smoothing circuit as one input, and receives a predetermined first reference voltage COM ₁ and a second reference voltage as the other input, respectively.
Two operational amplifiers OP ₃ , OP ₄ given COM ₂
The output ends of the amplifiers OP ₃ and OP ₄ are connected to the connection point between the resistor R and the capacitor C ₂ connected in series between the positive power supply +V and the negative power supply -V. This window comparator 44 is a rectifier smoothing circuit 43
The output voltage of amplifier OP ₃ is the first reference voltage COM ₁
and the second reference voltage COM ₂ of the amplifier OP ₄ , and if this state lasts for a time determined by the time constants of the resistor R ₂ and the capacitor C ₂ , it will issue an output. Furthermore, the output of the rectifying and smoothing circuit 43 is used as one input, and the other input is provided with a predetermined third reference voltage COM ₃ , which is an operational amplifier OP ₅ and a resistor.
A comparator circuit 45 consisting of r ₈ , r ₉ , and r ₁₀ outputs an output when the output voltage of the rectifying and smoothing circuit 43 falls below the third reference voltage COM ₃ . The output of this comparison circuit 45 is connected to one input terminal of a NOR circuit NOR ₁ via an inverting circuit NOT ₁ , and the output terminal of the window comparator 44 is connected to the other input terminal of this NOR circuit NOR ₁ . connected via. The output SP ₁ of this NOR circuit NOR ₁ is used as an input coin detection signal and a specific coin selection signal.

Next, the operation of the circuit shown in FIG. 3 will be explained with reference to the waveform diagram shown in FIG. 7a shows the output V ₁ of the rectifying and smoothing circuit 43, FIG. 7b shows the output V ₂ of the window comparator 44, FIG. 7c shows the output V ₄ of the Schmitt trigger circuit 46, and FIG. 7d shows the comparison circuit 45.
The output V ₃ and Figure 7 e are the outputs of the NOR circuit NOR ₁ .
Showing SP ₁ . In Figure 7a, the horizontal axis is time t,
The vertical axis indicates the output voltage, and V _C indicates the standby voltage induced in the receiving coil SW 1 in the standby state when there is no inserted coin between the transmitting coil 42 and _{the receiving coil SW 1 .} V _COM3 is a voltage slightly lower than the standby voltage V _C and represents the third reference voltage COM ₃ of the comparator circuit 45. V _COM1 and V _COM2 are window comparators 44
represents the first and second reference voltages COM ₁ and COM _{2 of COM 1 and COM 2} .

Transmitting coil 42 and receiving coil SW ₁ shown in Fig. 3
When there is no inserted coin between the receiving coil SW 1 and the receiving coil SW 1 , a standby voltage V _C is induced in the receiving coil SW ₁ by the magnetic field formed by the transmitting coil 42 . When a specific coin enters the magnetic field formed by the transmitting coil 42, the voltage induced in the receiving coil _SW1 by the specific coin gradually attenuates. At this time, the output V ₁ obtained by rectifying and smoothing the voltage induced in the receiving coil SW ₁ by a specific coin is shown by a solid line in Figure 7a, and the voltage induced in the receiving coil SW ₁ by a coin with a small diameter unlike the specific coin is shown by a solid line. The output V ₁ obtained by rectifying and smoothing the voltage is shown by a dashed line, and the output V ₁ obtained by rectifying and smoothing the voltage induced in the receiving coil SW ₁ by a large-diameter coin is similarly shown by a dotted line. The voltage induced in the receiving coil SW ₁ due to the entry of a specific coin is attenuated, and the output V ₁ becomes the third reference voltage of the comparator circuit 45.
When the voltage falls below COM ₃ , the comparator circuit 45 generates an output V ₃ as shown in FIG. 7d. Next, the specific coin passes between the transmitting coil 42 and the receiving coil SW ₁ , the voltage induced in the receiving coil SW ₁ is attenuated, and the output is
A state in which V ₁ is lower than the second reference voltage COM ₂ of the window comparator 44 and does not fall below the first reference voltage COM ₁ , that is, the output V ₁ is at the first reference voltage.
If the condition existing between COM ₁ and the second reference voltage COM ₂ continues for a predetermined time determined by the time constants of resistor R ₂ and capacitor C ₂ , the window comparator 44 outputs a signal as shown in FIG. 7b. Output V ₂ is emitted. Output of window comparator 44
_V1 is waveform-shaped into a rectangular wave by the Schmitt trigger circuit 46, and an output _V4 as shown in FIG. 7c is guided from the Schmitt trigger circuit 46 to one input terminal of the NOR circuit _NOR1 . Since the signal obtained by inverting the output V ₃ of the comparator circuit 45 by the inverting circuit NOT ₁ is led to the other input terminal of the NOR circuit NOR ₁ , the NOR circuit
The output SP ₁ of NOR ₁ becomes two pulse signals as shown in FIG. 7e. The output of this NOR circuit NOR ₁
SP ₁ is used as a detection signal to detect the passage of a coin, and when two pulse signals appear as this detection signal, it is determined as a specific coin. An example will be explained. In the case of a coin other than a specific coin, for example, if the output V _{1 of} the waveform shaping circuit 43 changes as shown by the dashed line in _FIG . A single pulse with a width equal to the falling period is transmitted as the detection signal SP ₁ via the NOR circuit NOR ₁ . Furthermore, if _the output V ₁ changes as shown by the dotted line in FIG.
The pulse detection signal is transmitted as a pulse detection signal having a width corresponding to the period during which the voltage is below the third reference voltage _COM3 . At this time, the output V ₁ shown by the dotted line is the first reference voltage COM ₁ and the second reference voltage of the window comparator 44.
COM ₂ , but since this period is shorter than the predetermined time determined by the time constant of the resistor R and the capacitor C, the output V ₂ is not generated or is small. Therefore, since the output V ₂ does not reach the trigger level of the Schmitt trigger circuit 46, the output V ₄ of the Schmitt trigger circuit 46 is not generated. Such a coin detection unit detects an inserted coin and sends out a detection signal, sending out two pulses when a specific coin is inserted, and sending out one single pulse when other coins are inserted. .

Next, the determination of the authenticity (authenticity) of a coin will be explained. First, a case will be described in which authenticity is determined by detecting the passing position of an inserted coin and determining a sorting period. FIG. 4 shows an authenticity determination circuit, and the terminal IN is connected to the output terminal of the comparison circuit 32 shown in FIG. Terminals SW ₁₁ and SW ₂₁ each indicate an input terminal for inputting a coin detection signal, and terminal SW ₁₁ is connected to the output terminal of the NOR circuit NOR ₁ in FIG.
SW ₂₁ is connected to coin detector SW ₂ . The terminal IN is a J-K flip-flop FF ₁ (hereinafter referred to as FF ₁
The JK terminal of FF ₁ is connected to the positive power supply +V and the negative power supply -V, respectively. The Q terminal of FF ₁ is connected to one input terminal of the AND circuit AD ₁ , and the signal input to the clock pulse input terminal CL of FF ₁ is guided to the other input terminal of the AND circuit AD ₁ . There is. The output terminal of AND circuit _AD1 is R-
It is connected to the S terminal of an S flip-flop FF ₂ (hereinafter referred to as FF ₂ ), and the terminal of this FF ₂ is connected to the other input terminal of an AND circuit AD ₂ which has one input as the output from the Q terminal of FF ₁ . ing. Coin detection signal SP ₁
The input terminal SW ₁₁ is connected to the S terminal of FF ₃ ,
The Q terminal of this _FF3 is connected to the input terminal of the timer _TM1 . On the other hand, the terminal SW ₂₁ is connected to the other input terminal of an OR circuit OR ₁ which has the output of the timer TM ₁ as one input, and the output terminal of this OR circuit OR ₁ is connected to the R terminal of FF ₃ and also serves as an inverting circuit. Connected to one input end of AND circuit AD ₃ via NOT ₂ .
The output of the terminal of FF ₃ is led to the other input terminal of this AND circuit AD ₃ , and the output terminal of the AND circuit AD ₃ is
Connected to the R terminals of FF ₁ and FF ₂ .

To explain the operation of this circuit, in the standby state, the output of the OR circuit OR ₁ is in the logic signal "0" state (hereinafter simply referred to as "0"), and FF ₁ is in the reset state, so the AND circuit The AND condition of AD ₃ is satisfied. As a result, R of FF ₁ and FF ₂
Logic signal “1” on the terminal (hereinafter simply referred to as “1”)
is given, FF ₁ and FF ₂ are in the reset state. When a coin is inserted into the coin slot ₁₁ shown in FIG.
Since it passes through the position of , the NOR circuit shown in Figure 3
A detection signal SP ₁ as shown in section (1) of FIG. 8a is led from NOR ₁ to terminal SW ₁₁ . FF ₃ is set by the detection signal SP ₁ . As a result, the timer TM ₁ starts a time-limited operation, and since "0" appears at the terminal of FF ₃ , the reset input given to FF ₁ and FF ₂ from the AND circuit AD ₃ is canceled (the reset signal RES disappears). do). After the reset inputs of FF ₁ and FF ₂ are released, the selection period begins as shown in FIG. 8d. The input coin passes through the receiving coil SW ₁ and then reaches the sorting coil 3, so the balanced state of the bridge circuit is detected by the circuit shown in FIG. e
A selection signal S as shown in FIG. terminal IN
When the selection signal S is led to the clock pulse input terminal CL of FF ₁ via the FF 1, FF ₁ is set and sends "1" to one input terminal of each of the AND circuits AD ₁ and AD ₂ . Since the AND condition is satisfied on the condition that FF ₂ is not set, the AND circuit AD ₂ outputs a determination signal SJ as shown in FIG. 8f. At this time, when FF ₂ is inserted with a coin that is made of the same material as the genuine coin and has a diameter larger than that of the genuine coin, the bridge circuit is balanced twice and two pulses are sent to the terminal IN as the sorting signal S. Since it is input, it is set at the second pulse. That is,
FF ₁ is set when the selection signal S appears only once, and FF ₂ is set when the selection signal S appears twice or more. Therefore, if the selection signal S appears twice or more, _FF2 is set, so the AND circuit is
The judgment signal SJ is no longer sent from AD ₂ . FF ₁
is set, a judgment signal SJ is sent from the AND circuit _AD2 , but this judgment signal SJ
is processed by, for example, taking an AND with the coin detector SW ₂ .

When the inserted coin that has passed the position of the sorting coil 3 reaches the position of the coin detector SW ₂ , the coin detector
A detection signal SP ₂ is applied from SW ₂ to a terminal SW ₂₁ .
This detection signal SP ₂ is guided to the R terminal of FF ₃ via an OR circuit OR ₁ , and is also guided to one input terminal of an AND circuit AD ₃ via an inverting circuit NOT ₂ . _FF3
At the same time as is reset, "1" is applied from that terminal to the other input terminal of the AND circuit AD ₃ , but since the AND circuit AD ₃ is provided with the inverted signal of the detection signal SP ₂ , the AND circuit In AD ₃ , the AND condition is not satisfied until the detection signal SP ₂ disappears. After the detection signal SP ₂ disappears, the AND condition of the AND circuit AD ₃ is satisfied, and as a result, the reset signal RES is sent to FF ₁ and FF ₂ . When FF ₁ and FF ₂ are reset, the selection period ends as shown in section (1) of FIG. 8d. In this way, only FF ₁ is set during the selection period from when the detection signal SP ₁ is generated and FF ₁ and FF ₂ are reset to when FF ₁ and FF ₂ are reset by the detection signal SP ₂ . or
Authenticity is determined depending on whether both FF ₁ and FF ₂ are set. Note that the time limit of the timer TM ₁ is set longer than the sorting period, and this is because when the inserted coin does not reach the position of the coin detector SW ₂ , for example, the coin gets stuck in the aisle, or the user inserts the coin. When the return lever, which is operated when you wish to return a coin, is operated, the inserted coin will be detected by a coin detector.
Since it is returned without reaching the SW ₂ position,
In such a case, timer TM ₁ operates and outputs
Transmit TIM and turn up/down counter in Figure 5
At the same time as resetting UD, FF ₃ is reset via OR circuit OR ₁ to return to the standby state.

Next, the determination of a specific coin and the determination of continuous insertion based on the detection signal from the coin detector shown in FIG. 3 will be described below. FIG. 5 shows such a determination circuit, in which SW ₁₁ and SW ₂₁ again represent the input terminals of the detection signal SP ₁ and the detection signal SP ₂ ,
TIM represents the output signal of timer _TM1 shown in FIG. Terminal SW ₁₁ is connected to the other input terminal of OR circuit OR ₂ , which takes the output of AND circuit AD ₄ as one input, and the output of OR circuit OR ₂ is connected to clock pulse input terminal CL of up-down counter UD. There is. Output Q ₁ of up-down counter UD,
The Q ₂ and Q ₃ terminals are connected to the inputs of the NOR circuit NOR, and the output of this NOR circuit is the judgment signal.
The inversion circuit is simultaneously transmitted as CNT NOT ₄
The judgment signal CNT is applied to one input terminal of the AND circuit _AD4 via the AND circuit AD4. The other input terminal of the AND circuit _AD4 is connected to a terminal _SW21 , and its output terminal is connected to an addition/subtraction command terminal U/D of an up-down counter UD via an inverting circuit _NOT3 . The reset terminal R of the up-down counter UD has a fourth
The output TIM of timer _TM1 shown in the figure is derived.

When no coins are inserted from the coin slot 11 shown in Fig. 1, the up-down counter UD is
Since "0" appears at the Q ₁ , Q ₂ , and Q ₃ terminals, the output of the NOR circuit NOR ₂ is "1", and this output is sent to one input of the AND circuit AD ₄ via the inverting circuit NOT ₄ . is given "0". Since the detection signal SP ₂ is not input via the terminal SW ₂₁ , the output of the AND circuit AD ₄ is "0", and therefore the up-down counter is input via the inverting circuit NOT ₃ .
"1" is given to the addition and subtraction command terminal U/D of UD. Here is the updown counter UD
When "1" is input to addition/subtraction command terminal U/D, addition operation is performed, when "0" is input, subtraction operation is performed, and in the above state, addition operation is performed. . Coin slot 1 shown in Figure 1
If only one specie coin is inserted from 1 to 1 and this coin reaches the position of the receiving coil SW ₁ , then from the coin detection section having the receiving coil SW ₁ to the section 1 of Fig. 8a.
The detection signal SP ₁ as described in 1 is sent to the up-down counter via the terminal SW ₁₁ and the OR circuit OR ₂ .
The up-down counter is given to the UD terminal CL.
UD adds this. As a result, "1" appears at the Q terminal of the up-down counter UD, so the output of the NOR circuit NOR ₂ becomes "0" and becomes an inverting circuit.
“1” is applied to one terminal of the AND circuit AD ₄ via NOT ₄ . Next, the inserted coin is detected by the coin detector.
When the position SW ₂ is reached, the detection signal SP ₁ as shown in section 1 of FIG. 8b is applied to the AND circuit AD ₄ , so that the AND condition of the AND circuit AD ₄ is satisfied.
When the AND condition of the AND circuit _AD4 is established, "0" is input to the addition/subtraction command terminal U/D of the up-down counter UD via the inverting circuit NOT ₃ , and the up-down counter UD enters the subtraction mode. on the other hand,
The output of the AND circuit _AD4 is applied to the terminal CL via the OR circuit _OR2 , causing the up-down counter UD to be subtracted. This causes the up-down counter UD
``0'' appears at the Q <sub>1</sub> terminal of , and the output of the NOR circuit NOR <sub>2</sub> becomes ``1''. Detection signal SP ₂ disappears or
Alternatively, at the same time as the output of the NOR circuit NOR becomes "1", the AND condition of the AND circuit _AD4 no longer holds, so its output becomes "0", and "1" is sent to the addition/subtraction command terminal U/D of the up-down counter UD. gives it, puts it in addition mode, and returns to standby state.

Next, when a specific coin is inserted from the coin slot 11 shown in FIG.
When the position of SW ₁ is reached _, two pulse detection signals SP ₁ as _shown in the section in _FIG . It is led to the clock pulse input terminal CL of UD. As a result, the up-down counter UD adds up the detection signal _SP1 and sends "1" from its _Q2 terminal, so the output of the NOR circuit _NOR2 becomes "0". receiving coil
When the coin that has passed through the position SW ₁ reaches the position of the coin detector SW ₂ , a single pulse detection signal SP ₂ as shown in the section of FIG. 8b is input to the terminal SW ₂₁ .
As a result, the AND circuit _AD4 satisfies the AND condition, so it applies "0" to the addition/subtraction command terminal U/D of the up-down counter UD via the inverting circuit NOT ₃ , thereby placing the up-down counter UD in a subtraction mode. On the other hand, the output "1" of the AND circuit _AD4 is guided to the up-down counter UD via the OR circuit _OR2 , so it is guided to the up-down counter UD, so the up-down counter UD subtracts the detection signal _SP2 , but the up-down counter The count content of the counter UD does not become zero and "1" is sent to the _Q1 terminal.
As a result, the output of the NOR circuit NOR ₂ remains at "0". Therefore, by ANDing the output of this NOR circuit NOR ₂ and the detection signal SP ₂ , it can be determined that the detection signal SP ₁ has occurred twice or more. In the above, we have explained the operation when a specific coin is inserted, but before the detection signal SP ₂ is generated from the coin detector SW ₂ , the detection signal from the receiving coil SW ₁ is generated.
The same applies when coins are continuously inserted at intervals such that two pulses are transmitted as SP ₁ .

As described above, the authenticity of the inserted coins, the specific counterfeit coins, and the continuous insertion are determined, and based on the determination results, the sorting member 2 shown in FIG. 1 is controlled to direct the inserted coins in the storage direction A or the return direction. Assign to B. Next, control of the distribution member 2 will be explained using the circuit diagram shown in FIG. FIG. 6 shows the distribution control circuit of the distribution member 2, and in the figure, SW ₂₁ and SW ₃₁ are coin detectors SW _{2 and} SW 31, respectively.
The input terminals of the detection signals SP ₂ and SP ₃ sent from SW ₃ , SJ ₁ are connected to the output terminal of the AND circuit AD ₂ shown in Fig. 4, and the input terminal of the judgment signal S J, and CNT ₁ is connected to the input terminal of the judgment signal S _J shown in Fig. 5. The input terminal of the judgment signal CNT is connected to the output terminal of the NOR circuit NOR ₂ shown in FIG. input terminal
SW ₂₁ , SJ ₁ , and CNT ₁ are each connected to the input terminal of an AND circuit AD ₅ , and the output terminal of this AND circuit AD ₅ is connected to the clock pulse input terminal CL of FF ₄ . The J and K terminals of FF ₄ are connected to the positive power supply +V and the negative power supply -V, respectively, and the Q terminal of FF ₄ is connected to the control signal sending terminal G and the input terminal of timer TM ₂ , and one input terminal is AND circuit AD ₆ connected to terminal SW ₂₁ and one input end connected to terminal
It is connected to the other input end of the AND circuit AD ₇ , which is connected to SW ₃₁ . Timer TM ₂ is connected to the R terminal of FF ₄ .
The output end of an OR circuit _OR3 whose inputs are the output of the AND circuit _AD6 and the output of the AND circuit AD6 are connected. The output terminal of the AND circuit _AD7 is connected to the S terminal of the FF ₅ , and the Q terminal of the FF ₅ is connected to the coin counting signal sending terminal _CN10 and to the input terminal of the timer _TM3 . The output terminal of timer TM ₃ is
Connected to FF ₅ 's R terminal.

In such a distribution control circuit, FF ₄ and FF ₅ are in a reset state in a standby state. When a specie coin is inserted from the coin input slot 11, a judgment signal _SJ as shown in section () in Fig. 8f is output from the terminal.
SJ ₁ , and a judgment signal CNT as shown in section () in Figure 8 h is input to terminal CNT _1. When the inserted coin reaches the position of coin detector SW ₂ , the signal shown in Figure 8 b is input to terminal CNT 1. Detection signal as shown in category ()
By inputting SP ₂ to terminal SW ₂₁ , the AND condition of AND circuit AD ₅ is satisfied. This allows FF ₄
is set, so "1" is sent from the Q terminal to G as a control signal as shown in section () in FIG. 8 j, and the distribution member 2 shown in FIG. As a result, the sorting machine body 1 caves in. Therefore, the input coins are sorted by the sorting member 2.
It falls in the storage direction A without being prevented from falling. When this coin reaches the position of the coin detector _SW3 , a detection signal _SP3 as shown in section () in FIG. 8c is sent to the AND circuit _AD7 via the terminal _SW31 .
is applied to one input terminal of At this time, the other input terminal of AND circuit AD ₇ is "1" on the Q terminal of FF ₄ .
Since is given, the AND condition is satisfied and FF ₅ is set. When FF ₅ is set, "1" is sent from the Q terminal to the terminal CN ₁₀ as a coin signal as shown in section () of k in Fig. 8, and the timer TM 3 starts time-limiting operation, and the timer TM ₃ starts to run for a predetermined time. Then reset FF ₅ . The timer TM ₂ starts its time-limited operation after "1" is generated at the Q terminal of the FF ₄ , and the timer TM 2 starts its time-limited operation after the time limit has elapsed, which is slightly longer than the time required for the inserted coin to pass through the position of the sorting member 2. Reset FF ₄ .

Next, when a specific coin is inserted or coins are continuously inserted, the judgment signal CNT becomes "0" as shown in division () in Fig. 8 h, so the AND condition of AND circuit AD ₅ is no longer satisfied. do not. Therefore, FF ₄ continues to be in the reset state, so the terminal G
The control signal for the distribution member 2 sent through the control signal remains at "0" as shown in section () in FIG. 8J. Therefore, the sorting member 2 protrudes above the sorting machine body 1, and the coins falling through the rolling path 12 are prevented from falling by the sorting member 2 and guided in the return direction B. In addition, FF ₁ and
If both FF ₂ are set within the screening period, the judgment signal S _J is set to the 8th one when the detection signal SP ₂ occurs.
As shown in the division () in _FIG . Then, as in the case where the inserted coin does not reach the position of the coin detector SW ₂ due to the operation of the return lever, the timer shown in Fig. 4 is activated.
TM ₁ operates for a limited time and produces an output as shown in section () in FIG. 8g, resets the up-down counter UD shown in FIG. 5, and returns to the standby state.

In the above embodiment, the coin detector SW ₂ only detects the passing of a coin;
It goes without saying that the coin properties may also be detected using the SW ₁ or the sorting coil 3. That is, a plurality of coin detectors (SW ₁ ,
A sorting coil, SW ₂ ) is arranged, and an up-down counter UD as a counting means as shown in FIG _.
The detection signal SP ₁ from the last stage coin detector SW ₂ is added and counted, and the detection signal SP ₂ from the last stage coin detector SW 2 is subtracted and counted, and the signal CNT indicating that the contents of this counter UD is zero is used to confirm the continuous input. A judgment is made, and if there is continuous input, the AND condition of AD ₅ in Figure 6 is prohibited from being satisfied and the input coins are refused to be accepted. Therefore, when the contents of this counter UD become zero after continuous input occurs, there are no coins between coin detectors SW ₁ and SW ₂ (all input coins are the coins of the last stage). This is when the coin has passed through the detector SW ₂ ), and from this point on, the next input coin will be used as shown in Figure 6.
The AND condition of AD ₅ can be satisfied. That is, the next inserted coin can be accepted from this time after the continuous insertion occurs (when the contents of the counter UD become zero).

Here, the plurality of coin detectors of the present invention are composed of a coin detector SW ₁ , a sorting coil 3 and a coin detector SW ₂ , and the acceptance judgment circuit includes the circuits shown in FIGS. 2 to 5 and the coin detector SW 2 . The flip-flop is composed of the flip-flop _FF4 of FIG. ₆ , the timer is composed of the timer _TM2 of FIG. 6, and the counting means is composed of the up-down counter UD of FIG. , the count content detection means is constituted by the NOR circuit NOR ₂ shown in Fig. 5, and the gate circuit is constituted by the AND circuit AD ₅ shown in Fig. 6.
It is made up of.

〔Effect of the invention〕

According to the present invention as described above, the detection signals from the first stage coin detector among the plurality of coin detectors arranged along the coin path are added and counted, and the detection signal from the last stage coin detector is detected. A counting means for subtracting and counting the signal is provided, and a judgment as to whether or not to accept the coins is made based on the count contents of this counting means, so that when all continuously inserted coins have passed through the last stage coin detector, It becomes possible to accept the next inserted coin, and there is no inconvenience that coins that have been returned due to continuous insertion are reinserted and returned again.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of the arrangement of a coin detector and sorting member, etc. of the present invention, and FIGS. 2 to 5 are circuit diagrams showing an embodiment of the acceptance determination circuit of the present invention. FIG. 6 is a circuit diagram showing one embodiment of the gate circuit and flip-flop of the present invention, and FIGS. 7 and 8 are waveform diagrams showing the operation of this embodiment. 1... sorting machine main body, 2... sorting member, 3,
SW ₁ , SW ₂ ...Selection coil and coin detector as a coin detector, 11...Coin slot, 12...Rolling path, A...Accepting path, B...Returning path, FF ₄ ...Flip-flop, TM ₂ ...Timer, AD ₅ ...AND circuit as a gate circuit, UD...up-down counter as a counting means, NOR ₂ ...NOR circuit as a counting content detection means.

Claims (1)

[Claims] 1. A rolling path on which coins inserted from a coin insertion slot roll, a plurality of coin detectors that are sequentially provided along the rolling path and detect the properties or passage of the inserted coins, and the plurality of coins. an acceptability determining circuit that integrates the outputs of the detector and determines acceptability based on the continuous input of the coins and authenticity; a flip-flop that is set based on the acceptability determination output of the circuit; and the flip-flop that is set. a timer for resetting the flip-flop after a predetermined time after the flip-flop has passed; and a distributing member for distributing the inserted coins that are set in a first state by a reset output of the flip-flop and set in a second state by a set output and have passed through the plurality of coin detectors. , a coin sorting device comprising a return path through which the inserted coins are guided according to a first state of the sorting member, and a receiving path through which the input coins are guided according to a second state of the sorting member, wherein the plurality of coins Add and count the passing detection signals from the first stage of the detector,
A counting means for subtracting and counting the passage detection signal from that of the last stage, a counting content detecting means for detecting and outputting a count content of the counting means as a predetermined value, and a condition that the output of the means is sent. A coin sorting device characterized in that the acceptability determining circuit includes a gate circuit that sends out the acceptability determining output.