JPH0241548A - I/o interrupt control system - Google Patents

Abstract

PURPOSE:To smoothly change the processing on the way at the time of preliminarily chaining input/output device control information by checking preceding input/output operations by the interrupt of the I/O adapter, which detects a flag in a DCW (input/output control information), to change following input/ output operations. CONSTITUTION:When preparing a series of chaining DCWs 11, a CPU 1 preliminarily inverts the polarity of a flag bit 12 of the DCW 11 for the just preceding processing if there is probability that the following processing is changed by results of preceding processings. When reading out the DWC 11 for the input/ output operation from a main storage 2 to detect that the flag is '1', I/O adapters 4 and 5 generate an interrupt to the CPU 1 to report the state after terminating the input/output operation related to the DCW 11. Adapters 4 and 5 find release of input/output operation suppression by the report from the CPU 1 and start the sequential execution from the next DCW 11. Thus, the processing is efficiently and smoothly changed on the way of input/output operations related to chaining DCWs.

Description

[Detailed Description of the Invention] [Summary] An I/O device that controls data transfer between an input/output device and main memory.
Regarding the control of input/output devices in a system where the O adapter operates asynchronously with the central processing unit, the purpose of this is to smoothly change the process midway when input/output device control information is chained in advance. At least a 1-bit flag is provided in the device control information, and if the flag is in a specific state when the I/O adapter reads the input/output device control information, the I/O adapter performs processing related to the input/output device control information. Generates an interrupt to the central processing unit to generate a status report, and performs processing related to input/output device control information that is chained to the input/output device control information until an instruction is given from the central processing unit corresponding to the interrupt. It is configured by providing a means to inhibit execution.

[Industrial application field]

The present invention provides the above-mentioned method in which an I/O adapter having an input/output device is specified by a central processing unit (hereinafter also referred to as CPU).
．． An input/output device in a system configured to read input/output device control information from an address on α and control data transfer between the input/output device and main memory according to the contents of the control information asynchronously with the CPU. Regarding control, the present invention particularly relates to means capable of changing human output device control information that has been chained in advance (hereinafter also referred to as chain) in accordance with processing results and the like.

[Conventional technology]

FIG. 3 is a diagram explaining the operation of the I/O adapter.

In the figure, 51 is a CPU, 52 is a main memory, 53 is a system bus, 54.55 is an I/O adapter, 56° 57
is an input/output device (hereinafter also referred to as I/O. In the figure, Il
o), 58.59 is l/O56, respectively.
．． 57 corresponds to a unit control word (hereinafter also referred to as UCW, also written as UCW in the figure), 60 corresponds to a device control block (hereinafter also referred to as DCB, also written as DCB in the figure), 61 is a device control It represents the word Iff (hereinafter, the device control word is also referred to as DCW. It is also written as DCW in the figure).

Note that the above DCW corresponds to input/output device control information referred to in the claims of this specification. (In the following description, input/output device control information is also referred to as DCW.) When the system is in iPL, the operating system (O3)
notifies each I/O adapter of the first address in the DCBO header 1 that corresponds to each I/O machine number.

The I/O adapter maintains this in U CW as D CB A. As described above, the UCW exists corresponding to each ■/○.

When the CPU executes an input/output command and as a result instructs the ■/○ adapter to start Ilo, the corresponding I/O
For the O adapter, check the DCBA in the UCW and use the above 1. D of scar
Know the start address of the CB, and then select D from the contents of the DCB.
The first address of the CW is obtained, the DCW is read from the address, and input/output operations are performed according to the contents.

At this time, if a chain display (data chain or command chain) is made in DCW, the contents of the next DC''vV are automatically executed.

Therefore, when each D CW is configured as a chain, the I/O adapter performs I/O completely asynchronously with the CPU.
He will concentrate on his imperial work.

[Problem to be solved by the invention]

In recent years, as the functions of I/O devices have become more sophisticated and control has become more complex, the CPU often has to synchronize and issue control instructions to the I/O devices, and it has become necessary to perform processing quickly. I'm in a hurry.

Conventionally, the execution progress of the device control word is sequentially reported to the CPU (for example, the memory address and status indicating the DCW to be executed next are notified), and the CPU checks the report contents. A method has been adopted in which a flag is provided in the device control word and the execution of the device control word is thereby postponed until an instruction from the CPU is given.

Among these conventional methods, in the former method of sequentially reporting the execution progress of the device control word (DCW) to the CPU, the I/O adapter reports to the CPU each time it executes one DC'vV. Since it is a system, there are many system losses, and there are also problems in that it is difficult to deal with a situation in which the CPU cannot immediately respond to a report.

In addition, even in the latter method in which a flag is provided in the DCW and the I/O adapter postpones execution of input/output operations related to the aD CW, the CPU always
There was a problem in that the processing progress of related input/output operations had to be monitored in the corresponding DC'vV.

In view of such conventional problems, the present invention provides a C
The CPU can efficiently and smoothly perform predefined I/O operations without reporting to the CPU or monitoring the progress of input/output operations.
It is an object of the present invention to provide a control method that can instruct an I/O adapter to perform an operation different from the /O operation.

When the pig reads input/output device control information, if the flag is in a specific state, after performing processing related to the input/output device control information, generates an interrupt to the central processing unit to generate a status report; An I/O interrupt control method that includes means for suppressing execution of processing related to input/output device control information chained to the input/output device control information until an instruction from a central processing unit corresponding to the separation is given. It is.

[Means to solve the problem]

According to the invention, the above-mentioned objects are achieved by the means specified in the claims. That is, in the present invention, an I/O adapter having an input/output device reads input/output device control information from an address on the main memory specified by the central processing unit, and controls the input/output device and the above (, In a system configured to control data transfer to and from α, at least a 1-bit flag is provided in the input/output device control information, and the I/O adder [Function] In the above means, CPtJ When preparing (chained) human output control information (DCW), if there is a possibility that the subsequent processing will be changed depending on the results of the previous processing, the DCW for performing the immediately preceding processing is prepared in advance.
The polarity of the W flag bit is inverted. for example,
Normally, when the flag bit is in the state of "0", it is set to "1".

[/○ The adapter uses DCW as described in 1. to perform input/output operations. If the above flag is “1” when read from the key, the CPU
generates an interrupt and reports the status.

At this time, for example, the CPU checks the normality of the processing of input/output operations related to a series of DCWs, then modifies the DCW that the adapter is supposed to execute as necessary, and then requests the adapter to receive interrupts. Notification will be given accordingly. The adapter is
Based on the notification from the CPU, the CPU learns that the input/output operation suppression has been lifted, and starts sequential execution from the next DCW.

〔Example〕

FIG. 1 is a block diagram of one embodiment of the present invention.

In the figure, 1 is the CPU, 2 is the main memory, 3 is the system bus, 4.5 is the I/O adapter, and 6°7 is the input/output device (
Ilo), 8.9 is a unit control word (UCW) corresponding to l/O6 or 7, respectively, IQ is a device control block (DCB), 111 to lln are device control words (DCW), respectively, 12. ~12n is a flag bit, ■3 is a device status word (DSW),
14 represents a flag detection section, and 15 represents a control section.

System IPLR, operating system (O8)
) notifies each ■/○ adapter of the first address in the main memory of the DCB corresponding to each I/O machine number.

The I/O adapter maintains this as a DCBA in the U CW. As described above, the U CW exists corresponding to each I/O.

The CPU executes input/output instructions, resulting in, for example, I
When the I/O adapter 4 is instructed to start the l/O6, the I/O adapter 4 looks at the DCBA in the UCWS, learns the start address of the DCBIO in 11) above, and then starts the DCBIO.
The first address of DCW is obtained from the contents of CB, DCWiL is read from the address, and input/output operations are performed according to the contents.

At this time, if a chain display (data chain or command chain) is made in DCW111, the contents of the next DCW112 are automatically executed.

Therefore, if each DCW is configured as a chain, the I/O adapter will concentrate on I/O operations completely asynchronously with the CPU.

If there is a possibility that depending on the processing result, it is necessary to perform an input/output operation that differs from the contents of the DCW set in advance in Ilo, the CPU will The DCW flag bit of is set to "1".

The flag detection unit 14 of the I/O adapter 4 detects that the I/O adapter 4 is active 1. ! When reading DCW from 2, DCW
The state of the flag bit is checked, and if it is "1", it is immediately notified to the control unit 15.

At this time, the control unit 15 generates an interrupt to the CPU 1, edits the status related to input/output operations up to that point, creates a device status word (DSW), and reads the DCBI of the main memory.
Store in O.

Then, input/output operations related to the next DCW are suppressed until a notification is received from the CPU.

FIG. 2 is a time chart showing an example of the operation of the embodiment.

In the same figure, ■ to ■ indicate 0 to ■ in the following explanation.
Corresponds to the explanation of item 0.

(2) It is assumed that there is a DCW group for controlling a series of I/O devices, and this is indicated as command chain 1.

■ If you want to see the processing progress of the I/O device, set the program control interrupt flag ("P" flag) to 1 in DCW.
”.

■ After the CPU instructs the I/O adapter to start up, if the adapter detects a DCW with the "P" flag set to "1" while executing DCWs sequentially, after executing the command instructed by that DCW. , a device status word (DSW), and issues an interrupt request to the CPU.

■ The CPU accepts the interrupt request, checks the data and the Ilo and I/O adapter status information shown in the DSW, modifies and changes the DCW that the I/O adapter is supposed to execute afterwards, and executes the I/O adapter. Notifies the O adapter that 1 interrupt has been accepted.

- After receiving an instruction from the CPU to accept an interrupt, the I/O adapter resumes processing and sequentially executes commands from the next DCW.

[Effects of the Invention] As explained above, according to the present invention, the CPU sets a flag in the DCW as necessary, and the interrupt of the I/O adapter that detects the flag sets the flag until then. It is possible to check the input/output operations of the system and control subsequent changes in input/output operations.

Therefore, there is no need for the CPU to constantly monitor the processing progress of the I/O adapter as in the past, and there is no need for the I/O adapter to report to the CPU every time the input/output operation related to one DCW is completed. No processing required.

Therefore, DCW is efficiently and smoothly chained.
There is an advantage that input/output operations related to the above can be changed midway.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a time chart showing an example of the operation of the embodiment, and FIG. 3 is a diagram explaining the operation of an I/O adapter. 1...CPU, 2...[l:! , 3... System bus, 4.5... I/O adapter, 6.7... Input/output device, 8.9... UCW, /O... DCB, 11
．． ~11,...Dcw, t2. ~12. ...Flag bit, 13-D SW.

Claims (1)

[Claims] An I/O adapter having an input/output device reads input/output device control information from an address on the main memory specified by the central processing unit, and controls the input/output device and the main memory according to the contents of the control information. In a system configured to control data transfer between If the input/output device control information is in the current state, after performing processing related to the input/output device control information, an interrupt is generated to the central processing unit to generate a status report, and the input/output device is processed until an instruction is given from the central processing unit corresponding to the interrupt. 1. An I/O interrupt control method, comprising means for inhibiting execution of processing related to input/output device control information chained to output device control information.