JPH0240750A - Peripheral controller - Google Patents

Abstract

PURPOSE:To disconnect a power source without exerting any influence upon a normal system by providing a device which instructs on-line processing and a device which transfers data between peripheral controllers and stopping all functional operations of a peripheral controller to be powered off. CONSTITUTION:When an A peripheral device 20 is powered off, an operator operates resource control information in a CPU 10 to stop a new input/output instruction to the A peripheral controller 20. Then the CPU 10 uses a B peripheral controller 21 to carry on access to a storage device group 80. Then the operator turns off an A on-line switch 30. Then, an A microprocessor 40 detects the state transition to the off state of the switch 30, inhibits new data from being stored in an A buffer storage 60 from a B peripheral controller 21, and then sends the data in the storage 60 to a B buffer storage 61 by using a communication path 1 between processors. The data which are transferred to the storage 61 are written in the device group 80 under the control of a B microprocessor 41.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a peripheral control device, which has a buffer memory for temporarily storing write data during busy periods, and is capable of transferring data between a host device and the buffer memory; The present invention relates to a peripheral control device that asynchronously transfers data between a storage device and a buffer storage.

[Conventional technology]

Some medium-sized and large-sized peripheral control devices have buffer storage to absorb the difference in data transfer speed between the channel interface and the drive interface. A write operation via buffer storage is performed by first receiving write data from a channel, storing it in the buffer storage, and writing the write data in the buffer storage to the storage device asynchronously with the channel interface.

On the other hand, the storage subsystem is usually configured on two access paths, and even if a failure occurs in a device on one access path, the buffer storage of each of the two peripheral control devices on the other access path is Input/output operations can be performed by selecting either local system buffer storage or external system buffer storage to enable access from peripheral control devices on the other side as well, and to improve subsystem usage efficiency and response time. Efforts are being made to do so.

[Problem to be solved by the invention]

While the storage subsystem configured as above is in operation, if one peripheral control device is powered off for the purpose of failure maintenance, preventive maintenance, etc., access to the peripheral control device on the side where the power is cut off is required. Simply making it unusable on the resource management information above the path will not allow usable access iJ? This is insufficient because it cannot exclude the possibility that input/output operations from the power source are processed using the buffer storage in the peripheral control device on the side where the power is turned off, and the operation to turn off the power is The disadvantage was that the entire subsystem had to be made unavailable during that time.

[Means for solving problems]

The peripheral control device of the present invention, which has a buffer memory and performs data transfer between host device buffer memories and data transfer between storage device buffer memories asynchronously, includes means for instructing two peripheral control devices to go offline; The present invention is characterized in that it has means for transferring data in its own buffer memory to the buffer memory of another peripheral control device that controls the same storage device when the memory device is issued.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The A peripheral control device 20 operates under microprogram control by the A microprocessor 40 and the B microprocessor 41. Both the A and B microprocessors 40 and 41 are connected by an interprocessor communication node 1, and can mutually communicate control information.Write data sent from the central processing unit 10 issues a write instruction. - Eight output adapters 50 on the access path
Or, via the B input/output adapter 51, it is stored in the A buffer memory 60 or the B buffer memory 61 selected by an appropriate algorithm. The stored write data is written to one of the storage device group 80 via each A formatter 70 and B formatter 71.

A online switch 30 and B online switch 3
1 is a switch that can be manually operated, and microprocessors 40 and 41 6D, A and B monitor the state transition of this switch at appropriate intervals.

When turning off the power to the A peripheral control device 20, the operator first operates the resource management information in the central processing unit 10 to stop new input/output instructions to the A peripheral control device 20. The central processing unit 10 can continue to access the storage device group 80 using the eight peripheral controllers 21 .

Since the 8th peripheral control device 21 does not know that the input/output instruction to the 8th peripheral control device 20 has stopped, it still assumes that the A buffer storage 60 is usable.

Conversely, since the load on the 8-peripheral control device 21 increases, it is predicted that the frequency of use of the A-buffer storage 60 will increase.

Next, the operator turns off the A online switch 30-. The microprocessor 40 detects the state transition of the A online switch 30 to the OFF state and prohibits the A buffer memory 6o from storing new data from the peripheral controller 21, and then stores the data in the A buffer memory 60. It is transferred to B buffer storage 61 using interprocessor communication A bus 1.

The data transferred to the B buffer storage 61 is written to the storage device group 80 under the control of the B microprocessor 41.

〔Effect of the invention〕

As explained above, the peripheral control device of the present invention is provided.

It has means for instructing online operation and means for transferring data between peripheral control devices.

This has the advantage that it is possible to stop all functional operations of the peripheral control device whose power is to be cut off, and therefore the power can be cut off without affecting the normal system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a peripheral control device according to the present invention. Explanation of symbols: 1... Inter-processor communication path. ...Central processing unit. 21...A B peripheral control device Place, 30 1...A B online switch. Buffer memory. 1...A B formattuta. 0...Storage device group. No. figure

Claims (1)

[Scope of Claims] 1. In a peripheral control device that has a buffer memory and performs data transfer between a host device and the buffer memory and data transfer between the storage device and the buffer memory asynchronously, the peripheral control device is configured to take the peripheral control device offline. A peripheral characterized in that it has means for instructing, and means for transferring data in its own buffer memory to the buffer memory of another peripheral control device that controls the same storage device when the offline instruction is issued. Control device.