JPH023992A - Manufacture of solar cell - Google Patents
Manufacture of solar cellInfo
- Publication number
- JPH023992A JPH023992A JP63152371A JP15237188A JPH023992A JP H023992 A JPH023992 A JP H023992A JP 63152371 A JP63152371 A JP 63152371A JP 15237188 A JP15237188 A JP 15237188A JP H023992 A JPH023992 A JP H023992A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- junction
- doped
- substrate temperature
- cdte
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 229910004613 CdTe Inorganic materials 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000012535 impurity Substances 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 18
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 14
- 238000009826 distribution Methods 0.000 abstract description 12
- 238000009792 diffusion process Methods 0.000 abstract description 9
- 239000010409 thin film Substances 0.000 abstract description 7
- 239000000969 carrier Substances 0.000 abstract description 6
- 229910021478 group 5 element Inorganic materials 0.000 abstract description 2
- 239000002019 doping agent Substances 0.000 abstract 4
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 129
- 239000010408 film Substances 0.000 description 13
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- -1 hydrogen compound Chemical class 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 150000002902 organometallic compounds Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000005979 thermal decomposition reaction Methods 0.000 description 2
- 101100215641 Aeromonas salmonicida ash3 gene Proteins 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- VQNPSCRXHSIJTH-UHFFFAOYSA-N cadmium(2+);carbanide Chemical compound [CH3-].[CH3-].[Cd+2] VQNPSCRXHSIJTH-UHFFFAOYSA-N 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- NZQSCKCTGMHIRY-UHFFFAOYSA-N ethylindium Chemical compound CC[In] NZQSCKCTGMHIRY-UHFFFAOYSA-N 0.000 description 1
- ILXWFJOFKUNZJA-UHFFFAOYSA-N ethyltellanylethane Chemical compound CC[Te]CC ILXWFJOFKUNZJA-UHFFFAOYSA-N 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005092 sublimation method Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Photovoltaic Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はｐｎ接合を利用する太陽電池もしくは各種電子
デバイスの製造方法、特にｐｎ接合型ＣｄＴｅ太陽電池
の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing solar cells or various electronic devices using a pn junction, and particularly to a method for manufacturing a pn junction type CdTe solar cell.
（従来の技術）
ｐｎ接合型太陽電池においては、ｐｎ−ＣｄＴｅセルを
使ったものが最も高いエネルギ変換効率が予想される。(Prior Art) Among pn junction solar cells, those using pn-CdTe cells are expected to have the highest energy conversion efficiency.
このｐｎ−ＣｄＴｅセルの製造方法としては、ｎ型Ｃｄ
Ｔｅ単結晶基板上にｐ型ＣｄＴｅ薄膜を近接昇華法によ
って積層させる方法が知られている。The method for manufacturing this pn-CdTe cell is to
A method is known in which a p-type CdTe thin film is laminated on a Te single-crystal substrate by a proximity sublimation method.
しかし、このような従来の製造方法では、セルの遺産性
及び大面積化において問題があった。そこで、■族ある
いは■族元素を含む有機金属化合物と■族あるいはＶ族
の水素化合物（もしくはアルキル化合物）の熱分解反応
を利用した気相成長法である有機金属化合物法（ｍｅｔ
ａｌ−ｏｒｇａｎｉｃ ｃｈｅｍｉｃａｌ ｖａｐｏｒ
ｄｅｐｏｓｉｔｉｏｎ：以下ＩＪ Ｄ ＣＶ Ｄ法と
いう。）を利用したＣｄＴｅセルの製造が考えられてい
る。このＭＯＣＶＤ法においては、膜厚や組成の制御性
が優れており、量産性に富む等の長所がある。しかしな
がら、ＭＯＣＶＤ法を利用したＣｄＴｅ薄膜の製造に関
しては、ノンドープＣｄＴｅエピタキシャル膜の製造に
関するものが知られているのみであり、良好なｐｎ接合
の製造条件に関する記述はほとんどない。However, such conventional manufacturing methods have problems in terms of cell inheritance and large area. Therefore, the organometallic compound method (met) is a vapor phase growth method that utilizes the thermal decomposition reaction of an organometallic compound containing a group II or group III element and a hydrogen compound (or alkyl compound) of a group III or V group.
al-organic chemical vapor
Deposition: Hereinafter referred to as IJDCVD method. ) is being considered for manufacturing CdTe cells. This MOCVD method has advantages such as excellent controllability of film thickness and composition, and excellent mass productivity. However, regarding the production of a CdTe thin film using the MOCVD method, only the production of a non-doped CdTe epitaxial film is known, and there is almost no description regarding the production conditions for a good pn junction.
通常、ＭＯＣＶＤ法を用いてｐｎ接合型太陽電池を製造
しようとする場合、ｐ層とｎ層の間で不純物の相互拡散
が生ずるため、ｐｎ接合界面の位置が当初に設定した位
置とずれてしまい、又ｐｎ各層での不純物の深さ方向の
分布が当初に設計した分布からずれてしまい、場合によ
ってはｐｎ接合の製造ができなくなってしまう、などの
問題が生ずる。これらの問題によって、太陽電池の短絡
光電流および光起電力の低下が生じ、太陽電池のエネル
ギ変換効率を減少させてしまい、良好なρｎ接合型太陽
電池を製造することができなかった。Normally, when attempting to manufacture a p-n junction solar cell using the MOCVD method, interdiffusion of impurities occurs between the p-layer and n-layer, so the position of the p-n junction interface deviates from the initially set position. Moreover, the distribution of impurities in the depth direction in each pn layer deviates from the originally designed distribution, and in some cases, problems arise, such as making it impossible to manufacture a pn junction. These problems cause a decrease in the short-circuit photocurrent and photovoltaic force of the solar cell, which reduces the energy conversion efficiency of the solar cell, making it impossible to manufacture a good ρn junction solar cell.
（発明が解決しようとする課題）
従ってＭ ＯＣＶ Ｄ法によりｐｎ接合型ＣｄＴｅ太陽
電池を製造するに際してｐ層及びｎ層間での不純物相互
拡散によって生じるｐｎ接合界面の位置の設定位置から
のずれ、及びｐｎ各層における不純物の深さ方向の分布
のずれを低減させる必要がある。本発明の目的はこのよ
うな問題を解消し、Ｍ ＯＣＶ Ｄ法を用いてエネルギ
変換効率の高いｐｎ接合型ＣｄＴｅ太陽電池を製造する
ためのｐｎ接合形成条件を提供することである。(Problems to be Solved by the Invention) Therefore, when manufacturing a pn junction type CdTe solar cell by the MOCVD method, the position of the pn junction interface is deviated from the set position due to impurity interdiffusion between the p layer and the n layer, and It is necessary to reduce the deviation in the distribution of impurities in the depth direction in each pn layer. An object of the present invention is to solve such problems and provide pn junction formation conditions for manufacturing a pn junction type CdTe solar cell with high energy conversion efficiency using the MOCVD method.
（課題を解決するための手段）
本発明は、ｐｎ接合型ＣｄＴｅ太陽電池をＭＯＣＶＤ法
により作成するにあたって基板上に第１層として第１の
基板温度でｎ型ＣｄＴｅ層を形成し、第２層として前記
第１の基板温度より低い第２の基板温度でノンドープＣ
ｄＴｅ層を形成し、第３層として前記第１の基板温度よ
り低い第３の基板温度でｐ型［：ｄＴｅ層を形成し、前
記第２層を第１層と第３層からの不純物の拡散により第
２層が１層として残らず、かつ、第１層及び第３層間の
不純物の相互拡散を制御するような厚さに形成すること
を特徴とするものである。(Means for Solving the Problems) In producing a pn junction type CdTe solar cell by the MOCVD method, the present invention forms an n-type CdTe layer as a first layer on a substrate at a first substrate temperature, and forms a second layer on a substrate at a first substrate temperature. as non-doped C at a second substrate temperature lower than the first substrate temperature.
forming a p-type [:dTe layer as a third layer at a third substrate temperature lower than the first substrate temperature; forming the second layer with impurities from the first and third layers; It is characterized in that the second layer is formed to such a thickness that no single layer remains due to diffusion, and that interdiffusion of impurities between the first layer and the third layer is controlled.
（作 用）
上述の通り、本発明においては、ＩＪＯｃＶＤ法によっ
てｐｎ接合型太陽電池を製造するに際して問題となるｎ
層、ｎ層間での不純物の相互拡散をｐ層とｎ層との間に
ノンドープ層を入れることによって抑制している。即ち
、ｐ層とｎ層との間にノンドープ層設けることにより、
ｐ層形成時にｐ層側からの不純物の拡散がこのノンドー
プ層によって抑制され、ｐｎ接合界面位置及びｐｎ各層
の不純物の分布が所定の位置および所定のパターンとな
るように制御することができる。このｐ層とｎ層の間に
入れるノンドープ層は真性半導体に非常に近い特性を示
すものである。このためノンドープ層の厚さが厚すぎる
とｐｎ接合ではな（ｐｉｎ接合となってしまい太陽電池
特性が低下する。又逆にノンドープ層が薄すぎる場合に
は不純物の相互拡散を抑制しきれずｐｎ接合間でキャリ
ア濃度の分布にだれを生ずるため当初設定した通りの太
陽電池特性を得ることができない。本発明では、ｐｎ接
合界面位置及びｐ層ｎ層各層の不純物の分布を所定の位
置及び所定のパターンに設定できるようにｐ層ｎ層間で
の不純物の相互拡散を抑制し、良好なｐｎ接合型太陽電
池特性を与えるようなノンドープ層の形成に関する条件
（膜厚、成膜時の基板温度）を明らかにしている。(Function) As described above, in the present invention, n which is a problem when manufacturing pn junction solar cells by the IJOcVD method is
Mutual diffusion of impurities between the p-layer and n-layer is suppressed by inserting a non-doped layer between the p-layer and n-layer. That is, by providing a non-doped layer between the p layer and the n layer,
During the formation of the p-layer, diffusion of impurities from the p-layer side is suppressed by this non-doped layer, and the pn junction interface position and the distribution of impurities in each pn layer can be controlled to be at a predetermined position and in a predetermined pattern. The non-doped layer inserted between the p-layer and n-layer exhibits characteristics very close to those of an intrinsic semiconductor. For this reason, if the thickness of the non-doped layer is too thick, it will not be a p-n junction (pin junction) and the solar cell characteristics will deteriorate.On the other hand, if the non-doped layer is too thin, it will not be possible to suppress the interdiffusion of impurities, resulting in a p-n junction. It is not possible to obtain the solar cell characteristics as originally set because the distribution of carrier concentration between the two layers is distorted.In the present invention, the p-n junction interface position and the impurity distribution in each layer of the p-layer and n-layer are adjusted to a predetermined position and a predetermined value. Conditions for forming a non-doped layer (film thickness, substrate temperature during film formation) that suppress mutual diffusion of impurities between the p-layer and n-layer and provide good pn junction solar cell characteristics so that the pattern can be set are determined. It's clear.
本発明の太陽電池製造方法では、Ｉｎ等の■族元素をド
ナー不純物としてドープしたｎ型ＣｄＴｅ薄膜を４００
℃〜６００℃の基板温度で成膜し、次に膜厚１００人〜
５００人の厚さのノンドープＣｄＴｅ層を３００℃〜３
８０℃の基板温度で積層する。そのあと、Ａｓ等のＶ族
元素をアクセプタ不純物としてドープしたｐ型ＣｄＴｅ
薄膜をやはり３００℃〜３８０℃の基板温度で積層する
。このように、ｐｎ接合形成プロセスにおいて、ｎ層と
ｐ層の間にノンドープＣｄＴｅ層をはさむことによって
、最初に設計したｐｎ接合位置及びｐ層及びｎ層での不
純物の深さ方向の分布と、実際のｐｎ接合位置及び不純
物の分布とのずれがｎ層とｐ層との間に形成したノンド
ープＣｄＴｅ層の膜厚間に限定されることとなる。ここ
でノンドープ層の厚さが１００ 人より薄いと、ノンド
ープ層の形成時に、下地となるｎ型ＣｄＴｅ層からＩｈ
等の不純物がノンドープ層に拡散し、ノンドープ層がｎ
型ＣｄＴｅ層のドナー濃度と同じ不純物濃度をもつ膜と
なってしまい、ノンドープ層を形成する意味がなくなっ
てしまう。又、ノンドープ層が１００Å以下の場合ｐ型
ＣｄＴｅ層形成時には、ｐ層からＡ５等の不純物が拡散
してきた時にバッファ層として働かず、不純物がｎ層ま
で拡散してしまう。In the method for manufacturing a solar cell of the present invention, an n-type CdTe thin film doped with a group Ⅰ element such as In as a donor impurity is
The film is formed at a substrate temperature of ℃ to 600℃, and then the film thickness is 100℃ to 600℃.
500mm thick non-doped CdTe layer at 300℃~3
Lamination is carried out at a substrate temperature of 80°C. After that, p-type CdTe doped with group V elements such as As as an acceptor impurity.
The thin film is also deposited at a substrate temperature of 300°C to 380°C. In this way, in the pn junction formation process, by sandwiching the non-doped CdTe layer between the n layer and the p layer, the initially designed pn junction position and the depth distribution of impurities in the p layer and n layer can be adjusted. The deviation from the actual pn junction position and impurity distribution is limited to the thickness of the non-doped CdTe layer formed between the n layer and the p layer. If the thickness of the non-doped layer is thinner than 100 nm, when forming the non-doped layer, the Ih
impurities such as are diffused into the non-doped layer, and the non-doped layer becomes
The resulting film has the same impurity concentration as the donor concentration of the type CdTe layer, and there is no point in forming a non-doped layer. Furthermore, when the non-doped layer is less than 100 Å, when forming a p-type CdTe layer, it does not function as a buffer layer when impurities such as A5 diffuse from the p layer, and the impurities diffuse to the n layer.
一方、ノンドープ層の厚さが５００八より厚い場合には
、ｎ層及びｐ層の各層から不純物が拡散してもなおノン
ドープ層が残存し、ｐｉｎ接合が形成されてしまうため
高効率の太陽電池を製造することができない。この残存
ノンドープ層の膜厚が１００Å以上となると、■−Ｖ特
性に影響を与えるのでそれより小さくするのが望ましい
。On the other hand, if the thickness of the non-doped layer is thicker than 500 mm, the non-doped layer will remain even after the impurities are diffused from each of the n-layer and p-layer, and a pin junction will be formed, resulting in a highly efficient solar cell. cannot be manufactured. If the thickness of this remaining non-doped layer exceeds 100 Å, it will affect the -V characteristics, so it is desirable to make it smaller.
次に成膜を行う際の基板温度は、上述した通り第１層（
ｎ層）は４００℃〜６００℃の範囲で、又第２層（ノン
ドープ層）及び第３層（ｐ層）はそれよりも低い３００
℃〜３８０℃の範囲に設定する。The substrate temperature during the next film formation is as described above for the first layer (
n layer) is in the range of 400°C to 600°C, and the second layer (non-doped layer) and third layer (p layer) are in the range of 300°C, which is lower than that.
Set in the range of ℃ to 380℃.
ノンドープ層である第２層の成膜時の基板温度は第１層
成膜時の基板温度より低く設定されているが、これは基
板温度を３８０℃以上にしてノンドープ層の成膜を行う
と、ノンドープ層の厚さにかかわらず下地となる第１層
すなわちｎ型ＣｄＴｅ層から不純物が拡散しノンドープ
層もｎ型ＣｄＴｅ層となってしまうからである。また第
２層成膜時の基板温度を３００℃以下とすると成膜速度
が遅くなり実用性を欠くこととなる。The substrate temperature when forming the second layer, which is a non-doped layer, is set lower than the substrate temperature during forming the first layer. This is because, regardless of the thickness of the non-doped layer, impurities diffuse from the underlying first layer, that is, the n-type CdTe layer, and the non-doped layer also becomes an n-type CdTe layer. Furthermore, if the substrate temperature during the second layer deposition is set to 300° C. or lower, the deposition rate will be slow and it will be impractical.
第３層即ちｎ型ＣｄＴｅ層の成膜時における基板温度も
、同様に第１層成膜時の基板温度より低く設定されてい
る。これは、ｐ層成膜時の基板温度を３８０℃以上にす
ると、ｎ層とｐ層の不純物の相互拡散が著しくなり、ｐ
ｎ接合界面が当初の設定位置より大幅に変化してしまい
、場合によってはｐｎ接合が形成できないこともあるた
めである。又第２層の場合と同様に基板温度が３００℃
以下になると成膜速度が遅くなってしまう。The substrate temperature during the formation of the third layer, that is, the n-type CdTe layer, is similarly set lower than the substrate temperature during the formation of the first layer. This is because when the substrate temperature during p-layer deposition is increased to 380°C or higher, interdiffusion of impurities between the n-layer and p-layer becomes significant, and the p-layer
This is because the n-junction interface changes significantly from the initially set position, and in some cases, it may not be possible to form a pn junction. Also, as in the case of the second layer, the substrate temperature is 300°C.
If it is less than that, the film formation rate will become slow.
これに対して第１層即ちｎ型ＣｄＴｅ層を形成する際に
は、上述したような下層からの拡散による問題は生じな
いので、ＣＪＴｅ層を良好にかつ成膜速度も速く成膜で
きる温度範囲である４００ ℃〜６００℃程度の基板温
度で成膜することとした。On the other hand, when forming the first layer, that is, the n-type CdTe layer, the above-mentioned problem due to diffusion from the lower layer does not occur, so the temperature range is within which the CJTe layer can be formed satisfactorily and at a high film formation rate. The film was formed at a substrate temperature of about 400°C to 600°C.
（実施例） 次に具体的に例を挙げて本発明を説明する。(Example) Next, the present invention will be explained with specific examples.
基板温度４２０℃に設定した石英ガラス基板（又はサフ
ァイヤ基板）上にジメチルカドミウム（以下Ｄ１．４
Ｃｄという。）とジエチルテルル（以下ＤＥＴｅという
。）を１対１の混合比で混合したガスにドナーとして働
くインジウムの有機化合物であるト。Dimethyl cadmium (hereinafter D1.4
It's called Cd. ) and diethyl tellurium (hereinafter referred to as DETe) in a 1:1 mixing ratio.
リエチルインジウム（以下ＴＥＩｎという）をモル分率
１０−３となる様に添加した後、高純度水素ガスをキャ
リアガスとして導き熱分解反応によって結晶成長させｎ
型ＣｄＴｅ薄膜を成膜する。この際の成膜速度は、約６
μｍ／時とすることができる。After adding ethyl indium (hereinafter referred to as TEIn) to a molar fraction of 10-3, high purity hydrogen gas was introduced as a carrier gas and crystals were grown by a thermal decomposition reaction.
A type CdTe thin film is formed. The film formation rate at this time was approximately 6
It can be μm/hour.
次にＴＥＩｎを添加していないＤＭＣｄとＤＥＴｅの混
合ガス（混合比１；１）を流し、基板温度を３８０℃へ
降温させノンドープＣｄＴｅ層を膜厚２００人となるよ
うにｎ型ＣｄＴｅ層の上に積層させる。このどきの成膜
速度は約５μｍ／時とすることができる。更に、Ｄ Ｍ
Ｃｄと ＤＥＴｅの混合ガス（混合比１：１．５）に
アクセプタとして作用するヒ素の水素化合物であるアル
シン（ＡＳＨ３）をモル分率１０−２になるように添加
し基板温度は３７０℃に設定してｎ型ＣｄＴｅ層を積層
させる。このようにしてｐｎ接合型ＣｄＴｅ太陽電池を
製造するが、第２層のノンドープ層にはｎ層からはｎ型
不純物であるＩ、、が、又ｐ層からｎ型不純物であるＡ
、が拡散し、その膜厚は２００人と薄いため真性半導体
としての性質を有する層は残らない。又、ｎ層の上に成
膜されたノンドープ層の存在により、ｐ層成膜時のｐ層
側からのＡ、のｎ層側への拡散が抑制され、ｐｎ接合位
置及びキャリアの深さ方向の分布を当初の設定位置、設
定値にコントロールすることができる。Next, a mixed gas of DMCd and DETe without adding TEIn (mixing ratio 1:1) was flowed, the substrate temperature was lowered to 380°C, and a non-doped CdTe layer was formed on the n-type CdTe layer to a thickness of 200 nm. Laminated on. The deposition rate at this time can be about 5 μm/hour. Furthermore, D.M.
Arsine (ASH3), a hydrogen compound of arsenic that acts as an acceptor, is added to a mixed gas of Cd and DETe (mixing ratio 1:1.5) at a molar fraction of 10-2, and the substrate temperature is set at 370°C. Then, an n-type CdTe layer is laminated. In this way, a pn junction type CdTe solar cell is manufactured, and the second non-doped layer contains n-type impurity I from the n layer, and n-type impurity A from the p layer.
, is diffused, and the film thickness is as small as 200 nm, so no layer having properties as an intrinsic semiconductor remains. In addition, due to the presence of the non-doped layer formed on the n-layer, the diffusion of A from the p-layer side to the n-layer side during the p-layer formation is suppressed, and the p-n junction position and the carrier depth direction are suppressed. distribution can be controlled to the initial setting position and setting value.
第１図Ａ及びＢはそれぞれｎ層とｐ層の間に３００人の
膜厚のノンドープ層を形成して製造したｐｎ接合ＣｄＴ
ｅ （第１試料）とノンドープ層を形成することなく作
ったｐｎ接合ＣｄＴｅ （第２試料）を二次イオン質
量分析法（ＳＩＭＳ：５ｅｃｏｎｄａｒｙ ｉｏｎ ｍ
ａｓｓＳｐｅｃｔｒｏｓｃｏｐｙ）により深さ方向の分
析を行い、その結果を示した図である。この図からノン
ドープ層を形成して作ったものよりもノンドープ層を形
成することなく作ったものの方がｐ層側から不純物Ａｓ
がｎ層側へより深く拡散していることがわかる。即ちノ
ンドープ層を入れずに作ったｐｎ接合ＣｄＴｅの方がｐ
ｎ接合界面の当初の設定位置からのずれが大きいという
ことになる。Figures 1A and 1B show p-n junction CdT fabricated by forming a non-doped layer with a thickness of 300 layers between the n-layer and p-layer, respectively.
e (first sample) and pn junction CdTe (second sample) made without forming a non-doped layer were subjected to secondary ion mass spectrometry (SIMS).
FIG. 3 is a diagram showing the results of analysis in the depth direction using assSpectroscopy. From this figure, it is clear that the impurity As from the p-layer side is higher than the one made without forming a non-doped layer.
It can be seen that is diffused deeper toward the n-layer side. In other words, p-n junction CdTe made without adding a non-doped layer has a higher p-n junction.
This means that the deviation from the originally set position of the n-junction interface is large.
第２図Ａ及びＢはそれぞれ前記第１試料と第２試料との
キャリア濃度を深さ方向に分析した結果を示すグラフで
ある。この図からノンドープ層を形成して作ったｐｎ接
合ＣｄＴｅでは表面からほぼ５０００人のところでキャ
リアの種類がｐ型からｎ型に急激に変化しており、ｐ型
キャリアの濃度もｐｎ接合界面で急激に減少している。FIGS. 2A and 2B are graphs showing the results of analyzing the carrier concentrations of the first sample and the second sample in the depth direction, respectively. This figure shows that in p-n junction CdTe made by forming a non-doped layer, the type of carrier changes rapidly from p-type to n-type at about 5000 layers from the surface, and the concentration of p-type carriers also changes rapidly at the p-n junction interface. has decreased to
これに対して、ノンドープ層を形成することなく作った
ｐｎ接合ＣｄＴｅでは、キャリアの種類は表面から５０
００八から７０００人くらいの範囲でゆるやかにｐ型か
らｎ型に変化しておりｐ型キャリアの濃度の減少の度合
もｎ型キャリア濃度の増加の度合も第２図Ａに比べてゆ
るやかなことがわかる。このことは、ノンドープ層を入
れることによって、アクセプタとして働＜ＡＳのｐ層形
成時のｎ層側への拡散が抑制されていることを示すもの
である。On the other hand, in pn junction CdTe made without forming a non-doped layer, the types of carriers are 50% from the surface.
There is a gradual change from p-type to n-type in the range from 0.08 to 7000, and the degree of decrease in the concentration of p-type carriers and the degree of increase in the concentration of n-type carriers are more gradual than in Figure 2 A. I understand. This shows that by including the non-doped layer, diffusion of AS acting as an acceptor to the n-layer side during formation of the p-layer is suppressed.
下の表１は、ｎ層とｐ層の間に３００への膜厚のノンド
ープ層を形成して製造したｐｎ接合太陽電池と、ノンド
ープ層を形成することなく製造したｐｎ接合太陽電池と
の光起電力を示すものである。Table 1 below shows the optical characteristics of a p-n junction solar cell manufactured by forming a non-doped layer with a thickness of 300 mm between the n-layer and p-layer, and a p-n junction solar cell manufactured without forming a non-doped layer. It shows electromotive force.
表 １
この表から、ｐｎ接合時にノンドープ層を入れて製造し
た太陽電池の方が、ノンドープ層を入れずに製造した太
陽電池よりも光起電力が大きいことがわかる。Table 1 From this table, it can be seen that the solar cell manufactured by adding a non-doped layer at the time of pn junction has a larger photovoltaic force than the solar cell manufactured without adding a non-doped layer.
（発明の効果）
上記に詳しく述べた通り本発明の太陽電池製造方法によ
ると、その製造過程においてｎ層とｐ層との間にノンド
ープ層をもうけているため、ｐ層成膜時におけるＡＳ等
の不純物のｎ層側への拡散が抑制され、ｐｎ接合位置、
及びキャリアの深さ方向分布を設定位置近傍、及び設定
値近傍になるようにコントロールすることができ、した
がって光起電力等の太陽電池の特性を向上させることが
できる。(Effects of the Invention) As described in detail above, according to the solar cell manufacturing method of the present invention, since a non-doped layer is formed between the n layer and the p layer during the manufacturing process, AS etc. The diffusion of impurities to the n layer side is suppressed, and the pn junction position,
It is possible to control the distribution of carriers in the depth direction so that they are near the set position and near the set value, and therefore the characteristics of the solar cell such as photovoltaic power can be improved.
第１図Ａ及びＢはＳｌ５Ｍによる深さ方向の不純物濃度
の変化を示すグラフ、
第２図Ａ及びＢは、キャリア濃度の深さ方向の変化を示
すグラフである。
第１図FIGS. 1A and 1B are graphs showing changes in impurity concentration in the depth direction due to Sl5M, and FIGS. 2A and B are graphs showing changes in carrier concentration in the depth direction. Figure 1
Claims (1)
作成するにあたって基板上に第１層として第１の基板温
度でｎ型ＣｄＴｅ層を形成し、第２層として前記第１の
基板温度より低い第２の基板温度でノンドープＣｄＴｅ
層を形成し、第３層として前記第１の基板温度より低い
第３の基板温度でｐ型ＣｄＴｅ層を形成し、前記第２層
を第１層と第３層からの不純物の拡散により第２層が１
層として残らず、かつ、第１層及び第３層間の不純物の
相互拡散を制御するような厚さに形成することを特徴と
するｐｎ接合型ＣｄＴｅ太陽電池の製造方法。1. When producing a p-n junction type CdTe solar cell by MOCVD method, an n-type CdTe layer is formed as a first layer on a substrate at a first substrate temperature, and a second layer is formed as a second layer at a temperature lower than the first substrate temperature. undoped CdTe at a substrate temperature of
forming a p-type CdTe layer as a third layer at a third substrate temperature lower than the first substrate temperature; 2 layers is 1
A method for manufacturing a p-n junction type CdTe solar cell, characterized in that it is formed to a thickness that does not remain as a layer and controls interdiffusion of impurities between the first layer and the third layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63152371A JPH023992A (en) | 1988-06-22 | 1988-06-22 | Manufacture of solar cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63152371A JPH023992A (en) | 1988-06-22 | 1988-06-22 | Manufacture of solar cell |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH023992A true JPH023992A (en) | 1990-01-09 |
Family
ID=15539066
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63152371A Pending JPH023992A (en) | 1988-06-22 | 1988-06-22 | Manufacture of solar cell |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH023992A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998000856A1 (en) * | 1995-11-09 | 1998-01-08 | Midwest Research Institute | Varible temperature semiconductor film deposition |
| JP2014072416A (en) * | 2012-09-28 | 2014-04-21 | Mitsubishi Electric Corp | Solar cell and manufacturing method therefor, solar cell module |
-
1988
- 1988-06-22 JP JP63152371A patent/JPH023992A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998000856A1 (en) * | 1995-11-09 | 1998-01-08 | Midwest Research Institute | Varible temperature semiconductor film deposition |
| US5712187A (en) * | 1995-11-09 | 1998-01-27 | Midwest Research Institute | Variable temperature semiconductor film deposition |
| JP2014072416A (en) * | 2012-09-28 | 2014-04-21 | Mitsubishi Electric Corp | Solar cell and manufacturing method therefor, solar cell module |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1148639A (en) | Multilayer photovoltaic solar cell with semiconductor layer at shorting junction interface | |
| US7122733B2 (en) | Multi-junction photovoltaic cell having buffer layers for the growth of single crystal boron compounds | |
| US4400221A (en) | Fabrication of gallium arsenide-germanium heteroface junction device | |
| US6482672B1 (en) | Using a critical composition grading technique to deposit InGaAs epitaxial layers on InP substrates | |
| US5407491A (en) | Tandem solar cell with improved tunnel junction | |
| JP4064592B2 (en) | Photoelectric conversion device | |
| US4392297A (en) | Process of making thin film high efficiency solar cells | |
| US9214580B2 (en) | Multi-junction solar cell with dilute nitride sub-cell having graded doping | |
| US5738732A (en) | Solar cell and manufacturing method thereof | |
| US4451691A (en) | Three-terminal ternary III-V multicolor solar cells and process of fabrication | |
| US6380601B1 (en) | Multilayer semiconductor structure with phosphide-passivated germanium substrate | |
| US4385198A (en) | Gallium arsenide-germanium heteroface junction device | |
| US20080149177A1 (en) | Apparatus and Method for Optimizing the Efficiency of Germanium Junctions in Multi-Junction Solar Cells | |
| CA1215457A (en) | Ternary iii-v multicolor solar cells containing a quarternary window layer and a quarternary transition layer | |
| WO2010151478A1 (en) | Method of making a semiconductor optical detector structure | |
| JPS61502020A (en) | Solar cells and photodetectors | |
| US4710786A (en) | Wide band gap semiconductor alloy material | |
| JP2722761B2 (en) | GaAs solar cell | |
| CA2711146A1 (en) | High efficiency silicon-based solar cells | |
| JPH023992A (en) | Manufacture of solar cell | |
| RU2366035C1 (en) | Way of realisation of structure of multilayered photo-electric converter | |
| KR950006965B1 (en) | Forming method of zn3p2 epitaxial thin film | |
| JPH10135494A (en) | Solar cell | |
| JPS6041269A (en) | Semiconductor device | |
| JPS61116823A (en) | Crystal growth method |