JPH0237811A - Sequence circuit for fet bias - Google Patents

Abstract

PURPOSE:To easily delay the ON-OFF of a FET bias at low cost on a small circuit scale by providing a time constant to a sequence circuit for the FET bias itself. CONSTITUTION:A capacitor 112 is connected between the emitter of a switching transistor 105 and the junction of resistances 110 and 111. consequently, a base current does not flow in the switching transistor 105 until the capacitor 112 is charged up with the time constant determined by the resistance value of the resistance 111 and the capacity value of the capacitor 112. After the capacitor 112 is charged up, the base current of the switching transistor 105 flows, thus, the collector current of the switching transistor 105 flows and a positive power is outputted to a positive power output terminal 103. Thus, the switching time of the switching transistor 105 lengthens and the ON-OFF of the bias voltage of the drain of a FET delays.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to FET (field effect transistor) amplifiers, and more particularly to FET (field effect transistor) amplifiers having a biasing sequence in which the gate of the FET is biased while the drain is biased. This invention relates to a sequence circuit for FET bias.

[Conventional technology]

An embodiment of a FET amplifier including a conventional FET biasing sequence circuit is shown in FIG.

In FIG. 2, the FET amplifier is composed of an FET bias sequence circuit 1, a bias circuit 2, and an FET 3. Further, the FET bias sequence circuit 1 has a positive power supply input terminal 101. Negative power input terminal 102. It is composed of switching transistors 105 and 106, a Zener diode 107, resistors 108, 109, and 110, a positive power output terminal 103, and a negative power output terminal 104. The bias circuit 2 has a positive power output terminal 103 and a negative power output terminal 104 of the FET bias sequence circuit 1.
, and supplies an appropriate bias voltage to the drain electrode 31 and gate electrode 32 of the FET 3.

Next, the operation of this FET amplifier will be explained.

First, the positive power input terminal 101 and the negative power input terminal 102
When the power is turned on, a negative voltage is output to the negative power output terminal 104, and the Zener diode 107 and resistor 108
, 109, the switching transistor 106 becomes O.
becomes N and base current flows.

Next, a collector current of the switching transistor 106 flows, which becomes a base current of the switching transistor 105, a collector current of the switching transistor 105 flows, and a positive power source is outputted to the positive power source output terminal 103. Positive power output terminal 103 and negative power output terminal 1
04 are coupled to the drain electrode 31 and gate electrode 32 of the FET 3 via the bias circuit 2, respectively.

In such a FET amplifier, the rise time of the bias voltage supplied to the FET 3 is the sum of the rise times of the switching operations of the switching transistors 105 and 106 (several tens of μs to several hundred μs).

pE including such a sequence circuit for FET bias
The T amplifier is used as a low-noise amplifier in a receiving device in a multilevel transmission system as shown in FIG.

In FIG. 3, 4 is a receiving antenna, 5 is a common amplifier,
6 is a frequency mixer, 7 is a crystal oscillator, and 8 is a demodulator. The common amplifier 5 is connected to the distributor 5 to improve line reliability.
1. It is composed of two low-noise amplifiers 52, 53 and a synthesizer 54, and even if one of the low-noise amplifiers 52 or 53 fails, a line error will not occur, and the low-noise amplifier 5
2 or 53 can be exchanged.

In this receiving device, radio waves received by the receiving antenna 4 are split into two by a divider 51, amplified by low noise amplifiers 52 and 53, and then combined by a combiner 54. The output of the synthesizer 54 is mixed in frequency with the output of the crystal oscillator 7 in the frequency mixer 6, converted into an IF frequency band, and supplied to the demodulator 8, where it is demodulated.

[Problem to be solved by the invention]

When the low noise amplifier 52 in the common amplifier described above breaks down and the power is turned off or turned on for replacement, the output amplitude of the synthesizer 54 will fluctuate by 6 dB and the phase will also fluctuate. This amplitude and phase fluctuation speed almost matches the switching time (several tens of μS to several hundred μS) of the switching transistors 105 and 106 of the FET bias sequence circuit 1 in FIG. Since the tracking speed for amplitude fluctuations, that is, fading, is extremely slow at several milliseconds, the demodulator 8 cannot follow the switching time of the sequence circuit, causing a line error.

Therefore, it is necessary to provide some kind of time constant circuit so that the amplitude and phase fluctuation speed of the low-noise amplifier 52 due to power ON/OFF is equal to or lower than the fluctuation tracking speed of the demodulator 8. Therefore, in order to lengthen the rise time of the power supply, an RC low-pass filter consisting of a resistor and a capacitor is connected to the low-noise amplifier 5.
There is a method of installing it in the second power supply line, but in the multi-level transmission method described above, the resistance and capacitance values are very large.
There are drawbacks such as increased cost and increased size.

[Means to solve the problem]

In order to solve the above problems, the FET bias sequence circuit of the present invention includes a switching transistor that supplies bias to the gate and drain of the FET with a time difference, and adds a time constant circuit to the switching transistor to increase the switching time. It's long.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a specific circuit diagram of an FET bias sequence circuit according to an embodiment of the present invention. The FET bias sequence circuit shown in FIG. 1 is characterized by adding a resistor 111 and a capacitor 112 to the FET bias sequence circuit 1 shown in FIG. In FIG. 1, the resistor 111
is connected between the switching transistor 106, the collector and the resistor 110, and the capacitor 112 is connected between the emitter of the switching transistor 105 and the resistor 110.
It is connected between the connection point of 10 and 111. Other circuit connections are the same as the 'If'ET bias sequence circuit 1 shown in FIG.

In the FET bias sequence circuit shown in FIG. 1, when power is applied to the positive power input terminal 101 and the negative power input terminal 102, a negative voltage is output to the negative power output terminal 104, and the Zener diode 107 and the resistors 108, 1
09, the switching transistor 106 is ONL.
When the base current of the switching transistor 106 flows, a collector current of the switching transistor 106 and a current flow through the capacitor 112 and the resistor 111.
The base current does not flow until the charger is turned off with a time constant determined by the capacitance value of 2.

Then, after the capacitor 112 is charged up, the base current of the switching transistor 1050 flows, so that the collector current of the switching transistor 105 flows, and a positive power source is output to the positive power source output terminal 103. In other words, Sui.

The switching time of the switching transistor 105 is longer.

Conversely, if the positive and negative side power supplies are turned off, the capacitor 11
Since the base current of the switching transistor 105 flows due to the charges charged in the transistor 2, the collector current of the switching transistor 105 flows, and a positive power source is outputted to the positive power source output terminal 103. Therefore, a sudden drop in the bias voltage of the drain of the FET can be reduced.

〔Effect of the invention〕

As explained above, the present invention provides a time constant to the FET bias sequence circuit itself, thereby making it possible to easily adjust the FET bias to 0N with a small circuit scale and at low cost.
-OFF can be delayed sufficiently.

[Brief explanation of the drawing]

FIG. 1 is a FET bias sequence circuit diagram according to an embodiment of the present invention, FIG. 2 is a circuit diagram of an FET amplifier using a conventional FET bias sequence circuit, and FIG.
FIG. 2 is a block diagram of a receiving device in a multi-value transmission system in which an FET amplifier including a FET bias sequence circuit is used. 101... Positive power input terminal, 102...
- Negative power input terminal, 103... Positive power output terminal, 104... Negative power output terminal, 105, 106...
...Switching transistor, 107...
... Zener diode, 108, 109, 110,
111...Resistor L112...Capacitor. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] A FET bias sequence circuit including a switching transistor that supplies bias to the gate and drain of an FET with a time difference, characterized in that a time constant circuit is added to the switching transistor to lengthen the switching time. .