JPH0237137B2 - FUGOKI - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an encoder with an offset compensation circuit.

The conventional encoder is equipped with an offset compensation circuit, and this offset compensation circuit is described in Research and Application Report Vol. 30, No. 7 (1981), pp. 1693-1698.
The paper by Iwata, Kikuchi et al., “Single channel
The sine-bit integration method proposed in "PCM CODEC LSI" is generally adopted.
This sine bit integration type offset compensation circuit uses a sine bit to adjust the amount of integration of a certain value based on the fact that the analog input signal has the same amount of positive and negative signals, and then feeds back the resulting voltage negatively. It operates to compensate for the DC offset voltage within the encoder.

FIG. 1 shows the input/output characteristics of an encoder using the A encoding rule, which is mid-riser encoding, and as is clear from the figure, it becomes binary and unstable at boundary points such as zero points. In the conventional offset compensation circuit using the sine bit integration method, the operating point of the encoder is the zero point, so if noise is superimposed on the input signal, even if the actual input signal is zero, the output signal will be (10000000) due to the noise. It will take two values: and (00000000). Therefore, when this encoder is used in a digital telephone system or the like, there is a drawback that noise during no calls becomes large.

The object of the invention is to provide a coder which eliminates the above-mentioned drawbacks.

The encoder of the present invention includes encoding means for converting each sample value of a sampled analog input signal into an m (an integer of 2 or more) bits digital signal, and a lower side ( m-1) control signal generating means for directly outputting the most significant bit of the m-bit digital signal or inverting the logic level and outputting the most significant bit based on the contents of the bit; and integrating the control signal from the generating means. offset compensating means for negatively feeding back the voltage obtained by the above to the encoding means, and the upper n (positive integer less than m) bits of the m-bit digital signal are used as the encoded output for the sample value. .

Next, the present invention will be explained in detail with reference to the drawings.

Referring to FIG. 2, one embodiment of the present invention is a sequential comparison type comprising a comparator (hereinafter referred to as a comparator) 1 and an array circuit 2 of capacitors and resistors connected to a non-inverting input terminal of the comparator 1. An encoding circuit 3, a 9-bit shift register 4 that sequentially takes in the output of the encoding circuit 3 one bit at a time, a control circuit 5 that controls 9-bit encoding in the encoding circuit 3, and an output from the shift register 4. 2nd, 3rd
and 4th bit and 9th bit (least significant bit)
OR gate 7-1 (Figure 3) into which the
and an AND gate 7-2 into which the first bit (most significant bit, or sign bit) output from the shift register and the output from the OR gate are input.
and a sine-bit integral type offset compensation circuit 6 operated by the output of the generation circuit 7, and the first to eighth bits are encoded outputs.

In this embodiment, the encoding of the 1st bit to the 8th bit adopts the A encoding rule having a polygonal companding characteristic, and the sign bit of the 1st bit and the 2nd,
It consists of 3rd and 4th segment bits and 5th to 8th step bits that are linearly encoded within this segment. Furthermore, in encoding the ninth bit, only a comparison is made with the step voltage 1/2 of the segment determined by the input signal at that time.

FIG. 4 shows the relationship between the analog input signal, the logic levels of the first to ninth bits, and the control signal x output from the circuit 7. As is clear from the figure, the control signal x is 1/2 LSB on the positive side with respect to the 4th bit.
(least signifcant bit) is the shifted value. As a result, when the noise is not larger than 1/2LSB, the encoder output will only have the value (10000000),
The above-mentioned no-call noise is reduced.

In this embodiment, a case has been described in which an 8-bit encoded output is obtained, but the present invention can also be applied to a case where an n (positive integer) bit encoded output is obtained.
Furthermore, in this embodiment, we have described the case where 1 extra bit is encoded in order to shift the least significant bit (LBS) of the 8-bit encoded output by 1/2 LSB, but it is also possible to encode 2 or more bits extra. and convert the encoded output LBS to 1/a (a is an integer greater than or equal to 3) LBS
It can also be shifted.

As described above, the present invention includes a mip-riser such as the A encoding rule.
This has the effect of eliminating instability in the output due to noise when a small input signal is input to the encoder.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the input/output characteristics of an encoder using the A encoding rule, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is a control signal used in an embodiment of the present invention. A circuit diagram showing details of the generation circuit and FIG. 4 are diagrams showing relationships among signals in an embodiment of the present invention. In the figure, 1... comparator, 2... array circuit, 3... code circuit, 4... shift register,
5...Control circuit, 6...Offset compensation circuit, 7
... Control signal generation circuit, 7-1 ... OR gate, 7-2 ... AND gate.

Claims (1)

[Claims] 1. Encoding means for converting each sample value of a sampled analog input signal into a digital signal of m (an integer of 2 or more) bits; control signal generating means for directly outputting the most significant bit of the m-bit digital signal or inverting the logic level and outputting it based on the content; and a voltage obtained by integrating the control signal output from the generating means. offset compensating means for negatively feeding back the m-bit digital signal to the encoding means, and the upper n bits (a positive integer less than m) of the m-bit digital signal are used as the encoded output for the sample value. encoder.