JPH0237104B2 - HANDOTAISHUSEKIKAIRO - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to semiconductor integrated circuits, and in particular to insulated gate field effect transistors (referred to as MISFETs).
The present invention relates to a semiconductor integrated circuit in which a differential amplifier circuit is formed.

Conventionally, differential amplifiers using bipolar transistors have mainly been used, but due to recent advances in MISFETs and requirements for their application circuits, differential amplifiers made of MISFETs are being put into practical use. . However, the differential amplifier circuit using MISFET has the problem that the constant current circuit is complicated in order to control the flowing current, and when this circuit is integrated, the required area of the chip becomes large and the stability of the circuit is poor. are doing.

FIG. 1 shows such a conventional differential amplifier circuit.
This shows what uses MISFET. N
Type FET Q ₁ and Q ₂ are each P type as load resistance.
It has FETs Q ₃ and Q ₄ and forms a differential amplification section.
A constant current circuit consisting of N-type FETs _Q5 to _Q8 is provided. Note that 1 and 2 are input terminals, 3 and 4 are output terminals, 5 is a V _DD power supply terminal, and 6 is a V _SS power supply terminal. In other words, this circuit requires a larger area than conventional bipolar transistors, which have a vertical structure and require a small area for the same performance as a constant current circuit, and also requires four MOSFETs to control the flowing current. Since the chip is also used, the chip area becomes large, and the stability of the circuit is also not sufficient due to the fact that it cannot be made large enough to have sufficient capability and there are large manufacturing variations.

It is an object of the present invention to eliminate the above-mentioned problems and to achieve further miniaturization by forming the constant current circuit part using vertical bipolar transistors formed on the same substrate and by changing the connection of the P-type FET as a load resistor. An object of the present invention is to provide a semiconductor integrated circuit in which a differential amplifier circuit with higher stability is formed.

The circuit configuration of the present invention includes first and second one conductive channel MIS formed on the same semiconductor substrate.
a field effect transistor, first and second opposite conductive channel MIS field effect transistors, and first and second vertical bipolar transistors, said first and second one conductive channel;
The sources of the MIS field effect transistors are commonly connected to lead to a first potential, their gates are connected to the first and second input terminals, respectively, and their drains are connected to said first and second oppositely conducting channels MIS electric field, respectively. the drain of the effect transistor and the first and second output terminals, and the source of the first oppositely conductive channel MIS field effect transistor connected to the gate of the first and second oppositely conductive channel MIS field effect transistor; ,
the sources of said first and second opposite conduction channel MIS field effect transistors are connected to the emitters of said first and second vertical bipolar transistors, respectively, and the bases and collectors of said first and second vertical bipolar transistors are connected; are commonly connected to the substrate potential of the semiconductor substrate and lead to a second potential.

The present invention will be described in detail below with reference to the drawings.

Fig. 2 is an equivalent circuit diagram of a differential amplifier according to an embodiment of the present invention, and Fig. 3 is a schematic partial cross-sectional view for explaining the structure, with field oxide films and aluminum electrode wiring etc. omitted. Wiring is also shown in the wiring diagram.

P-type well 1 in N-type silicon semiconductor substrate 10
1 and 12 are formed by, for example, a selective diffusion method. Next, the collector electrode extraction N ⁺ region 13 (also serves as the electrode extraction region of the substrate 10) and the emitter N ⁺ region 15 of the first vertical bipolar transistor _Q15 ,
Drain N ⁺ of the first N-channel MOSFET Q ₁₁
Region 19 and source N ⁺ region 21 are formed, for example, by selective diffusion. Then vertical transistor
Base electrode extraction P ⁺ region 14 of Q ₁₅ , source P ⁺ region 16 and drain P ⁺ region 18 of first P channel type MOSFET Q ₁₃ , first potential point V _SS
The power terminal lead-out P ⁺ region 22 is similarly formed using the selective diffusion method. Next, a gate silicon oxide film 20 of MOSFET Q ₁₁ and a gate silicon oxide film 17 of MOSFET Q ₁₃ are formed. Although not shown, a second vertical bipolar transistor Q ₁₆ is arranged symmetrically in parallel with these at the same time.
Second P-type MOSFET Q ₁₄ and second N-type MOS
Transistor _Q12 is formed. Finally, aluminum evaporation wiring is performed as follows.

That is, as shown in the equivalent circuit diagram of Fig. 2,
The sources of N-channel MOSFETs Q ₁₁ and Q ₁₂ are commonly connected and led to V _SS power supply terminal 6, their gates are connected to input terminals 1 and 2, respectively, and their drains are connected to P-channel MOSFETs Q ₁₃ and Q ₁₄ , respectively.
connected to the drain and output terminals 3 and 4, and P
Channel type MOSFET Q ₁₃ source
Connect to the gates of MOSFET Q ₁₃ and Q ₁₄ ,
The sources of MOSFETs Q ₁₃ and Q ₁₄ are connected to the emitters of vertical bipolar transistors Q _{15 and} Q ₁₆ , and commonly connected to the bases and collectors of vertical bipolar transistors Q ₁₅ and Q 16 (the substrate potential of semiconductor substrate 10 and common) to the second potential V _DD power supply terminal 5.

In this embodiment, MOSFETs Q ₁₁ to _{Q 14} form a differential amplifier section, and vertical bipolar transistors Q ₁₅ and Q ₁₆ form a constant current circuit. Comparing the circuit of this example with the conventional circuit shown in Fig. 1, this example is formed using a vertical bipolar transistor that can obtain the desired current value in the same manufacturing process as the MOSFET, and also uses a vertical bipolar transistor as a load resistor.
Since the resistance value of MOSFET Q ₁₃ is controlled on the MOSFET Q ₁₄ side, the constant current circuit is different from the conventional one.
Since it is formed using only two vertical FETs for four MOSFETs, the required chip area can be significantly reduced to approximately 1/2 of that of conventional devices. Further, since the vertical bipolar transistor has a large capacity and manufacturing variations are small, stability is further improved. Moreover, the constant current circuit is connected to the base and collector of the vertical bipolar transistor in common and is led to the substrate potential.
Since it is connected to the V _DD power supply terminal, as is clear from the above explanation, it can be manufactured in the same process as a conventional MOS integrated circuit without adding any special manufacturing process.

In the above description, a MOSFET was used as the MISFET, but it goes without saying that the present invention is applicable to MISFETs in general. Furthermore, although an N-type semiconductor substrate is used, it is clear that in the case of a P-type semiconductor substrate, the same explanation can be made by replacing N and P in the above explanation.

As explained in detail above, in the semiconductor integrated circuit of the present invention, the constant current circuit portion is formed by vertical bipolar transistors formed on the same substrate, so a smaller and more stable differential amplifier circuit can be realized. It has the effect of being formed.

[Brief explanation of drawings]

Fig. 1 is an equivalent circuit diagram of a conventional differential amplifier, Fig. 2 is an equivalent circuit diagram of an embodiment of the present invention, and Fig. 3 is a schematic partial sectional view of an embodiment. It is. 1...First input terminal, 2...Second input terminal, 3...First output terminal, 4...Second output terminal, 5...V _DD power supply terminal, 6...V _SS power supply terminal,
Q ₁ , Q ₂ , Q ₅ ~ Q ₈ , Q ₁₁ , Q ₁₂ ... N-channel MOSFET, Q ₃ , Q ₄ , Q ₁₃ , Q ₁₄ ... P-channel FET, Q ₁₅ , Q ₁₆ ... Vertical bipolar transistor, 10...N-type silicon semiconductor substrate, 1
1, 12...P-type well, 13...Collector electrode extraction N ⁺ area of _Q15 , 14...Base electrode extraction P ⁺ area of _Q15 , 15...Emitter N ⁺ area of _Q15 , 1
6...Source P ⁺ region of _Q13 , 17...Gate silicon oxide film of _Q13 , 18...Drain P ⁺ region of _Q13 , 19...Drain N ⁺ region of _Q11 , 20...
Gate silicon oxide film of _Q11 , 21...source N ⁺ region of _Q11 , 22... _VSS power supply terminal extraction P ⁺ region.

Claims (1)

[Claims] 1 First and second one conductive channel MIS type field effect transistors and first and second opposite conductive channel MIS formed on the same semiconductor substrate
and first and second vertical bipolar transistors, the sources of the first and second single-channel MIS field-effect transistors are commonly connected to lead to a first potential, and the gate are connected to first and second input terminals, respectively, and their drains are connected to the drains and first and second output terminals of said first and second opposite conducting channel MIS field effect transistors, respectively, and said first opposite conducting channel of
a source of the MIS field effect transistor is connected to a gate of the first and second oppositely conducting channel MIS field effect transistor, and a source of the first and second oppositely conducting channel MIS field effect transistor is connected to the first and second oppositely conducting channel MIS field effect transistor, respectively connecting to the emitter of a second vertical bipolar transistor, and commonly connecting the bases and collectors of the first and second vertical bipolar transistors to a common substrate potential of the semiconductor substrate, leading to a second potential; A semiconductor integrated circuit characterized by: