JPH0236446A - Disk cache memory - Google Patents

Abstract

PURPOSE:To efficiently use a cache memory and to maintain a high cache hit ratio by providing an access frequency detection means. CONSTITUTION:The access frequency detection circuit 3400 counts the number of access times with respect to respective logical volumes in a disk device 4000 in a prescribed time. When access for a logical volume #0 is concentrated, for instance the number of access times exceeds a prescribed number of times, and the difference of the number of access times with a logical volume #2 having least access frequency exceeds reference, a disk cache control circuit 3600 assigns the set (set number 2) of the cache memory 3200 assigned in the volume #2 through a rewrite control circuit 3800 and a set address generation circuit 3500 to the volume #0. Thus, the high speed memory can effectively be used and the cache hit ratio can be maintained without being deteriorated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a disk cache device used in a computer system, and in particular, to a disk cache device used in a computer system.
The present invention relates to a disk cache device that employs an associative method.

Conventional technology In order to reduce processing time for disk devices, a high-speed, small-capacity cache memory is provided between the main storage device and the disk device, and frequently referenced disk data is stored in the cache memory. In disk cache devices that try to shorten disk access time,
In order to improve its performance, it is necessary to increase the probability that accessed data will be found on the cache memory (catch hit rate) and shorten the time to determine whether the data exists on the cache memory. Therefore, it is important to have a mapping method for mapping part of the data in the disk device to the cache memory. Conventionally known mapping methods include the full associative method and the set associative method. The fully associative method allows a disk data block (memory unit) to be mapped to any block in the cache memory.The set associative method allows disk devices to be logically organized into several sets. The cache memory blocks are correspondingly divided into groups called sets, and mapping is performed for each divided group.

Problems to be Solved by the Invention In the conventional mapping method described above, the fully associative method uses all or a large number of blocks in the cache when determining whether or not the data to be accessed exists in the cache memory. I need to find out.

In addition, in the configuration of the set-associative method, it is necessary to check only a limited number of blocks to determine whether the data to be accessed exists in the cache memory, so it can be done in a shorter time than in the fully-associative method. On the other hand, once the correspondence between a disk device and a cache memory set is set, it is fixed, so during computer system operation, depending on the usage situation, access to a specific logically divided area of the disk device may be restricted. When a concentration occurs, data cannot be stored in cache memory other than the set corresponding to that area, so not only can expensive and fast memory not be used effectively, but a small reduced set The memory for this amount may not be enough to store frequently referenced data, leading to a decrease in the cash hit rate.

The present invention was made in order to solve these conventional problems, and it is possible to quickly determine whether or not data to be accessed exists in the cache memory, and to efficiently use the limited cache memory. The object of the present invention is to provide a high-performance disk cache device that can be used extensively and maintain a high cache hit rate.

Means for Solving the Problems A disk cache device according to the present invention includes a cache memory that is divided into a plurality of sets, each of which is divided into a plurality of blocks, and a cache memory that is logically divided into the number of sets. access frequency detection means comprising one or more disk devices divided into the same number of logical volumes, and detecting the number of times a host device requests access to each of the logical volumes per unit time; Each set of the cache memory is allocated one-to-one to each logical volume, a set address for access is generated, and correspondence information between the set and the volume is provided, and based on the detection result of the access frequency detection means. If there is an extreme bias in access to each of the logical volumes, stop allocating the cache memory set to the least frequently accessed logical volume, allocate the set to the most frequently accessed logical volume, and then If the cache memory corresponding to the logical volume can be increased and the access frequency detection means detects that each logical volume is being accessed without extreme bias, the cache memory is increased again. A set address generation means that makes it possible to allocate a set and the logical volume one-to-one, and a data block given from a host device to a storage location in the cache memory specified by the set address generated by the set address generation means. A disk cache device is characterized in that it includes a means for controlling storage of the data.

Effects According to the configuration described above, during computer system operation, if access to each logical volume of the disk device is distributed appropriately, the target data can be stored in the cache memory due to the advantage of the set associative method. Even if access to a specific logical volume is concentrated or decreased, it can be determined in a short time whether or not to
Increase the cache memory set allocated to the logical volume. Alternatively, it is possible to automatically make adjustments, such as stopping allocation of cache memory, to use cache memory effectively, without reducing the cash hit rate.

EXAMPLE An example of the present invention will be described below. In FIG. 1 showing a computer system to which the present invention is applied, 1000 is C
PU (upper unit'), 2000 is main storage, 2100
O8.2110 runs on main memory 2000 is 0
Programs and drivers included in 32100 3000
4000 is a disk cache device, 4000 is a disk device including a disk control device, and the inside is logically divided into multiple volumes, and information about each volume is 0.
It is managed by 82100. 3200 is a cache memory for temporarily storing data on the disk device 4000 included in the disk cache device 300o;
3100 is a cache memory 3200 with a disk device 4
This is a directory in which you can determine which data on 000 is stored. Note that the disk cache device 3000 does not necessarily have to be independent as a device, but can also be incorporated into an input/output channel (input/output interface) or disk control device.

Next, the basic operation will be explained. CPU1000
issues a read request to the disk device 4000 using the driver 2110, the disk cache device 3000 searches the directory 3100 using the address of the read request received from the driver 2110,
The data you are trying to access is in cache memory 3.
Check whether it exists in 200. If the data exists, the data is read therefrom and transferred to the CPU 100O. If the accessed data is stored in the cache memory 3200
If the data does not exist on the disk drive 4000, the data block containing the data is read from the disk device 4000, and this block is stored in an appropriate block of the cache memory 3200.
CPUI 0 at the same time as updating directory 3100
Transfer the data accessed to 00.

Conversely, when the CPU 100O issues a write request to the disk device 4000, the write data is written to the disk device 4000, and if data before the written location of the disk device 4000 exists on the cache memory 3200, Disable that block.

Since the present invention relates to how to allocate the data blocks on the disk device to which part of the cache memory in the above operation, it will be explained in detail using FIG. 2 showing the inside of the disk cache device 3000.

In FIG. 2, 3300 is an address register that stores the address of data specified by a read or write request to disk device 4000, and 3400 is an access request per unit time for each logical volume of disk device 4000. An access frequency detection number 3500 for detecting the number of times is a set address generation circuit 36 that generates a set address based on the address of the data to be accessed and information from the access frequency detection circuit 3400.
00 is a disk cache control circuit that controls the overall operation of the disk cache device, and 3700 is a directory 3.
A comparison circuit 3800 compares the contents of 100 with the contents of the address register 3300, a rewrite processing circuit 3800 performs processing such as replacing a cache memory block with a new data block, and the cache memory 3200 has an input/output bus 3900. It is connected to the disk device 4000 through.

Assuming that the smallest storage unit of a disk device is a sector, and a block is a block that is multiple times the size of the sector, the address of the data to be accessed is volume number 3310. It is decomposed into block address 3320° and sector address 3330.

The cache memory 3200 is a memory that can be addressed in sector units and is divided into sets consisting of a plurality of blocks.If the collection of blocks in the same order in each set is taken as a level, then the sectors in the cache memory can be addressed by a set address. , level address, and sector address within the block.

The directory 3100 is a memory having entries corresponding to blocks in the cache memory 3200, and has a set level arrangement similar to the cache memory 3200, and each entry has a list of disk devices stored in the corresponding block of the cache memory 3200. Addresses (volume numbers, block addresses) of 4000 data blocks are stored.

The access frequency detection circuit 3400 reads the volume number from the address register 3300 every time reading or writing to the disk device 4000 is requested during a predetermined period of time, counts the number of access circuits for each logical volume, and sends the result to the disk cache control circuit 3600. send to After a predetermined time has elapsed, each count value is reset once and counting begins anew.

The set address generation circuit 3500 has an internal volume/set correspondence table 3510, and
The logical volume number 3310 of 000 is input, the volume set correspondence table 3510 is referred to, and a set address is generated. Normally, the cache memory 3200 and each logical volume of the disk device 4000 are in a one-to-one correspondence (however, based on the information of the access frequency detection circuit 3400, the volume set correspondence table 3510
We also make changes to the contents of .

Next, referring to FIGS. 1 and 2, the operation of an embodiment of the present invention will be described. When there is a read request from the CPU 100O, the driver 2110 stores the address of the data of the specified disk device 4000 in the address register 330.
Store at 0. The set address generation circuit 3500 generates a set address based on the contents of the address register 3300, and the directory 3 according to the generated set address.
One set within 100 is selected. Comparison circuit 370
0 compares the contents of the directory entries in the set with the contents of the address register 3300 one by one in level order. This comparison operation is performed only within the selected set, so it can be processed in a short time. If the comparison matches at a certain level, the cache memory 3 corresponding to this entry
The sector to be accessed is stored in block 200, and the set address is stored in the set address generation circuit 3.
500 and the matching level address are transmitted to the cache memory 3200 by the comparison circuit, and the block is designated. and address register 33
A sector in the block is selected by the sector address 3330 in 00, and the data is sent to the CPU 100O.

If the comparison does not match at all levels of the set, then
By the rewriting processing circuit 3800, the cache memory 32
Extract an empty block from 00. If there are no free blocks, a known algorithm, e.g.
Like U (Least Recently Used), among the blocks in use, the block that was last referenced the oldest is considered to be least frequently used, and is selected as a replacement block. Then, the address of the data block to be accessed is written in the entry of the directory 3100 corresponding to that block. Next, the rewrite processing circuit 3800 reads the block at the address indicated in the address register 3300 from the disk device 4000 into the selected block of the cache memory 3200, and at the same time, among the sectors in the block,
Data in the sector specified by sector address 3330 is sent to CPU 1000.

Following the basic operation of the set-associative type disk cache device, we will next explain the functions of the access frequency detection circuit 3400 and set address generation circuit 3500, which are the features of the present invention, with reference to FIGS. 1 and 2 and the cache memory. An example of allocating n sets of data to n logical volumes of a disk device will be explained using FIG. 3.

At the beginning of computer system operation, assuming that accesses to each logical volume of the disk device 4000 are distributed approximately evenly, one set of cache memory is set for each logical volume as shown in FIG. 3(a). However, during the operation of the computer system, the access frequency detection circuit 3400 determines that the
The number of access circuits to each logical volume in the disk device 4000 for each minute) is counted, and the information is sent to the disk cache control device 3600. Here, if accesses to the logical volume, volume #0, are concentrated, and the number of accesses exceeds a predetermined number of times, and the logical volume, volume #2, which has the lowest access frequency,
If the difference between the number of accesses and the number of accesses exceeds the standard, the disk
The cache control circuit 3600 is a rewrite control circuit 380
0 to invalidate all block data of the cache memory set (set number 2) corresponding to volume #2 and the directory entry corresponding to the block. At the same time, the disk cache control circuit 360
0 indicates the volume/volume in the set address generation circuit 3500.
An instruction is given to change the volume number entry corresponding to set number 2 in the set correspondence table 3510 from 2 to 0.

As a result of the above operations, as shown in FIG. 3(b), the cache memory set (set number 2) that was allocated to volume #2 is now allocated to volume #0. Therefore, when there is an access request to volume #0, the end J of the set with set number O in the directory is searched, and if there is no entry that matches the contents of the address register, then the end J of the set with set number O in the directory is searched. You will be searching for an entry. Note that the reference value of the access circuit to each logical volume per unit time to determine whether bias has occurred in access to the logical volume depends on the number of logical volumes, the capacity of the cache memory, the configuration of the calculation system, etc. The maximum value can be set freely.

Furthermore, when an access request occurs to volume #2, the cache memory is not allocated to volume #2, so the directory is not searched.
Although the disk device is directly accessed, during computer system operation, access to each logical volume is distributed, access to volume #0 decreases, access to volume #2 increases, and the access frequency detection circuit 340
From the detection result of 0, either the difference in the number of accesses per unit time to volume #O and volume #2 is within the reference value, or the number of accesses to volume #O per unit time.

When the number of accesses for the previous volume falls within the standard value, the cache memory set (set number 2 or O) that was allocated to volume #O is allocated to volume #2 again with the same effect as described above, and the ¥% Figure 3 (a)
becomes the state of However, the number of accesses per unit time to volume #0 still exceeds the standard value, and the difference in the number of accesses per unit time to volume #0 and volume #2 is within the standard value, but the access frequency to volume #1 exceeds the standard value. Assuming that the difference in the number of accesses per unit time with volume #O exceeds the reference value, the set of cache memory allocated to volume #1 (set number 1) will be However, as shown in Figure 3(e), volume #2
If the difference in the number of accesses per unit time between volumes 31 and 32 and volume #07 exceeds the standard value, a set of cache memory will be allocated as shown in Figure 3(d). It will be done.

By repeating the above operations during computer system operation, the limited cache memory can be used effectively and efficiently.

Although the above embodiment has been described assuming that one disk is connected with sectors as recording units, the present invention can also be applied to disk devices other than the sector system.
A configuration in which not only one unit but also multiple units are connected is also possible.

Effects of the Invention As explained above, the present invention employs a set associative method in which blocks in a disk device and cache memory are divided into sets and mapping is performed within the same set, so that accessed data blocks are stored in the cache memory. It can be easily and quickly determined whether or not a disk exists on a disk, and it can also be used when accesses are concentrated or reduced to a specific disk device or a specific area of a disk device during computer system operation, or when there is a failure. Even if a situation arises where this is not possible, by automatically adjusting the set of cache memory allocated to that disk device area, the limited amount of expensive, high-speed memory can be used effectively and the cache hit rate can be reduced. It has an effect that can be maintained without any problems.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a computer system to which the present invention is applied;
FIG. 2 is a block diagram showing a configuration example of a disk cache device according to the present invention, and FIG. 3 is an explanatory diagram illustrating the operation of allocating a set of cache memories to a disk device. 1000...CPU, 2000...Main storage device, 3000...Disk cache device, 3100...Directory, 3200...
... Cache memory, 4000 ... Disk device, 3300 ... Address register,
3400...Access frequency detection circuit, 3500
...Set address generation circuit, 3600...
...Disk cache control circuit, 3700...
... Comparison circuit, 3800 ... Rewriting processing circuit,
3900...Input/output bus. Name of agent: Patent attorney Shigetaka Awano and one other person Figure 1 Figure 3 (α) Kazushi Susumori Figure (b) + Ko Tsunyu Memozo Figure (C No Kyadushi Shimozo Figure (d)) Cache Memory Separation/μ Number chant 'duyum・'t! zutokari left kale

Claims (1)

[Claims] The whole is divided into a plurality of sets, each set is divided into a plurality of blocks, and a cache memory is provided, and one or more disk devices are logically divided into the same number of logical volumes as the number of sets, access frequency detection means for detecting the number of times access is requested per unit time to each of the logical volumes; It generates a set address and has correspondence information between the set and the volume, and if an extreme bias in accesses to each logical volume is found from the detection result of the access frequency detection means, the most It is possible to stop allocating a set of cache memory to a low logical volume, allocate the set to the most frequently accessed logical volume, increase the cache memory corresponding to the logical volume, and a set address generating means that makes it possible to once again allocate the cache memory set and the logical volume on a one-to-one basis when the access frequency detecting means detects that accesses are being performed without any bias; A disk cache device comprising: means for controlling a data block requested for access to be stored in a storage location of the cache memory designated by a set address generated by a set address generating means.