JPH0235873A - Video signal a/d converter - Google Patents

Abstract

PURPOSE:To display a highly contrastive picture by detecting the level of a video signal in real time, and changing the level of an A-D conversion for the video signal according to the level so as to trace the change of the detection level with a delay for a prescribed time. CONSTITUTION:A video signal (a) is integrated by an integrating circuit 21, amplified by an OP amplifier 22, and made into a signal (b). That is, the signal (b) changes according to the change of the mean value of the video signal (a). Reference potentials VH and VL outputted from a reference potential generating circuit 11 change according to the output (b) of the OP amplifier 22. Comparators 121-12n extract the video signals outputted from a video signal amplifying circuit 1 corresponding to the reference potentials VH and VL, and converts them through a decoder 13 into data at four bits. Consequently, the A-D conversion is always executed for the vicinity of the mean value of the video signals. Thus, an A-D converter at low level resolution can execute the A-D conversion at high level resolution, and the highly contrastive picture can be displayed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a video signal AD converter that converts a television video signal into a digital signal.

[Conventional technology and issues to be solved]

In recent years, a liquid crystal television receiver that uses a liquid crystal display panel instead of a cathode ray tube has been developed as a small portable television receiver, and has already been put into practical use.

When displaying a television image using a liquid crystal display panel, it is currently considered that the appropriate number of gradations is 16 gradations based on the capabilities of the liquid crystal display element. Above 160 gradations can be produced by a 4-bit A/D converter. Therefore, in order to faithfully A/D convert a video signal, it is necessary to perform A/D conversion from the white level to the black level of the video signal, and the resolution thereof needs to be 7 bits or more.

The A-D converter is constructed using four converters; for example, there are 15 converters for 4-bit output, 31 for 5-bit output, and 63 for 6-bit output. If a large number of comparators are required and one resolution is improved, the configuration becomes complicated and very expensive. Furthermore, since the video signal does not always change from the white level to the black level, the contrast is poor if the entire range of the video signal is A-D converted.

The present invention has been made in view of the above points, and by changing the level of A-D conversion according to the level of the video signal, an A-D converter with a low level resolution is used to convert an A-D converter with a high level resolution into an A-D converter. It is an object of the present invention to provide a video signal A-D conversion device capable of performing D conversion and displaying an image with good contrast.

[Means and effects for solving the problem] That is, the present invention detects the level of a video signal in real time, and adjusts the level of A-D conversion for the video signal according to the detected level.
By changing the detection level so as to follow the change with a predetermined time delay, it is possible to display an image with good contrast even when using a bA-D conopter with a low level resolution. .

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows the configuration of the main parts of a liquid crystal television receiver. In the figure, 1 is a video amplification circuit, which amplifies the signal from a video detection circuit (not shown), and a synchronous separation circuit 2.
and output to the A-D converter 3. Further, a part of the output signal of the video amplification circuit 1 is sent to an audio amplification circuit (not shown).

The synchronization separation circuit 2 separates horizontal and vertical synchronization signals from the input video signal and outputs them to the control circuit 4. This control circuit 4 provides a drive timing signal to the first drive circuit 6 via the shift register 5, and also provides a timing signal to the i2 drive circuit 7. The first drive circuit 6 is
The liquid crystal display panel 8 is scanned in the vertical direction, and the second drive circuit 7 is scanned in the horizontal direction of the liquid crystal display panel 8. Further, the control circuit 4 generates a chip enable signal CE for selecting a video signal every other horizontal scan, and supplies it to the A/D converter 3. This A/D converter 3 includes a reference potential generation circuit 11. Kon Zoreta 121-12
n, decoder 13. It is mainly composed of a bias circuit 14. As will be described in detail later, the reference potential generation circuit 1 generates a low level reference potential VL and a high level reference potential VH in accordance with the white level voltage and black level voltage of the video signal. V, , Vyo are applied to the comparator 12. directly or after being divided by resistors R1 to Rrr1. ~12n reference terminal. The comparison terminals of the comparators 121 to 12n are supplied with the output signal of the video amplification circuit 1. On the other hand, the bias circuit 14 operates in synchronization with the chip enable signal CE.
Bias is applied to the comparators 121 to 12n. The comparators 121 to 12n are biased by the bias circuit 14 and operate in an open state, and input their output signals to the decoder 13. This decoder 13 decodes the input signal into, for example, a 4-bit digital signal and sends it to the shift register 9 as an output of the AD converter 3. This shift register 9 has a liquid crystal display panel 8 of 120×, for example.
For 160 dot double matrix, 4 bits x 320
It is composed of tiers. The data input to the shift register 9 is then passed through the buffer 710 to the second drive circuit.
sent to. The second drive circuit 7 modulates the brightness of the output of the buffer 1θ based on the brightness/luminus from the control circuit 4, and applies a drive bias to the liquid crystal display panel 8.

Next, details of the reference potential generation circuit 11 will be explained with reference to FIG. The video signal sent from the video amplification circuit 1 is inputted to the 10 input terminal of the OP amplifier f22 via the integration circuit 21. This OP amplifier 22 is used as a buffer of a voltage follower, and its output is inputted to one input terminal of itself and also inputted to one input terminal of an OP amplifier 24 via a resistor 23. A DC voltage of 1/2 voc is applied to the ten input terminals of the op amplifier 24. The output of the OP amplifier 24 is input to one input terminal of the OP amplifier 24 via a resistor 25. Above OP
The amplifier 24 is used as a DC inverting amplifier, and its output is input to one input terminal of an OP amplifier 27 via a resistor 26 and to one input terminal of an OP amplifier 29 via a resistor 28. . Further, a voltage of 1/2 Vc is applied to the input terminal of the OP amplifier 27°29. Furthermore, the voltage of vcc is divided by a series circuit of a resistor 3o, a variable resistor 31, and a resistor 32,
The divided voltage between the resistor 30 and the variable resistor 31 is OP an f
29 is supplied to one input terminal of variable resistor 3 and resistor 32.
A divided voltage between is supplied to one input terminal of the OP amplifier 27. Further, the outputs of the OP amplifiers f27 and 29 are inputted to one input terminal of the OP amplifiers through resistors 3:l and 34, respectively. Then, the output of the OP amplifier 27 is taken out as the reference potential vH, and the output of the OP amplifier 29 is taken out as the reference potential v.

Next, the operation of the above embodiment will be explained with reference to the signal waveforms of each part shown in FIG. From the video amplification circuit 1, the third
A video signal a as shown in FIG. fl) is output and input to the A/D converter 3. The video signal a is first integrated by the integrating circuit 2, and then amplified by the OP amplifier 22 to produce a signal as shown in FIG. 3(b). That is,
This signal is.

It changes following the change in the average value of the video signal a.

The signal S is then inverted and amplified by the OP amplifier 24, resulting in a signal waveform shown in tc+ in FIG. That is, OP
The output signal C of the Ang 24 is given 1/2 Vcc as the reference voltage of the OP Ang 24, so c = (1/2 Vce-b) + 1/2 Vc
c=voc-b. The output C of the above OP amplifier f24 is
7, it is inverted and amplified to become the signal shown in FIG. 3 (,), that is, the reference potential vH. At this time, the voltage of 1/2 vCc is input to the child terminal of the OP amplifier 27, and the divided voltage d between the variable resistor 3 and the resistor 32 is applied to the terminal, so the OP amplifier 27 The output e is: e=vH=(1/2vcc-c)+(1/2vcc-d
)+1/2voc=3/2vcc-c-d=3/2 Voc-(Vcc-b)-d=1/2
Vcc + bd. The above-mentioned divided voltage d is set to a much lower value, for example, 5 K 1/2 Vc as shown in Fig. 3 (di), so the reference potential vH becomes a high level.
The output of the amplifier 24 is inverted and amplified by the OP amplifier f29 to become a signal g, that is, a reference potential vL, shown in FIG. 3(g).

At this time, the voltage of 1/2vCC is input to the child terminal of the OP amplifier 7629, and the divided voltage between the resistor 30 and the variable resistor 31 is given to one terminal, so the OP amplifier 29
The output g is: g=VL=(1/2 Vcc-C) +(1/2 Vc
c-f) +1/2 v,.

= 3/2 V,. -c-f ” 3/2”cc (vCCb) f= 1/2
v,, + b −t. The divided voltage f is set to a value higher than 1/2 voc, for example, as shown in FIG. 3 (fl).

The reference potential vL becomes low level. Note that 1 partial voltage d,
Since f changes by adjusting the variable resistor 3), the level of the reference potential 8vL can be adjusted by operating the variable resistor 3). Also, the reference potential vH-vL is
As is clear from the above calculation formula, it changes depending on the output of the OP angle 22.

That is, the reference potential V□·vL changes following the change in the average value of the video signal.

The reference potential (18.vL) outputted from the reference potential generation circuit 11 is inputted as a reference voltage to the comparators 121-12 either directly or after being divided by the resistors R1-Rm. The above comparator 12. ~12n is
The video signal output from the video amplifier circuit 1 is set to a reference potential vH.
-vLVc therefore removed.

The data is converted into 4-bit data via the decoder 13. Therefore, A-D conversion is always performed for the vicinity of the average value of the video signal. In other words, when the image is dark, the average value of the video signal is low, so the reference potential V,·vL is low, and
When the image is whitish, the average value of the video signal is high, so the reference potential becomes high, and AD conversion is performed around the average value of the video signal.

The 4-bit data that has been A-D converted by the A-D converter 3 is written to the shift register 9 and then transferred to the buffer 1.
0 to the second drive circuit 7, and the liquid crystal display panel 8
Displayed in .

Therefore, rather than the entire range of the video signal, a predetermined range around the average value of the video signal with gradual changes is A-converted, so an A-D converter with a low level resolution is used to convert the level resolution. High A-D conversion can be performed and images with good contrast can be displayed. Furthermore, since an A-D converter with low level resolution can be used, the number of comparators used can be reduced, the configuration can be simplified, and costs can be reduced.

In addition, the relative change in the level of the video signal and the reference potential for A-D conversion is determined by the integration circuit 2 with respect to the level change in the video signal.
Since the contrast is tracked with a delay time determined by a time constant of 1, the brightness of one part of the screen does not affect other parts, and the contrast can be controlled according to changes in the brightness of the entire screen.

〔Effect of the invention〕

As described above, according to the present invention, the level of a video signal is detected in real time, and the level of A-D conversion for the video signal is determined according to the detected level.

By changing the detection level so as to follow the change with a predetermined time delay, an image with good contrast can be displayed even if an A-D converter with low level resolution is used.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention, and FIG. 1 is a circuit configuration diagram, and FIG. 2 is a circuit diagram showing details of a reference potential generation circuit in the A-D converter in FIG. 1. 3(a) to 3(g) are operation signal waveform diagrams of each part in FIG. 2. 3...A-D converter, 11...-Reference potential generation circuit, 121-12n...Comparator, 13...Decoder, 14...Bias circuit, 21...Integrator circuit,
22゜24.27.29...op amp.

Claims (1)

[Claims] An A-D conversion device for converting a video signal into a digital signal, comprising: means for detecting the level of the video signal in real time; and A-D conversion of the video signal according to the level detected by the means. an A/D converter comprising means for changing the level of the detection level so as to follow the change in the detection level with a delay of a predetermined time.