JPH0235696A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To realize a high voltage detecting operation with high reliability by controlling the validity/invalidity of the operation of a high voltage detection circuit by the output of a decoder circuit which decodes the levels of plural input signals supplied to another external terminal at the time of supplying a high voltage from a specific external terminal. CONSTITUTION:The validity/invalidity of the operation of the high voltage detection circuit VH which receives the high voltage over a source voltage supplied from the specific external terminal A9 is controlled by the output of the decoder circuit XADB.DCR to decode the levels of the plural input signals supplied from another external terminals A and X at the time of supplying the high voltage from the specific external terminal A9. Thereby, since it is possible to nullify the operation of the high voltage detection circuit by the output of the decoder circuit XADB.DCR which receives the level of another input signal even when overshoot assumed as the high voltage is generated at the specific external terminal A9, the high voltage detecting operation with high reliability can be realized.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and for example, an EPROM (erasable & Programmers Concerning effective technology for use in blue-read-only memory.

[Conventional technology]

In EPROM, in order to set the silicon signature read mode, a specific address terminal is set as a ternary level input and set to a voltage higher than the power supply voltage, and when a high voltage input is detected, data such as the product code and write conditions are automatically read. There is something that I am trying to output. Silicon signature like this
For example, see page 265 of ``Microcomputer Handbook'' published by Ohmsha on December 25, 1985.

[Problem to be solved by the invention]

The above-mentioned high voltage detection circuit may malfunction in that it may determine that it is an overshoot 'cK voltage that occurs when the input signal supplied to its input terminal changes from a normal low level to a high level. When the high voltage detection circuit malfunctions as described above, the EPROM enters the silicon signature read mode even though it is in the normal read mode, and data such as the write conditions are erroneously output.

An object of the present invention is to provide a semiconductor integrated circuit device having a high voltage detection circuit with improved operational reliability.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Means for Solving Problem C] A brief summary of typical inventions disclosed in this application is as follows.

In other words, the operation of the high voltage detection circuit that receives a high voltage higher than the power supply voltage supplied from a specific external terminal is enabled/disabled when the high voltage is supplied from another external terminal when the high voltage is supplied from the specific external terminal. control by the output of a decoder circuit that decodes multiple input signal levels.

(Function) According to the above-described means, even if an overshoot that is considered to be a high voltage occurs at a specific external terminal, its operation is nullified by the output of the decoder circuit that receives the level of other input signals. Therefore, a highly reliable high voltage detection operation can be realized.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of an EPROM device to which the present invention is applied. Each circuit element in the same figure is
It is formed using known integrated circuit manufacturing techniques on a semiconductor substrate, such as, but not limited to, a single crystal silicon substrate.

Although the EPROM device of this embodiment is not particularly limited,
It has eight data input/output terminals, allowing writing and reading of 8-bit data. EPROM devices require a power supply voltage such as +5 volts and a high level write voltage Vpl such as tens of volts.
) and operated by. EPROM devices are operated with a power supply voltage Vcc, such as +5V, during normal read operations. The EPROM device receives an external address signal supplied through an address input terminal, and a control terminal C.
Its operation is controlled by a chip enable signal, an output enable signal, and a program signal supplied via E, ○E, and PGM.

In this embodiment, in order to write/read data in an 8-bit configuration as described above, eight sets of memory arrays M-
ARY (X8) and data input cover sofa DIB (X8)
and a data output cover sofa DOB (X8).

In the figure, one of the memory arrays M-ARY, a data input circuit DrB, and a data output circuit DOB are exemplarily shown.

The memory array M-ARY consists of a plurality of stacked gate transistors (non-volatile memory elements...MOS) each having a control gate and a floating gate.
FETQ1 to Q6), word lines Wl, W2 and data HD1. It is composed of D2 to Dn. In the memory array M-ARY, the stacked gate transistors Q1 to Q3 (Q
4 to Q6) control gates respectively correspond to the corresponding word vAW1. FAMOS) transistor Q1. connected to W2 and placed in the same column. Q4, Q2. Q5 and Q3. The drain of Q6 is connected to the corresponding data line D.
1, connected to D2 to Dn.

The common source line C8 of the stacked gate transistor (memory cell) is grounded via a depletion MOSFET QIO that receives the write signal we, although not particularly limited thereto. This MOSFETQIO is
This is established for the following reasons.

That is, when writing data to a memory cell, for example, memory cell Q1, a high voltage at the write level is applied to the word line Wl, and a high voltage according to the data to be written or a low voltage of rOV is applied to the data wADl. . In this case, the floating gate of a memory cell such as the memory cell Q2 that is to be unselected and is coupled to the selected data line DI is connected to the data line D1 at a high potential due to the capacitive coupling that occurs between it and the data IDI. When it is done,
The potential is accordingly increased undesirably.

As a result, memory cells such as memory cell Q2, which should be maintained in an off state by being unselected, undesirably pass through R. In other words, leakage current flows into memory cells that should be unselected. Correspondingly, the write current that should flow through the selected memory cell Ql is reduced.

The conductance of the illustrated MO5FET QIO is made relatively small by the low level of the internal control signal we during writing. As a result, the potential of the common source line CS caused by the write current flowing during writing is made relatively high by making the conductance of the MOS FETQ 1O relatively small.

When the potential of this common source line C8 is made relatively high, the threshold voltage of the stand gate transistor is made relatively high due to the substrate effect.

In this way, as a result of increasing the effective threshold voltage of the stacked gate transistor to be unselected, the leakage current flowing through the stacked gate transistor to be unselected can be reduced. As a result, the write current generated by the high write voltage is efficiently supplied to the selected stacked gate transistor, so that an efficient write operation can be performed. Note that during the read operation, the conductance of MOSFET QIO is made relatively large due to the high level of the control signal we. This makes it possible to increase the current flowing through the stacked gate transistor for logic "1" writing, which is set to a low threshold voltage by not injecting charge into the floating gate, thereby increasing the read speed.

The EPROM device of this embodiment includes address buffers XADB and YADB that receive X and Y address signals AX and AY supplied via external terminals (not shown). Complementary address signals formed by address buffers XADB and YADB are sent to address decoders XDCR and YDC.
Supplied to R.

In the figure, the X address buffer XADB and
Circuit block XA with address decoder XDCR
DB-DCR, and the above X address buffer Y
ADB and the Y address decoder YDCR are collectively shown as a circuit block YADB-DCR.

Although not particularly limited, the address buffers XADB and YADB are activated by the chip selection signal ce generated by the control circuit C0NT, take in address signals from external terminals, and combine them with the address signals supplied from the external terminals. A complementary address signal consisting of an internal address signal of the same phase and an address signal of opposite phase is formed.

The X address decoder XDCR selects the memory array memory array M-A according to the complementary address signal supplied thereto.
RY (same for other memory arrays not shown)
form a selection signal to be supplied to the word line of the word line. Although the X address decoder XDCR is not particularly limited, +5
It is operated with a power supply voltage of v. Therefore, the address decoder XDCR forms a 5-volt selection signal.

On the other hand, the level of the selection signal required by the memory array M-ARY is, for example, a high level of Y' 5 V in a read operation and a low level of S'OV in a write operation. The high level of the write voltage Vl)P level is the low level of VOV. In order to make the word lines of the memory array M-ARY reach the required levels in response to the 5-system selection signals output from the X address decoder XDCR, the output terminals of the X address decoder XDCR and each memory array A dip fusion type MOSFE is connected between the word line and the word line.
TQII to Q12 are provided, and a write high voltage load circuit XR is provided between each word line and the write voltage terminal Vl)+1. Although the details of the write high voltage load circuit XR are not shown, the terminal Vpf
1 and each word line, each consisting of a high resistance polysilicon layer.

The gates of the dabre-notion type MOSFETs QI1 to Q12 are supplied with a 5-system internal write control signal we output from the control circuit C0NT.

In the case of a read operation, the internal write control signal we is set to a high level of \゛5■. In this case, MOSFETQ
All of I1 to Q12 are X address decoder
It is turned on in response to a 5V selection signal output from the DCR. Therefore, the output of the X address decoder XDCR is directly transmitted to each word line.

In the case of a write operation, the internal write control signal W1 is set to a low level of so00. In this case, for example, among the signals output from the X address decoder XDCR, the signal corresponding to the word line Wl is !゛5V high level (
(select level), MOSFET QI 1 is automatically turned off because the voltage applied to its gate is brought to a negative level relative to the voltage applied to its source.

In response, the word line W1 is set to the high level of the write voltage Vl)p by the high voltage load circuit XR. On the other hand, for example, whether the signal corresponds to the word line W2 of the X address decoder XDCR is y' o
If vO is at low level, MOSFET Q12 is kept on. Therefore, the word line W2 is set to the low level of x' ov by the address decoder XDCR.

In FIG. 1, common data IcD is provided for memory array M-ARY. Memory array M-A
MOSFETs Q7 to Q9 forming a column switch circuit are provided between the RY data line and the common data line CD corresponding to the memory array.

Y address decoder YDCR forms a selection signal for selecting a data line of memory arrays M to ARY according to a complementary address signal supplied thereto. The Y address decoder YDCR is operated by a 5V power supply voltage similarly to the X address decoder XDCR. The selection signal output from the Y address decoder YDCR is used to control the column switch circuit jH. Here, the column switch circuit is required to have the ability to transmit a write signal at a write voltage level in a write operation. In order to turn on and off the column switch MOSFET, the Y address decoder YDCR is
Depletion type MOSFETs Q13 to Q15 are arranged between the output terminal of the column switch MOS FET and the gate of the column switch MOS FET, that is, the column selection line. The internal write control signal we is supplied to the gates of these MOSFETs Q13 to Q15, similarly to the MOSFETs QI1 to Q12. each of the column selection lines and, although not limited to, the high voltage terminal Vpl)
A write high voltage load circuit YR is provided between the two.

The common data line CD is coupled to an output terminal of a data input circuit DIB that receives a write signal input from an external terminal I10. The output circuit in the data input circuit DrB is a write MOS F controlled by a write signal level-converted to the level of a high voltage Vl)p.
A write voltage vpp is sent out via ET. This output circuit is configured such that its output impedance is in a high impedance state when the write pulse we is at a high level (read operation) as shown in FIG.

The input terminal of the data output circuit DOB is the common data line CD
is combined with The data output circuit DOB is comprised of a sense amplifier and an output buffer that receives its output. Although the sense amplifier is not particularly limited, the common data line CD
It has a bias circuit to supply bias current to.

The bias circuit outputs a bias current in its operating state.

The bias circuit is provided with appropriate level detection functionality. As a result, a bias current is formed when the input level of the data output circuit D0B is below a predetermined potential, and when the input level reaches the predetermined potential, the bias current becomes substantially zero.
be made to become.

The selected memory cell has a high threshold voltage (logic "0") or a low threshold voltage (logic "1") with respect to the word line selection level during reading according to the data written therein in advance. .

If the selected memory cell in the memory array M-ARY has a high threshold voltage, no direct current path is formed between the common data line CD and the circuit ground. In this case, the common data line CD is brought to a relatively high level by current supply from the sense amplifier. The supply of bias current from the bias circuit in the sense amplifier is substantially stopped when the common data kW CD reaches a predetermined potential. Therefore, the high level of the common data line is limited to a relatively low potential.

On the other hand, if the selected memory cell in the memory array M-ARY has a low threshold voltage, the column switch M
OSFET, data line, selected memory cell and MO
A direct current path is formed through the 5FET QIO. Therefore, the common data line CD is brought to a low level regardless of the bias current supplied from the bias circuit.

Limiting the amplitude of the high level and low level of the common data line CD by such a bias circuit brings about the following advantages. That is, even if there is a capacitance such as a stray capacitance that limits the signal change speed in the common data line CD, etc., it is possible to increase the speed of reading. In other words, when reading data from a plurality of memory cells one after another, the time required for one level of the common data line CD to change to the other level can be shortened.

The output sofa in the data output circuit DOB is configured such that its operation is controlled by the read control signal oe. The output buffer has a control signal OE of 1'5V.
If the signal is at a high level such as , a data signal of a level corresponding to the signal supplied from the sense amplifier is output to the external terminal T/○. On the other hand, the output sofa uses the control signal oe
If the voltage is at the low level of SOOV, a high output impedance state is established. This prevents the output buffer from limiting the level of the write data signal supplied to the data input/output terminal I10 during a write operation.

The control circuit C0NT is activated by the power supply voltage Vcc and receives a write high voltage Vρρ supplied from an external terminal.
, chip enable signal CE, output enable signal OE
and generates various control signals according to the program signal PGM.

In this embodiment, a memory array MARY is used, although not particularly limited, to provide a silicon signature function. That is, as shown by the dotted line in the figure, the word line W
Using the memory cells Ql' to Q3' coupled to O, conditions for an automatic write operation such as a silicon signature are set. For this reason, if a stacked gate transistor is used as the memory cell connected to the word line WO as shown in the figure, it is necessary to provide a light-shielding mask or the like to the portion shown by the dotted line to make it non-erasable. , or the memory cell is configured with a mask ROM.

In other words, the transistors Ql' to Q3' are replaced with stacked gate transistors by controlling the thickness of the gate insulating film, selectively connecting to the word line or data line, etc., so that the word line WO can be selected. The level is substantially turned on or off. EPRO with a l-time program configuration whose erasing function is disabled by using a package without an erasing window, etc.
In M, the stacked gate transistor of the word line WO can be used as is.

In the configuration using the memory array M-ARY as described above, it is possible to store data consisting of a relatively large number of bits corresponding to one word line, so it is possible to store data consisting of a relatively large number of bits corresponding to one word line, so it is possible to store data such as quality control such as product loft number etc. Various useful information can also be stored. Note that the silicon signature may have a configuration in which a ROM is provided at the input section of the data output circuit DOB instead of the configuration using the memory array M-ARY as described above.

The selection of the word line WO is performed by the high voltage detection circuit (2)H. The high voltage detection circuit VH detects a high voltage such as about 10V supplied to the address terminal A9, although this is not particularly limited. In this embodiment, in order to increase the reliability of the operation of the high voltage detection circuit VH (in other words, in order to prevent malfunctions in which overshoot at address terminal A9 is regarded as high voltage), other address The signal is utilized, i.e. the high voltage detection circuit V H
As will be described later, its operation is controlled by an output signal from a decoder circuit that receives other address signals.

FIG. 2 shows a circuit diagram of an embodiment of the high voltage detection circuit and a decoder circuit for controlling its operation.

In the silicon signature read mode, all address signals AO to Ai other than the address terminal A9 are set to low level. And data output diagram! In order to operate DOB, the output enable signal OE must be at low level, and the chip enable signal C
B is a low level. Focusing on this, the other conditions mentioned above are set as the operating conditions of the high voltage detection circuit VH. That is, address buffer ADB corresponding to address terminal A9 for high voltage supply, and other address buffers ADB except 9.
The inverted output signals aO to Ai of O to ADB i and the non-inverted output signals ce and oe of the control input buffers CEB and OEB are supplied to a NAND gate circuit G. As a result, when all the input signals of the Nant gate circuit Gl are at a high level (logic "1"), in other words, when the control signals CE and OE are at a low level, the address signal A
When O to At (excluding address signal A9) are at low level, the output signal of Nant gate circuit G1 is set to low level.

The output signal of the Nant gate circuit G1 is supplied to the gate of a P-channel type switch MO5FETQI6. This switch MOSFET QI6 transmits the voltage at the address terminal A9 to a voltage dividing circuit made up of N-channel MOSFETs QI7 and Q18. That is, the N-channel MOSFET Q17 is an enhancement type, and its gate and drain are coupled, so that
It acts as a type of variable resistance element. MOSFET
Q18 is of a dip reflex type, and acts as a constant current load by applying a ground potential to its gate and source. The MOSFETs QI7 and Q18 act as a voltage dividing circuit that receives the voltage at the terminal A9. Above M
The conductance ratio of OSFET QI7 and Q18 is such that when the voltage at terminal A9 is at a high level such as approximately 5V, the divided voltage becomes lower than the logic threshold voltage of inverter circuit N1, and the voltage at terminal A9 is approximately 10V. The divided voltage is set so as to be higher than the logic threshold voltage of the inverter circuit Nl when the voltage is increased. In addition, P channel MO as a power switch
The conductance of SFETQI6 when it is turned on is set to be sufficiently larger than that of MOSFETQ17, so that the divided voltage is equal to that of MOSFETQ17.
It is set only by the conductance ratio of Q17 and Q18.

The output signal NS of the inverter circuit N1 is supplied to the X address decoder circuit XDCR which receives the X address signal at a low level, and forcibly invalidates the selection operation thereof.

The inverter circuit N2 receiving the output signal of the inverter circuit N1 forms a selection signal for the word line WO. As a result, when the output signal of the Nant gate circuit G1 is at a low level, that is, all address signals AO to At except for the address signal A9 are at a low level.
When the control signals CE and OE are at low level, if the voltage of terminal A9 is set to a high voltage such as about 10V, the word line WO is selected instead of the word line WO used for normal writing/reading, and the silicon The signature information is automatically read out and output from the data output circuit DOB.

In this configuration, even if an overshoot occurs in the address signal A9 that is considered to be a high voltage in the high voltage detection circuit VH, other address signals AO to
If any one of Ai is at high level, the output signal of Nant gate circuit G1 becomes high level and P
Channel MO5FETQI 6 is turned off. This invalidates the above-mentioned overshoot input, thereby preventing erroneous silicon signature reading.

In this embodiment, the word line WO as shown in FIG. 1 is used as a write test area of the EFROM with the one-time program configuration as described above, instead of being used for the silicon signature as described above. You can also use it as That is, one address terminal of the X system is provided with a high voltage detection circuit VH as described above to form a three-value input configuration,
By supplying the above-mentioned high voltage thereto, the word line wo is selected. In this configuration, the Y
The system address signal needs to be changed arbitrarily to enable writing/reading to/from any memory cell coupled to the word line WO. Therefore, it is assumed that another X-system address signal is supplied to the decoder circuit G1 shown in FIG. Furthermore, since the control signal OE is set to high level during writing and set to low level during reading,
It is sufficient to supply only the chimp selection signal ce to the input of the decoder circuit G1.

FIG. 3 shows a circuit diagram of an embodiment of a level conversion circuit used in the EFROM.

The level conversion circuit of this embodiment is 0MO5 (complementary type MO
3) It is directed to the EFROM of the configuration.

That is, in order to supply a high voltage selection level to the word line for a write operation, instead of the configuration using a depletion type MOS FET as shown in FIG. Use. The P-channel type load MO5FET Q20 and the N-channel type drive MOSFETs Q22, Q23, etc. constitute an address decoder circuit. In this example, the drive MOSFET
Between Q22 and load MOSFET Q20, cut MOS
FETQ21 is provided. Cut MOS FETQ
21, the power supply voltage Vcc is constantly supplied to its gate.

The level conversion circuit consists of a P-channel MO5FETQ24 that operates with a high voltage vpp as an operating voltage, and an N-channel MO5FETQ24 that operates with a high voltage vpp as an operating voltage.
The basic configuration is a CMOS inverter circuit consisting of OSFETQ25. This CMOS inverter circuit (Q24.
Q25) receives the output signal of the address decoder circuit and forms a selection signal for word hiw1. Operating voltage V
l) The CMOS inverter circuit (Q24.Q2
5) A P-channel MO5FETQ26 is provided between the human power and the high voltage Vp1). This P channel M
The gate of OSFETQ26 is connected to the output signal (word line W
l) is supplied.

When the output signal of the address decoder circuit is at a low level such as the ground potential of the circuit, the N-channel MOSFET Q2
5 is turned off, the P-channel MOSFET Q24 is turned on, and the word line W1 is set to a high level such as the high voltage vpp. On the other hand, when the output signal of the address decoder circuit is at a high level such as the power supply voltage Vcc of the circuit, the N-channel MOSFET Q25 is turned on and the word IWI is set at a low level close to the ground potential of the circuit. In response to this low-level signal, P-channel MOSFET Q26 turns on, so the input level of the CMOS inverter circuit (Q24, Q25) becomes higher than the power supply voltage Vcc, and N-channel MOSFET Q26 turns on.
25 conductance thicker (, P channel MOSF
Feedback is applied to reduce the conductance of ETQ24, and due to the on state of P channel MOSFETQ26, P channel MO3FBTQ24 is completely turned off. At this time, the drain and source of the cut MOSFET Q21 are reversed and the cut MOSFET Q21 is turned off due to the on state of the P-channel MOSFET Q26, and the high voltage Vp
Direct current can be prevented from flowing from ρ toward the power supply voltage Vcc.

FIG. 4 shows a circuit diagram of another embodiment of the level conversion circuit.

In this example, the above-mentioned I-MOSFETQ33 is
It is provided between the output of the address decoder circuit and the input of the CMOS inverter circuit (Q34°Q35) constituting the level conversion circuit. In this configuration, the output signal of the address decoder circuit is connected to the cut MOSFET which acts as a resistance element.
Since the signal is transmitted to the level conversion circuit via the ETQ33, the circuit of the embodiment shown in FIG. 3 can operate at higher speed.

FIG. 5 shows a circuit diagram of another embodiment of the high voltage detection circuit VH.

In this embodiment, the power supply voltage Vcc is used as the operating voltage, and the P-channel MOSFET QI is switch-controlled by the output signal of the Nant gate circuit G1 similar to the above.
6 and inverter configuration N-channel MOSFETQ1
7 and Q19 are provided in series. Above MOSFETQI
7 acts as a load resistance by having its gate and drain commonly connected, and the N-channel MO5F
The voltage of terminal A9 is supplied to the gate of ETQ19. With this configuration, a high input impedance can be achieved because no direct current flows from the terminal A9.

The conductance of MOSFET QI 9 increases according to the voltage supplied from terminal A9.Therefore, the conductance ratio of MOSFET QI 7 and Q19 is opposite to that in the case of FIG. When the voltage is at a relatively low potential such as approximately 5V, the output voltage is higher than the logic threshold voltage of the inverter circuit N1, and when the voltage supplied to terminal A9 is a high voltage such as approximately 10V, the output voltage is higher than the logic threshold voltage of the inverter circuit N1. It is made to be lower than the logic threshold voltage of N1.

Also, in this configuration, since the signal levels are reversed, an inverter circuit N3 is added, a signal NS for disabling the operation of the X address decoder circuit is output from the inverter circuit N2, and a signal NS is output from the inverter circuit N3 to the word line WO. Outputs the selection signal.

The effects obtained from the above examples are as follows. In other words, (1) The operation of the high voltage detection circuit that receives a high voltage higher than the power supply voltage supplied from a specific external terminal can be enabled/disabled by other external terminals when high voltage is supplied from the specific external terminal. By controlling the output of a decoder circuit that decodes the levels of multiple input signals supplied from Since the output of the decoder circuit can invalidate the operation, it is possible to realize a highly reliable muscle voltage detection operation.

(2) According to (11) above, it is possible to realize silicon signature read/normal read with high reliability.

(3) MO whose switch is controlled by a decode signal for input signals from other terminals other than the terminal that inputs the ternary level
By inserting the S FET into a voltage dividing circuit for high voltage detection, it is possible to suppress wasteful current consumption.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples (although it is possible to make various changes without departing from the gist of the invention). For example, a circuit that controls the effective/disabled operation of a high voltage detection circuit is provided with a gate circuit at the output section of the high voltage detection circuit, and the gate circuit is connected to the decoder circuit as described above. The high voltage detection circuit may have a configuration in which a plurality of MOSFETs in the form of diodes are connected in series, and the high voltage supplied from a specific terminal is level-shifted, and the logic threshold voltage is used as the reference voltage. The high voltage detection circuit may be configured to be supplied to a voltage comparison circuit such as an inverter circuit that performs a voltage comparison operation.As described above, the specific configuration of the high voltage detection circuit can take various embodiments.

In addition, the input signal supplied to the decoder circuit that controls the enable/disable of the operation of the high voltage detection circuit is set to a fixed level in the operation mode when high voltage is supplied to the high voltage detection circuit. It can be anything.

Although the invention made by the present inventor is applied to an EPROM device, which is the background field of application, it is not limited to this, and includes, for example, high voltages higher than the power supply voltage as described above. It can be widely used in various semiconductor integrated circuit devices equipped with three-value input circuits.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, the operation of the high voltage detection circuit that receives a high voltage higher than the power supply voltage supplied from a specific external terminal is enabled/disabled when the high voltage is supplied from another external terminal when the high voltage is supplied from the specific external terminal. By controlling the output of a decoder circuit that decodes multiple human input signal levels,
Even if an overshoot that is considered to be a high voltage occurs at the specific external terminal mentioned above, the operation can be nullified by the output of the decoder circuit that receives the level of other input signals, so it is possible to use a highly reliable high voltage. Detection operation can be realized.

[Brief explanation of the drawing]

FIG. 1 is an internal configuration block diagram showing an embodiment of an EPROM device to which the present invention is applied, and FIG. 2 is a circuit diagram showing an embodiment of a high voltage detection circuit and a decoder circuit that controls its operation. Fig. 3 is a circuit diagram showing one embodiment of the level conversion circuit, Fig. 4 is a circuit diagram showing another embodiment of the level conversion circuit, and Fig. 5 is a high voltage detection circuit and its operation control. FIG. 3 is a circuit diagram showing another embodiment of a decoder circuit for performing the following steps. XADB・DCR・・X address buffer decoder, Y
ADB-DCR...Y address buffer decoder,
M-ARY...Memory array, DOB...Data output circuit, DIB...Data input circuit, C0NT...Control circuit, XR, YR...High voltage load circuit, VH...High voltage detection circuit, G1°, Nantes Gate circuit (decoder circuit),
C.E.B. OEB...Control buffer, ADBO~ADB i...
Address buffer diagram 1

Claims (1)

[Claims] 1. A high voltage detection circuit that receives a high voltage higher than the power supply voltage supplied from a specific external terminal, and a high voltage detection circuit that receives a high voltage higher than the power supply voltage supplied from a specific external terminal, and a a decoder circuit that decodes a plurality of input signal levels to control effective/ineffective operation of the high voltage detection circuit. 2. A patent characterized in that the semiconductor integrated circuit device is a nonvolatile memory device, the specific external terminal is a specific address terminal, and the decoder circuit receives the remaining address signals and control signals. A semiconductor integrated circuit device according to claim 1. 3. The high voltage detection circuit according to claim 1 or 2, wherein an operating current is caused to flow through a switch MOSFET controlled by an output signal of the decoder circuit. Semiconductor integrated circuit device.