JPH0235495B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor integrated circuits, and more particularly to a reference voltage detection circuit that changes an output signal when an input signal crosses a reference voltage level within an integrated circuit.

In various electronic circuits, it may be necessary to detect the moment when an input signal crosses a predetermined reference voltage. In particular, zero-cross detectors that detect the moment when an input signal crosses a ground voltage (zero voltage) are in high demand in phase control circuits and the like. However, since normal integrated circuits (ICs) operate between the ground voltage and the power supply voltage, there was no IC chip that could detect voltages with the opposite polarity to the ground voltage or operating voltage. Since these reference voltage detectors were assembled on a printed circuit board using individual parts, there were many problems in terms of cost, reliability, miniaturization of the printed circuit board, etc.

In general, the reference voltage in logic circuits such as inverters is the given power supply voltage V _SS (OV) and V _DD (C
- Positive polarity for MOS and N-MOS, negative polarity for P-MOS).
Furthermore, there is a certain overdrive voltage determined by process parameters and circuit constants, and the output signal will not be inverted unless the input voltage exceeds (reference voltage + overdrive voltage). Therefore, in conventional circuits, even if a zero voltage is applied as a reference voltage and a signal that changes between positive and negative is applied as an input signal, it is not possible to accurately detect the point where the input signal crosses the zero voltage. Furthermore, it is also impossible to use a reference voltage with a polarity opposite to the operating voltage due to the structure of the integrated circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a reference voltage detection circuit that can detect with high precision even the moment when an input signal crosses a ground voltage within an integrated circuit.

According to the invention, a depletion mode insulated gate field effect transistor (IG-FET) is included;
an input circuit including a pair of voltage divider circuits having substantially the same configuration;
By using it as a reference voltage circuit and comparing and amplifying each output with a comparator circuit, stable and highly accurate reference voltage detection can be achieved. Despite having a simple and economical circuit configuration, extremely stable operation can be achieved even with power supply voltage fluctuations and temperature changes. Furthermore, all the components
It can be configured with IG-FETs and can be manufactured using conventional processes. By configuring the input circuit and reference voltage circuit using only depletion mode IG-FETs, parameter fluctuations during the manufacturing process can be avoided.
It is stable against variations in exposure and etching processes, is easy to manufacture, and can have a high yield.

A description will be given below along with examples. In FIG. 1, the zero voltage detection circuit includes an input circuit 1, a reference voltage circuit 2, a comparison circuit 3, and an output buffer circuit 4. The input circuit 1 and the reference voltage circuit 2 receive the input voltage V _IN of the input terminal 5 and the ground voltage V _G4 of the V _SS line = 0,
Comparison voltage _IN within the working voltage range (V _SS −V _DD ),
Generates reference voltage V _REF . _IN is an inverted signal that changes in the opposite direction to V _IN . Depression IG
FET Q ₁ and Q ₃ have exactly the same characteristics (Q ₁ =
Q ₃ ), which is zero biased and exhibits a predetermined resistance value.
Depletion IG-FETs Q ₂ and Q ₄ also have exactly the same characteristics (Q ₂ = Q ₄ ), and their gates are connected to input terminal 5 and the ground V _SS line, and V _IN , V _G4 =
Indicates the impedance corresponding to OV. Q ₁ −Q ₂ ,
Each series connection of Q ₃ −Q ₄ constitutes a voltage divider circuit. For example, as shown in Figure 2, IG-FET Q ₁ , Q ₂ ,
Q ₃ and Q ₄ are arranged close to each other and along the same direction within the IC board. Q ₁ and Q ₃ have the same design dimensions,
Q ₂ and Q ₄ also have the same design dimensions. power line 18,
Connected to the ground line 19, the diffusion regions 11, 11',
13, 13' are formed, and a diffusion region 12, 12' is further formed in the middle. A gate electrode 15 is provided on the region that becomes the channel between the diffusion regions.
15', 16, 16' are formed. number 1
Parts indicated by 1, 12, 13, 15, 16 and number 1
The parts indicated by 1', 12', 13', 15', and 16' have the same dimensions, are made of the same material, and are made by the same process. Therefore, excessive or insufficient exposure process or etching process,
Variations in process parameters such as mask alignment errors affect each transistor equally and do not affect the relative relationship of voltage division. Therefore, manufacturing is easy and high yield can be obtained. Also, transistor Q ₁ ,
Q ₂ , Q ₃ , and Q ₄ are all of the depletion mode type and work as simple voltage divider circuits, so they are not easily affected by fluctuations in operating conditions. The voltage division ratio is determined only by the channel size ratio (W/L) of each transistor, and is not easily affected by power supply voltage fluctuations, temperature changes, etc., and extremely stable and highly accurate operation can be obtained.

The depletion IG-FETs Q ₂₂ and Q ₄ are designed to exhibit a finite source-drain impedance when a predetermined gate bias including reverse bias is applied. Furthermore, depression IG-
The design constants of each transistor are selected so that the divided voltages of FETs Q ₁ -Q ₂ and Q ₃ -Q ₄ are appropriate voltages for operating the comparator circuit 3 in the subsequent stage. Comparison circuit 3
compares the comparison voltage signal _IN and the reference voltage signal V _REF .

The series connection of depletion IG-FET Q ₇ and enhancement IG-FET Q ₈ is used as a current stabilizing IG.
- Supply constant voltage bias to FET Q ₁₅ . In other words, IG-FET Q ₇ , which is directly connected to the gate and drain, supplies a constant current to IG-FET Q ₈ , which is directly connected to the gate and drain, and IG-FET Q ₈ , which acts as a constant voltage element, supplies the stabilized gate bias to FET Q _15. supply to FET
The constant current flowing through _Q15 flows through the branches of _Q11 - _Q12 and _Q13 - _Q14 , forming a current switching type differential amplifier.
Q ₁₁ and Q ₁₃ are zero-biased depressions
IG-FET, Q ₁₂ and Q ₁₄ are enhancement IG-FETs that receive each input signal to the differential amplifier.
It is. The two outputs of the current switching type differential amplifier change in opposite directions.

Output buffer circuit 4 is enhancement IG-
FET Q ₁₆ , Q ₁₇ , Q ₁₉ and depletion IG
FETQ ₁₈ , and receives the two outputs of the differential amplifier to generate a rectangular wave output voltage having a desired voltage swing width.

Referring to FIG. 3, the case of an N-channel MOS-IC will be explained as an example. Consider that the input voltage V _IN gradually increases from negative polarity to positive polarity. V _IN
While _Q2 has negative polarity, the resistance of Q2 is higher than the resistance of _Q4 , and _IN is at a higher level than V _REF . _IN is Q ₁₂
Q ₁₆ and Q ₁₉ are turned off, and the voltage V _OUT at the output terminal 6 becomes high level (V _DD ). When the input voltage crosses zero voltage, the impedance of Q ₂ becomes smaller than the impedance of Q ₄ , raising the output level of Q ₁₂ and lowering the output level of Q ₁₄ . Therefore, _Q16 is turned on, _Q17 is turned off, and _Q19 is turned on, and the output voltage V _OUT falls to a low level close to V _SS =OV.

In other words, although the reference voltage V _REF of the comparator circuit is not OV, _IN crosses V _REF exactly when V _IN crosses OV, and an inverted output waveform is obtained. IG-
FETQ ₂ and Q ₄ have exactly the same configuration, and IG-FET
Since Q ₁ and Q ₃ have exactly the same configuration, the comparison voltage _IN also crosses the reference voltage V _REF at the moment the input voltage V _IN crosses the reference voltage OV from positive to negative or from negative to positive.

Assume now that a sine wave voltage is applied to the input terminal 5 as shown in FIG. The period of t ₁ with V _IN > 0 is
V _IN > V _REF , and V _OUT outputs a high level close to V _DD . V _IN crosses OV and V _IN < 0 at t _2
IN < V _REF from the moment it enters the period, the comparator is inverted and V _OUT becomes low level. Therefore t ₁ =
t ₂ , and an output signal that precisely matches the phase of the input signal is obtained. The output rectangular wave signal can be used for a wide range of purposes including timing and phase control of logic circuits and memory circuits on the same chip.

Since zero voltage can be detected accurately and the output signal can be quickly changed, dead time in the circuit while the signal level is changing can be eliminated, and the degree of freedom in circuit design can be greatly increased.

All the components of this embodiment are designed using IG-FETs, and can be manufactured in the same process as other circuit components on the IC chip, and once the mask is completed, the manufacturing process is the same as the conventional one.

In the above embodiment, the reference voltage was OV, but
Reference voltages other than OV can also be easily detected.

FIG. 5 shows another embodiment. Resistors R ₁ and R ₃ are used instead of IG-FETs Q ₁ and Q ₃ in the embodiment shown in FIG.
This embodiment is the same as the embodiment shown in FIG. 1, except that the gate of IG-FET Q ₄ is led to the reference voltage input terminal 7 using the following. In this case as well, resistors R ₁ and R ₃ should be made completely equal and
It is important to create IG-FETs Q ₂ and Q ₄ exactly the same. Resistors R ₁ and R ₃ are, for example, diffused resistors,
It can be formed using ion implantation resistor or polysilicon resistor. V _G4 voltage, for example, minus 1.0V or positive
By setting a specific inverted output to the expected value, such as 1.5V, it can be freely adjusted, making it possible to use a ``minus 1.0V detector'' or a ``plus 1.5V detector.'' In this case, the reference voltage V _G4 can be supplied either by creating it internally or by providing an external V _G4 terminal and supplying the reference voltage from the outside.

Incidentally, as a protection means for inputting an input signal including a voltage having a polarity opposite to the operating voltage to the IC chip, a configuration as shown in FIG. 6 may be adopted, for example.
In the N-channel MOS-IC shown in the figure, V _IN and
A lateral bipolar transistor made of N regions 21 and 22P substrates is formed between the N region and V _DD . When V _IN becomes a negative voltage, the electrons injected from the N region 21 do not spread into the substrate and move to the N region 21.
The negative voltage V _IN is collected as is for input.
Applied to the gate of IG-FET Q ₂ , its source
Adjust the drain-to-drain resistance. In the case of the embodiment shown in FIG.
If the protective means shown in the figure is provided, a reference voltage with the opposite polarity to the operating voltage can also be input.

Although the present invention has been described above with reference to the embodiments, it will be obvious to those skilled in the art that various modifications, combinations, and changes can be made.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a partial top view of an IC chip incorporating the circuit of FIG. 1,
3 and 4 are characteristic diagrams of the circuit shown in FIG. 1, FIG. 5 is a circuit diagram of another embodiment, and FIG. 6 is a sectional view showing protection means for the input terminal. Explanation of symbols, 1... Input circuit, 2... Reference voltage circuit, 3... Comparison circuit, 4... Output buffer circuit, 5...
Input terminal, 6...output terminal.

Claims (1)

[Claims] 1. In an integrated circuit that is supplied with a predetermined power supply voltage VDD and a ground voltage VSS and operates in a voltage range between the two voltages, (a) an input circuit that includes a voltage level exceeding the above voltage range; a reference voltage circuit for receiving a selected reference voltage signal, both circuits including voltage dividing circuits of substantially the same configuration including depletion mode field effect transistors; (b) the input circuit is , an input circuit that generates a comparison voltage signal within the voltage range (VSS, VDD) according to an input signal, and the input signal is applied to one gate of a depletion mode field effect transistor connected in series. (c) The reference voltage circuit generates a comparison voltage signal within the voltage range (VSS, VDD) according to the reference voltage signal, and includes a depletion mode field effect transistor connected in series with the reference voltage signal. A reference voltage circuit that is applied to one gate, and (d) receives the comparison voltage signal and the reference voltage signal, and detects and amplifies the moment the voltage of the input signal crosses the reference voltage. A reference voltage detector comprising: an amplifier circuit that generates a rectangular wave within the above voltage range.