JPH0234906A - Semiconductor substrate - Google Patents
Semiconductor substrateInfo
- Publication number
- JPH0234906A JPH0234906A JP18621488A JP18621488A JPH0234906A JP H0234906 A JPH0234906 A JP H0234906A JP 18621488 A JP18621488 A JP 18621488A JP 18621488 A JP18621488 A JP 18621488A JP H0234906 A JPH0234906 A JP H0234906A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- recognition mark
- semiconductor
- orientation flat
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 81
- 239000000758 substrate Substances 0.000 title claims abstract description 62
- 239000013078 crystal Substances 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 238000001514 detection method Methods 0.000 abstract description 3
- 238000011084 recovery Methods 0.000 abstract description 2
- 230000011514 reflex Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000002238 attenuated effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000007858 starting material Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の出発材料である半導体基板に関し
、特に形状を改良した半導体基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor substrate that is a starting material for a semiconductor device, and particularly to a semiconductor substrate whose shape has been improved.
従来、半導体装置の出発材料である半導体基板は、第３
図に示すように円板の一端を直線状に切断加工した形状
となっていた。この直線部５はオリエンティション・フ
ラットと呼ばれ、半導体基板の結晶方位を規定するもの
である。通常、半導体装置のトランジスタ特性は、トラ
ンジスタを形成する半導体基板の結晶方位によって変わ
るためにトランジスタの形成は一定の結晶方位に行う必
要があり、通常オリエンティション・フラットは、半導
体装置製造工程中のフォトリソグラフィ工程のフォトマ
スクと半導体基板の目合せの基準線となっている。Conventionally, semiconductor substrates, which are the starting materials for semiconductor devices, are
As shown in the figure, one end of the disk was cut into a straight line. This straight portion 5 is called an orientation flat, and defines the crystal orientation of the semiconductor substrate. Normally, the transistor characteristics of a semiconductor device vary depending on the crystal orientation of the semiconductor substrate on which the transistor is formed, so it is necessary to form a transistor in a certain crystal orientation. It serves as a reference line for alignment of the photomask and semiconductor substrate in the lithography process.
しかしながら上述した従来の半導体基板は、円板の一端
を切断した形状となっているので、以下のような種々の
欠点がある。半導体基板は半導体装置の製造工程中に、
くり返し高温の熱処理を受けるが、この熱処理時の応力
はオリエンティション・フラット部に集中し、オリエン
ティション・フラット部から結晶欠陥が発生しやすくな
る。この結晶欠陥は、トランジスタ特性の劣化を招き半
導体装置の歩留りを低下させる。However, the conventional semiconductor substrate described above has the shape of a disk with one end cut off, and therefore has various drawbacks as described below. During the manufacturing process of semiconductor devices, semiconductor substrates are
The material is repeatedly subjected to high-temperature heat treatment, but the stress during this heat treatment is concentrated in the orientation flat area, making crystal defects more likely to occur from the orientation flat area. These crystal defects cause deterioration of transistor characteristics and reduce the yield of semiconductor devices.
また一方、オリエンティション・フラットを有するがた
めに半導体装置の製造装置の半導体基板保持治具への装
填前に半導体基板のオリエンティション・フラットを一
定方向に整列させる必要が有る場合がある。第４図は、
半導体基板の高温熱処理時に使用する７石英製半導体基
板保持治具による、半導体基板の保持状態の説明図であ
る。第４図（ａ）に示すようにこの半導体基板保持治具
８において、半導体基板１は３本の石英棒６のそれぞれ
に切られた３つの溝７によって保持される。On the other hand, since the semiconductor substrate has an orientation flat, it may be necessary to align the orientation flat of the semiconductor substrate in a certain direction before loading it into a semiconductor substrate holding jig of a semiconductor device manufacturing apparatus. Figure 4 shows
FIG. 7 is an explanatory diagram of a state in which a semiconductor substrate is held by a quartz semiconductor substrate holding jig used during high-temperature heat treatment of a semiconductor substrate. As shown in FIG. 4(a), in this semiconductor substrate holding jig 8, the semiconductor substrate 1 is held by three grooves 7 cut in each of three quartz rods 6.
しかしながら第４図（ｂ）に示すように、半導体基板１
のオリエンティション・フラット部が溝にかかった場合
、半導体基板の保持が十分できず、不安定な状態となる
。したがって、半導体基板の半導体基板保持治具への装
填前に半導体基板のオリエンティション・フラット部が
溝部にかからないように、半導体基板のオリエンティシ
ョン・フラット部を整列させる必要が生じる。However, as shown in FIG. 4(b), the semiconductor substrate 1
If the orientation flat part of the semiconductor substrate is caught in the groove, the semiconductor substrate cannot be held sufficiently, resulting in an unstable state. Therefore, before loading the semiconductor substrate into the semiconductor substrate holding jig, it is necessary to align the orientation flat portions of the semiconductor substrate so that the orientation flat portions of the semiconductor substrate do not overlap the groove portions.
以上説明した欠点以外にも、オリエンティション・フラ
ットを有する半導体基板は、半導体装置の製作可能なる
面積が小さくなる。又、フォトリソグラフィー工程にお
ける感光性樹脂の回転塗布工程において、オリエンティ
ション・フラット部近傍の塗布膜厚のむらが生じるなど
の種々の欠点を有する。In addition to the drawbacks described above, a semiconductor substrate having an orientation flat reduces the area in which a semiconductor device can be manufactured. Further, in the spin coating process of photosensitive resin in the photolithography process, there are various drawbacks such as uneven coating film thickness near the orientation flat portion.
本発明の半導体基板は、半導体基板の半導体装置形成面
となる一主面あるいは、半導体装置形成面に対向する他
の主面の外周部に半導体基板の結晶方位認識用の認識マ
ークを有し、且つ、該半導体基板の平面形状を真円状と
したことを特徴とする。The semiconductor substrate of the present invention has a recognition mark for recognizing the crystal orientation of the semiconductor substrate on the outer periphery of one principal surface serving as the semiconductor device formation surface or the other principal surface opposite to the semiconductor device formation surface, Further, the semiconductor substrate is characterized in that the planar shape of the semiconductor substrate is a perfect circle.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を示す半導体基板の平面図で
ある。ここで半導体基板１は真円形をしており、半導体
装置形成面外周部から内側に１ｍｍの位置には、長さ３
ｍｍ、深さ１００μｍ１間隔３鵬の３本の溝から成る認
識マーク２がレーザーマーク法により印字されている。FIG. 1 is a plan view of a semiconductor substrate showing an embodiment of the present invention. Here, the semiconductor substrate 1 has a perfect circular shape, and at a position 1 mm inward from the outer periphery of the semiconductor device forming surface, there is a length of 3 mm.
A recognition mark 2 consisting of three grooves of 1 mm and 100 μm deep and 3 grooves apart is printed by a laser mark method.
この認識マーク２は、従来の半導体基板のオリエンティ
ション・フラットに代るものであり、（１００）単結晶
シリコン基板の場合には通常Ｃｏ Ｏ１）方向端部に円
弧状に記入する。この認識マーク７は、半導体装置製造
工程中の最初のリソグラフィー工程においては、半導体
基板とフォトマスクの目合せの基準となるもので、この
認識マーク２の位置に応じて、半導体基板へのパターン
の焼きつけ方向を決定する。また、２回目以降のリソグ
ラフィー工程においては、半導体基板に焼きつけられた
パターンとフォトマスクの目合せの前のプリアライメン
トとして、半導体基板上のパターンの方向とフォトマス
クの方向を合せるための認識マークとして用いる。この
認識マークによる半導体基板の位置合せは反射式フォト
センサーによって行う、第２図に本発明の半導体基板に
印字された認識マークの検出装置の概略構成図を示す。This recognition mark 2 replaces the orientation flat of a conventional semiconductor substrate, and in the case of a (100) single crystal silicon substrate, it is usually written in an arc shape at the end in the Co O1) direction. This recognition mark 7 serves as a reference for alignment between the semiconductor substrate and the photomask in the first lithography process in the semiconductor device manufacturing process, and the pattern on the semiconductor substrate is determined according to the position of this recognition mark 2. Determine the burning direction. In addition, in the second and subsequent lithography processes, it is used as a pre-alignment before aligning the pattern printed on the semiconductor substrate with the photomask, and as a recognition mark to align the direction of the pattern on the semiconductor substrate with the direction of the photomask. use The alignment of the semiconductor substrate using the recognition mark is performed by a reflective photosensor. FIG. 2 shows a schematic configuration diagram of a detection apparatus for a recognition mark printed on a semiconductor substrate according to the present invention.
本装置において、認識マークの検出は以下のように行な
われる。まず、半導体基板１を、認識マーク検出装置回
転ステージ３上に回転ステージの回転中心と半導体基板
の中心が一致するよう配置する。回転ステージ上には回
転ステージ中心から一定の距離の位置に反射式フォトセ
ンサー４が配置されておりこの距離は半導体基板中心か
ら認識マークの距離に等しくしている。次いで回転ステ
ージを数十ＲＰＭから数百ＲＰＭの速度で回転させる。In this device, recognition marks are detected as follows. First, the semiconductor substrate 1 is placed on the rotation stage 3 of the recognition mark detection device so that the rotation center of the rotation stage and the center of the semiconductor substrate coincide. A reflective photosensor 4 is placed on the rotating stage at a constant distance from the center of the rotating stage, and this distance is made equal to the distance of the recognition mark from the center of the semiconductor substrate. The rotary stage is then rotated at a speed of several tens of RPM to several hundred RPM.
この時、反射式フォトセンサー下を半導体基板上の認識
マークが通過すると反射光が散乱し反射光強度が減衰す
る。ここで認識マークはある間隔持った３本の溝より形
成されているため、反射光の強度は減衰。At this time, when the recognition mark on the semiconductor substrate passes under the reflective photosensor, the reflected light is scattered and the intensity of the reflected light is attenuated. Since the recognition mark is formed by three grooves spaced apart from each other, the intensity of the reflected light is attenuated.
回復と３度繰り返す。このパターンを認識することによ
り、認識マークの位置検出が可能となる。Recovery and repeat 3 times. By recognizing this pattern, the position of the recognition mark can be detected.
以上説明したように本発明は、半導体基板結晶面方位認
識用の認識マークを半導体装置形成面となる半導体基板
の一主面、あるいは−主面に対向する他の主面の外周部
に入れることにより、従来の半導体基板にあったオリエ
ンテーション・フラットを無くすことが可能となり、半
導体基板の形状を真円状にすることができる。これによ
り、オリエンティション・フラットをいれるために切断
されていた部分にも半導体装置の形成が可能となり、半
導体基板の半導体装置の形成可能なる面積が増える。ま
た、半導体基板の高温熱処理時にオリエンティション・
フラット部から発生する熱応力による結晶欠陥の発生が
ない。さらに半導体装置の製造装置の半導体基板保持治
具への装填前に、半導体基板のオリエンティション・フ
ラット部の整列の必要がなくなり、半導体装置の製造装
置の簡略化が可能となる。As explained above, the present invention provides a method for placing a recognition mark for recognizing the crystal plane orientation of a semiconductor substrate on the outer periphery of one main surface of the semiconductor substrate, which is a surface on which a semiconductor device is formed, or on the other main surface opposite to the -main surface. As a result, it is possible to eliminate the orientation flat that is present in conventional semiconductor substrates, and the shape of the semiconductor substrate can be made into a perfect circle. As a result, it becomes possible to form a semiconductor device even in a portion that has been cut to include an orientation flat, increasing the area of the semiconductor substrate in which a semiconductor device can be formed. Also, during high-temperature heat treatment of semiconductor substrates, orientation and
No crystal defects occur due to thermal stress generated from flat parts. Furthermore, there is no need to align the orientation flat portions of the semiconductor substrates before loading them into the semiconductor substrate holding jig of the semiconductor device manufacturing apparatus, and the semiconductor device manufacturing apparatus can be simplified.
回転ステージ、４・・・・・・反射式フォトセンサー５
・−・・・・オリエンティション・フラット、６・・・
・・・石英棒、７・・・・・・溝、８・・・・・・半導
体基板保持治具。Rotating stage, 4... Reflective photo sensor 5
・－・・・Orientation flat, 6...
...Quartz rod, 7...Groove, 8...Semiconductor substrate holding jig.
Claims (1)
半導体装置形成面に対向する他の主面の外周部に、半導
体基板の結晶方位認識用の認識マークを有し、且つ該半
導体基板の平面形状を真円状としたことを特徴とする半
導体基板。One main surface of the semiconductor substrate that is the surface on which the semiconductor device is formed, or
A semiconductor substrate having a recognition mark for recognizing the crystal orientation of the semiconductor substrate on the outer periphery of the other main surface facing the semiconductor device forming surface, and the semiconductor substrate having a perfect circular planar shape. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18621488A JPH0234906A (en) | 1988-07-25 | 1988-07-25 | Semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18621488A JPH0234906A (en) | 1988-07-25 | 1988-07-25 | Semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0234906A true JPH0234906A (en) | 1990-02-05 |
Family
ID=16184367
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18621488A Pending JPH0234906A (en) | 1988-07-25 | 1988-07-25 | Semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0234906A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5716876A (en) * | 1995-10-31 | 1998-02-10 | Nec Corporation | Method for manufacturing completely circular semiconductor wafers |
| CN103854991A (en) * | 2012-12-04 | 2014-06-11 | 不二越机械工业株式会社 | Method of manufacturing semiconductor wafers |
-
1988
- 1988-07-25 JP JP18621488A patent/JPH0234906A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5716876A (en) * | 1995-10-31 | 1998-02-10 | Nec Corporation | Method for manufacturing completely circular semiconductor wafers |
| CN103854991A (en) * | 2012-12-04 | 2014-06-11 | 不二越机械工业株式会社 | Method of manufacturing semiconductor wafers |
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