JPH0234543B2 - REBERUHENKANKAIRO - Google Patents

Description

Detailed Description of the Invention (Industrial Application Field) The present invention is a method for adjusting the level of a frequency modulation signal that is performed when transmitting a pulsed control data signal using a wireless transmission path in data communication, etc. It relates to a circuit that converts levels so that stable frequency modulation is performed.

(Prior art and problems) Conventionally, when frequency modulation is performed using a control signal, a voltage controlled oscillator is generally used, and the output oscillation frequency is changed by changing the barrier capacitance of the varactor diode using the control voltage. .

FIG. 3 is a diagram showing the change characteristics of the output frequency with respect to the control voltage of the varactor diode. In the diagram
V _N is the modulation center control voltage, and the oscillation frequency at this time is the modulation center frequency f ₀ . That is, a DC bias voltage is applied so that the modulation voltage changes around V _N so that the modulation operation is performed within the optimum operating range of the varactor diode.

Therefore, the voltage when no modulation signal is applied is
V _N and the oscillation frequency is f ₀ . For this reason, the fourth
As shown in the figure, a coupling capacitor 2 is connected between the output terminal 31 of the control logic circuit 28 that generates a control signal, which is a modulation signal, and the input terminal 32 of the frequency modulator 30.
They are joined by 9.

As shown in FIG. 5a, the output waveform of the control logic circuit 28 is a pulse waveform having a constant voltage peak value (for example, 5 V in a circuit using a power supply voltage of 5 V) with reference to 0 volts.
That is, the reference level of the part where the pulse signal train does not exist and the low level when the pulse signal exists have the same waveform.

Now, when a control signal with such a waveform is applied to the input terminal 32 of the frequency modulator via the coupling capacitor 29, the voltage waveform at the input terminal 32 transiently changes to the fifth waveform due to the influence of the charge charged in the coupling capacitor 29.
The waveform will be as shown in Figure b. This is a phenomenon normally observed when a pulse train signal as shown in FIG. 5a is intermittently applied to a coupling circuit using a capacitor. However, the waveform that is originally desirable for the frequency modulator circuit is the waveform shown in FIG. 5c. Therefore, in Figure b, a voltage higher than the wavefront value V _P of the waveform in Figure c will cause overmodulation beyond a predetermined frequency range and will interfere with other adjacent frequency channels. Furthermore, as the pulse waveform is raised, the wave bottom value V _B becomes closer to the modulation center control voltage V _N , increasing the possibility that it will be applied to the modulation threshold voltage, making it easier to cause reading errors during demodulation. In order to prevent interference to other channels, there are methods to set the frequency value of the frequency channel to a large value for safety, or to install a clip circuit in the input circuit of the frequency modulator, but it is not possible to widen the frequency width of one channel. There is a problem from the point of view of frequency band utilization efficiency, and it is uneconomical to provide a clip circuit, and even if a clip circuit is provided, the wave bottom value approaches the threshold level and reading errors are likely to occur during demodulation. There is a problem in that the drawbacks of becoming unresolved remain as they are without being improved.

(Means for Solving the Problems) In order to solve the above-mentioned problems in the prior art, the present invention frequency-modulates the output waveform of a control logic circuit through a coupling capacitor to which a DC bias voltage is applied. In order to avoid the waveform shown in Fig. 5b even when added to the input circuit of the device, the output waveform of the control logic circuit is set in advance so that the reference value of the pulse waveform signal is set as shown in Fig. 5c. It is an attempt to provide a level conversion circuit that converts between high level and low level.

The conversion circuit of the present invention is a level conversion circuit having the following configuration in order to achieve the above object.

That is, it consists of an exclusive OR circuit having two input terminals and an inverting circuit that receives an output signal of the exclusive OR circuit and inverts the level thereof, and uses the output of the inverting circuit as the first output signal. a two-signal output circuit that directly uses one input signal of the two input terminals of the exclusive OR circuit as a second output signal; and a two-signal output circuit that receives the output of the two-signal output circuit at the two input terminals and outputs it to one of the two input terminals. The output potential when a high level potential is applied to the other and the output potential when the high level potential is applied to both of the two input terminals and the output potential when the high level potential is applied to both of the two input terminals. This is a level conversion circuit consisting of a resistor circuit that outputs a voltage at an intermediate potential of the output level when a low-level potential is applied, and a voltage follower circuit that receives and outputs the output voltage of the resistor circuit. .

(Embodiment of the Invention) FIG. 1 shows a circuit configuration of an embodiment of a level conversion circuit according to the present invention.

FIG. 2 shows signal waveforms at various parts in the circuit of FIG. 1. FIG. 2a shows an enable signal applied to input terminal 6 in FIG.
This is a signal that becomes high level (for example, 5V) only when a pulse signal train as shown in FIG. b is applied.

Figure b shows the input waveform to the input terminal 7, and at the same time, it is also the waveform at the terminal 9 since it is directly output. Figure c is the waveform at terminal 8. The two-signal output circuit 1 includes an exclusive OR circuit 4 and an inversion circuit 5, and operates as follows. When the input terminal 6 is at a high level, when a high level is applied to the input terminal 7, the terminal 9 also goes to a high level and the output of the exclusive OR circuit 4 becomes a low level (for example, 0 volts), which is the inverting circuit 5. Since it is inverted and becomes a high level, the terminal 8 also becomes a high level. Similarly, when a low level is applied to the input terminal 7, the terminal 9 also becomes a low level and the output of the exclusive OR circuit 4 becomes a high level, which is inverted by the inverting circuit 5.
is at a low level.

As a result, while a high level potential is applied to input terminal 6, when a high level is applied to input terminal 7, the potentials of terminals 8 and 9 both become high level, and when a low level potential is applied to input terminal 7. When this happens, the potentials at terminals 8 and 9 both go to low level.

On the other hand, while a low level is being applied to the input terminal 6, when a low level is applied to the input terminal 7, the terminal 9 becomes a low level and the output of the exclusive OR circuit 4 becomes a low level. Inversion circuit 5
Since the signal is inverted and becomes a high level, the terminal 8 becomes a high level. Similarly, when a high level is applied to input terminal 7, terminal 9 becomes high level and terminal 8 becomes low level. As a result, when a low level is applied to the input terminal 6, one of the potentials of the terminals 8 and 9 is always at a high level and the other is at a low level. Figures 2a, b, and c show the above relationships.

The waveform of FIG.
Apply the pulse voltages shown in Figures b and c, apply a 5V power supply voltage to terminal 12, and change the values of resistor 22, resistor 23, and resistor 21 of resistor circuit 2 in Figure 1a to 3:3:1.
This is the waveform at terminal 10 when the ratio is set to , and therefore also the waveform at output terminal 11, which is the output of the voltage follower.

The waveform in FIG. 2e is the same as that in the resistor circuit 2' in FIG.
These are waveforms at the terminal 10 and the output terminal 11 when the resistance value of the resistor 27 is set to 3:2:2:3.

The voltage follower 3 is connected to the terminal 10 so as not to affect the potential setting in the resistor circuit 2 or 2'.
It has the function of receiving the potential of 1 with a high input impedance and transmitting a pulse signal to the input circuit of the frequency modulator with a low output impedance.

As a result of the above-described operation, the output waveform of the control logic circuit is at the same level as the low level of the pulse signal when no pulse signal is present, that is, the reference level, as shown in Figure 2b and Figure 5a. Therefore, if the DC voltage is supplied to circuits with different DC levels through capacitors, the waveform shown in FIG. 5B will not occur, which will cause problems in the operation of the frequency modulator.

That is, as shown in FIGS. 2d and 2e, the reference level when no pulse signal is present is between the high level and low level of the pulse signal, and this level also almost matches the average value of the levels of the pulse signal train. .
For this reason, the DC average level is constant regardless of the presence or absence of a pulse signal train, so even if it is coupled to the input circuit of the frequency modulator via a capacitor, it will not be affected by the incoming pulse signal train. As a result, the DC level does not fluctuate, and the pulse signal is directly applied to the modulation circuit with the DC bias voltage as a reference.

(Effects of the Invention) As explained above, the output signal of the conventional control logic circuit receives a pulse signal, that is, a pulse signal train, in which the reference level in the absence of a pulse signal and the low level of the pulse signal are the same. Since the signal causes the DC level to change, if it is applied to the input circuit of the frequency modulator via a capacitor, the DC level at the frequency modulator input circuit will change due to the discontinuity of the pulse signal train, causing overmodulation or modulation. However, by passing the signal through the level conversion circuit of the present invention, the reference level of the signal can be set to a level between the high level and the low level of the pulse signal. In addition, since this level almost matches the average level of the pulse signal train, even if it is applied to the input circuit of the frequency modulator via a capacitor, the DC level will not fluctuate due to the discontinuation of the pulse signal train, unlike in the conventional technology. It has the advantage of eliminating many problems.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing signal waveforms in each part of FIG. 1, and FIG. 3 is a change in output frequency with respect to control voltage of a varactor diode in a frequency modulator. Figure 4 shows the connection between the control logic circuit and the frequency modulator, Figure 5a shows the output waveform of the control logic circuit, and Figure b shows how the DC average level fluctuates due to the influence of the coupling capacitor. Figure c is a diagram showing an example of a waveform in which the DC average level does not change even when applied through a capacitor. 1...2 signal output circuit, 2,2'...resistance circuit,
3... Voltage follower circuit, 4... Exclusive OR circuit, 5... Inverting circuit, 6, 7... Input terminal,
8, 9, 10...terminal, 11...output terminal, 12
...Power terminal, 21-27...Resistor, 28...
Control logic circuit, 29... Coupling capacitor, 30
... Frequency modulator, 31 ... Control logic circuit output terminal, 32 ... Modulator input terminal.

Claims (1)

[Claims] 1. Comprised of an exclusive OR circuit having two input terminals and an inverting circuit that receives an output signal of the exclusive OR circuit and inverts the level thereof, the output of the inverting circuit is used as the first output signal, and the exclusive a two-signal output circuit that directly uses one input signal of the two input terminals of the logical OR circuit as a second output signal; The output potential when a high-level potential is applied to the other input terminal and the output potential when a low-level potential is applied to the other input terminal is low to the output potential when the high-level potential is applied to both of the two input terminals. A level conversion circuit comprising a resistor circuit that outputs a voltage at an intermediate potential of an output level when a potential of a certain level is applied, and a voltage follower circuit that receives and outputs the output voltage of the resistor circuit.