JPH0233918A - Manufacture of three-dimensional device - Google Patents
Manufacture of three-dimensional deviceInfo
- Publication number
- JPH0233918A JPH0233918A JP18437388A JP18437388A JPH0233918A JP H0233918 A JPH0233918 A JP H0233918A JP 18437388 A JP18437388 A JP 18437388A JP 18437388 A JP18437388 A JP 18437388A JP H0233918 A JPH0233918 A JP H0233918A
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- crystal silicon
- silicon layer
- layer
- apertures
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000000034 method Methods 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 27
- 239000013078 crystal Substances 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 5
- 239000012808 vapor phase Substances 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-N hydrochloric acid Substances Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は集積回路装置において三次元構造を有する素子
を製造する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing elements having a three-dimensional structure in an integrated circuit device.
従来の技術
ヘテロエピタキシャル法は、サファイア基板を用いて実
用化され、集積回路へ応用されて高速性耐ラツチアツプ
性及び耐放射線性の向上に有効であることが確認された
。The conventional heteroepitaxial method has been put to practical use using a sapphire substrate, and has been applied to integrated circuits and has been confirmed to be effective in improving high-speed latch-up resistance and radiation resistance.
酸素イオン注入による埋め込み酸化膜形成法と。A buried oxide film formation method using oxygen ion implantation.
レーザ及び電子ビームによる酸化膜上シリコン再結晶化
法と、気相エピタキシャル選択成長及び固相成長法によ
る構方向結晶成長法等の方法はいずれも開発段階の要素
技術である。Methods such as silicon recrystallization on an oxide film using laser and electron beams, and directional crystal growth using vapor phase epitaxial selective growth and solid phase growth are all elemental technologies at the development stage.
発明が解決しようとする課題
す７アイヤ基板は製造コストが高く経済性に乏しく、ま
た、多層構造とすることが困難である。Problems to be Solved by the Invention Seven-layer substrates are expensive to manufacture, are not economical, and are difficult to form into a multilayer structure.
その他の方法は、結晶性や処理能力に問題があり歩留シ
や量産性の要求を満たすことは現段階では難かしい。Other methods have problems with crystallinity and processing capacity, and it is currently difficult to meet the requirements for yield and mass production.
課題を解決するための手段
本発明は単結晶シリコン層上に集積回路を製作した後、
この上に絶縁膜を形成し、短冊状の溝を形成し更に溝の
底部に下層の単結晶シリコンに達する柱状の開口部を形
成する。この開口部より下層と異なった電導型の単結晶
シリコンを成長させ柱状の開口部を埋める。さらに所望
の電導型の単結晶シリコンを成長させ短冊状の溝を利用
して平坦な単結晶シリコン膜を絶縁膜上に形成しこの上
に再び集積回路を製作するものである。さらに多層化す
るにはこの方法をくり返す。Means for Solving the Problems The present invention provides a method for fabricating an integrated circuit on a monocrystalline silicon layer.
An insulating film is formed on this, a rectangular groove is formed, and a columnar opening reaching the underlying single crystal silicon is formed at the bottom of the groove. From this opening, single crystal silicon of a conductivity type different from that of the layer below is grown to fill the columnar opening. Furthermore, single-crystal silicon of a desired conductivity type is grown, a flat single-crystal silicon film is formed on the insulating film using the rectangular grooves, and an integrated circuit is again fabricated on this film. Repeat this method to create more layers.
作用 以下の作用が見込まれる。action The following effects are expected.
（１）単結晶シリコン層のシードとなる部分が分散して
いるだめ、この部分を避けた配線を施すことが可能であ
る。(1) Since the seed portion of the single crystal silicon layer is dispersed, it is possible to perform wiring that avoids this portion.
（２） シードを高密度にとることにより結晶性のす
ぐれた単結晶シリコン層が得られる。(2) A single-crystal silicon layer with excellent crystallinity can be obtained by providing seeds at a high density.
（３）絶縁層に形成した溝の効果によシ結晶成長の異方
性を利用して平坦な表面を持つ単結晶層が容易に得られ
る。(3) A single crystal layer with a flat surface can be easily obtained by utilizing the anisotropy of crystal growth due to the effect of the grooves formed in the insulating layer.
（４） シードを高密度にとっても、下層との絶縁性
が保たれる。(4) Even if the seeds are densely packed, insulation from the underlying layer is maintained.
実施例
第１図（＆）〜（ｄ）は絶縁層の形状説明図である。第
１図（１Ｌ）は、集積回路が形成された単結晶シリコン
層１の表面に厚さ１．５μｍの二酸化シリコン２が形成
され、この二酸化シリコンには０．８μｍの深さで幅が
Ｏ，Ｓμｍの短冊状の溝が溝間隔１．５μｍで形成され
、さらにこれらの溝の底部に単結晶シリコン層１に達す
る深さの開口部が１．５μｍの間隔で複数個形成された
ものの平面図である。また第１図（ｂ） 、 （０＞
、 （（１）はそれぞれ第１図（ａ）のＡ人′線。Embodiment FIGS. 1(&) to (d) are explanatory diagrams of the shape of the insulating layer. In FIG. 1 (1L), silicon dioxide 2 with a thickness of 1.5 μm is formed on the surface of a single crystal silicon layer 1 on which an integrated circuit is formed, and this silicon dioxide has a width of O2 with a depth of 0.8 μm. , Sμm strip-shaped grooves are formed with a groove interval of 1.5μm, and a plurality of openings with a depth reaching the single crystal silicon layer 1 are formed at 1.5μm intervals at the bottoms of these grooves. It is a diagram. Also, Fig. 1(b), (0>
, ((1) is the person A' line in Figure 1(a), respectively.
Ｂ Ｂ’線、 ＣＣ’線での断面図である。断面はく１
０ｏ〉方向にとっである。It is a sectional view taken along line BB' and line CC'. Cross section foil 1
0o> direction.
第２図（１Ｌ）〜（６）は本発明方法における工程図を
示したものである。第１電導型としてｐ型の単結晶シリ
コン層３上に素子を作製した後絶縁層４を形成し、第１
図に示した形状にエツチングする（第２図（＆））。開
口部よシエビタキシャル選択成長をさせｎ型の単結晶シ
リコン５で柱状の開口部を埋める（第２図（ｂ））。次
にｐ型の単結晶シリコンをエピタキシャル選択成長をさ
せ溝を埋めたところで気相エツチングによシ平坦化し再
び成長を続は最後に再び気相エツチングを行い絶縁層４
の表面を平坦な単結晶６で覆う（第２図（Ｃ））。この
単結晶シリコン、１上に素子を作成した後、前と同様の
方法で絶縁層Ｔを形成する（第２図（ｄ））。開口部よ
りｎ型の単結晶シリコンをエピタキシャル選択成長させ
前と同様に気相エツチングを加えることで絶縁層下を覆
う平坦な単結晶シリコン層８を形成する（第２図（θ）
）。以下これと同じ方法により任意の電導型の単結晶シ
リコン層を互いに絶縁された形で重ねてゆく。この実施
例は他の電導型の構成においても容易に製作することが
できる。Figures 2 (1L) to (6) show process diagrams in the method of the present invention. After producing an element on a p-type single crystal silicon layer 3 as a first conductivity type, an insulating layer 4 is formed, and the first
Etch it into the shape shown in the figure (Fig. 2 (&)). The columnar openings are filled with n-type single crystal silicon 5 by selectively growing via the opening (FIG. 2(b)). Next, p-type single crystal silicon is selectively grown epitaxially to fill the grooves, and then flattened by vapor phase etching.
The surface of the crystal is covered with a flat single crystal 6 (FIG. 2(C)). After forming a device on this single crystal silicon 1, an insulating layer T is formed in the same manner as before (FIG. 2(d)). N-type single crystal silicon is epitaxially selectively grown from the opening and subjected to vapor phase etching in the same manner as before to form a flat single crystal silicon layer 8 covering the bottom of the insulating layer (Fig. 2 (θ)).
). Thereafter, monocrystalline silicon layers of arbitrary conductivity types are stacked in a mutually insulated manner using the same method. This embodiment can easily be fabricated in other conductivity type configurations.
エピタキシャル成長工程では水素−ジクロール７ランー
塩酸のガス系を用い、９５０℃の温度で成長させる。ま
た途中で水素−塩酸のガス系に切り換えることにより気
相エツチングを行なう。In the epitaxial growth process, a gas system of hydrogen-dichlor 7-hydrochloric acid is used and growth is performed at a temperature of 950°C. Additionally, gas phase etching is performed by switching to a hydrogen-hydrochloric acid gas system midway through the process.
発明の詳細
な説明した様に本発明は三次元構造を持つ集積回路を現
在直ちに量産可能な装置により実現するものである。三
次元化により素子性能や集積度が大きく向上する。As described in detail, the present invention is to realize an integrated circuit having a three-dimensional structure using an apparatus that can be mass-produced immediately. Three-dimensional technology greatly improves device performance and integration.
第１図（ａ−）〜（ｄ）は絶縁層の形状説明図、第２図
（ＩＬ）〜（ｅ）は本発明方法の工程図である。
１・・・・・・単結晶シリコン層、２・・・・・・絶縁
層、３・・・・・・ｐ型単結晶シリコン層、４・・・・
・・絶縁層、５・・・・・・ｎ型単結晶シリコン層、６
・・・・・・ｐ型単結晶シリコン層、了・・・・・・絶
縁層、８・・・・・・ｎ型単結晶シリコン層。FIGS. 1(a-) to (d) are explanatory diagrams of the shape of the insulating layer, and FIGS. 2(IL) to (e) are process diagrams of the method of the present invention. 1... Single crystal silicon layer, 2... Insulating layer, 3... P-type single crystal silicon layer, 4...
...Insulating layer, 5...N-type single crystal silicon layer, 6
. . . P-type single-crystal silicon layer, Terminal: Insulating layer, 8: N-type single-crystal silicon layer.
Claims (1)
記シリコン層の上に絶縁膜を形成する工程、前記絶縁膜
に前記シリコン層に達しない深さの短冊状の溝を形成し
更に溝の底部に選択的に前記第１のシリコン層に達する
深さの開口部を形成する工程、この開口部より、結晶シ
リコンを成長させ、さらに前記絶縁膜上に第２のシリコ
ン層を形成する工程、更に前記第２のシリコン層に第２
の集積回路を製作する工程を有することを特徴とする三
次元素子製造方法。a step of manufacturing a first integrated circuit on a first silicon layer; a step of forming an insulating film on the silicon layer; forming a strip-shaped groove with a depth that does not reach the silicon layer in the insulating film; selectively forming an opening deep enough to reach the first silicon layer at the bottom of the groove; growing crystalline silicon through the opening; and further forming a second silicon layer on the insulating film. step, further adding a second silicon layer to the second silicon layer.
A method for manufacturing a tertiary element, comprising a step of manufacturing an integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18437388A JPH0233918A (en) | 1988-07-22 | 1988-07-22 | Manufacture of three-dimensional device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18437388A JPH0233918A (en) | 1988-07-22 | 1988-07-22 | Manufacture of three-dimensional device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0233918A true JPH0233918A (en) | 1990-02-05 |
Family
ID=16152078
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18437388A Pending JPH0233918A (en) | 1988-07-22 | 1988-07-22 | Manufacture of three-dimensional device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0233918A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100566675B1 (en) * | 2004-12-14 | 2006-03-31 | 삼성전자주식회사 | Semiconductor device and method of manufacturing the same |
| KR100611112B1 (en) * | 2005-01-20 | 2006-08-09 | 삼성전자주식회사 | Single crystal structure and method for forming the same, emiconductor device having the Single crystal structure and method for manufacturing the same |
| JP2011023610A (en) * | 2009-07-16 | 2011-02-03 | Toshiba Corp | Method of fabricating semiconductor device |
-
1988
- 1988-07-22 JP JP18437388A patent/JPH0233918A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100566675B1 (en) * | 2004-12-14 | 2006-03-31 | 삼성전자주식회사 | Semiconductor device and method of manufacturing the same |
| KR100611112B1 (en) * | 2005-01-20 | 2006-08-09 | 삼성전자주식회사 | Single crystal structure and method for forming the same, emiconductor device having the Single crystal structure and method for manufacturing the same |
| JP2011023610A (en) * | 2009-07-16 | 2011-02-03 | Toshiba Corp | Method of fabricating semiconductor device |
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